CN116169030A - Chip packaging structure, preparation method thereof and electronic equipment - Google Patents
Chip packaging structure, preparation method thereof and electronic equipment Download PDFInfo
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 19
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 503
- 230000008439 repair process Effects 0.000 claims abstract description 90
- 229910052751 metal Inorganic materials 0.000 claims abstract description 82
- 239000002184 metal Substances 0.000 claims abstract description 82
- 230000008021 deposition Effects 0.000 claims abstract description 49
- 238000001312 dry etching Methods 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 33
- 239000012790 adhesive layer Substances 0.000 claims abstract description 28
- 230000004888 barrier function Effects 0.000 claims description 50
- 238000004519 manufacturing process Methods 0.000 claims description 24
- 239000003292 glue Substances 0.000 claims description 23
- 230000008569 process Effects 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 239000004642 Polyimide Substances 0.000 claims description 7
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 7
- 238000005538 encapsulation Methods 0.000 claims description 7
- 229920002577 polybenzoxazole Polymers 0.000 claims description 7
- 229920001721 polyimide Polymers 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 2
- 238000000576 coating method Methods 0.000 claims 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- 229910052719 titanium Inorganic materials 0.000 description 7
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 230000008054 signal transmission Effects 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 230000002950 deficient Effects 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000007847 structural defect Effects 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
The disclosure relates to a chip packaging structure, a preparation method thereof and electronic equipment. The method comprises the following steps: preparing an initial chip packaging structure, wherein the structure comprises a chip, a rewiring layer and a carrier plate correspondingly bonded with the rewiring layer through a release adhesive layer, and the rewiring layer in contact bonding with the release adhesive layer comprises: the first metal layer, the first deposition layer covering the surface of the first metal layer close to the release adhesive layer along with the shape and the first dielectric layer positioned between the adjacent first deposition layers; stripping the release adhesive layer and the carrier plate; removing the residual release adhesive layer and part of the first dielectric layer by dry etching and exposing the top surface of the first dielectric layer, so that the top surface of the first dielectric layer after dry etching is lower than the top surface of the first metal layer; forming an initial repair layer covering the top surface of the first dielectric layer after dry etching and the exposed surface of the first deposition layer; forming a first external conductive element on the surface of the initial repair layer, which is away from each first metal layer; and removing the initial repair layer between the adjacent first external connection conductive pieces to form a repair layer.
Description
Technical Field
The disclosure relates to the technical field of semiconductor packaging, in particular to a chip packaging structure, a preparation method thereof and electronic equipment.
Background
Chips are often used in electronic devices such as personal computers, cell phones, or digital cameras. Currently, with the increasing demands of electronic devices for miniaturization and thinning, and the continuous progress of chip design and manufacturing technology, the manufacturing process of chips also faces many challenges. For example, the circuitry in the latter generation of chips may be smaller and more complex than the circuitry in the former generation of chips, requiring wafer level processing and packaging, increasing the complexity of the chip fabrication process and also easily affecting the reliability of the chip.
Disclosure of Invention
The embodiment of the disclosure provides a chip packaging structure, a preparation method thereof and electronic equipment, which can provide a good electric signal transmission path for a chip, thereby effectively improving the reliability of the chip and the electronic equipment.
In one aspect, some embodiments of the present disclosure provide a method for manufacturing a chip package structure. The preparation method comprises the following steps.
And preparing a chip packaging initial structure. The chip package initial structure comprises: the chip comprises a chip, one or more rewiring layers arranged on one side of the chip, a chip encapsulation body which encapsulates the chip and is correspondingly connected with the rewiring layers, and a carrier plate which is correspondingly bonded with the rewiring layers through a release adhesive layer; wherein, the rewiring layer that contacts bonding with release glue film includes: the first metal layers are formed in a conformal manner, cover the first deposition layer of each first metal layer close to the surface of the release adhesive layer, and the first dielectric layer is located between the adjacent first deposition layers.
And stripping the release adhesive layer and the carrier plate.
And removing the residual release glue layer and part of the first dielectric layer by dry etching and exposing the top surface of the first dielectric layer, so that the top surface of the first dielectric layer after dry etching is lower than the top surface of the first metal layer.
And forming an initial repair layer covering the top surface of the first dielectric layer after dry etching and the exposed surface of the first deposition layer.
And forming a first external conductive piece on the surface of the initial repair layer, which is away from each first metal layer.
And removing the initial repair layer between the adjacent first external connection conductive pieces to form a repair layer.
In some embodiments, the step of dry etching removes the remaining release liner and a portion of the first dielectric layer and exposes a top surface of the first dielectric layer, comprising: the etching is performed using a plasma etching process that includes oxygen atoms.
In some embodiments, the step of removing the remaining release liner and a portion of the first dielectric layer by dry etching to expose a top surface of the first dielectric layer further comprises: and controlling the removal thickness of the first dielectric layer by controlling the oxygen flow, the etching time and the etching power.
In some embodiments, the material of the first dielectric layer comprises: polyimide photoresists, polybenzoxazole photoresists or benzocyclobutene photoresists.
In some embodiments, the first deposited layer comprises: the first barrier layer and the first seed layer are stacked in this order in a direction away from the first metal layer. The step of forming an initial repair layer covering the top surface of the first dielectric layer after dry etching and the exposed surface of the first deposition layer comprises the following steps: forming an initial second barrier layer covering the top surface of the first dielectric layer after dry etching and the exposed surface of the first deposition layer; an initial second seed layer is formed overlying the initial second barrier layer.
In some embodiments, the method further comprises the step of forming a first externally connected conductive element on a surface of the initial repair layer facing away from each of the first metal layers.
A sacrificial layer is formed overlying the initial repair layer.
Patterning the sacrificial layer to form a plurality of openings in the sacrificial layer; the opening exposes the initial repair layer on the corresponding first metal layer.
Correspondingly, the step of forming the first externally connected conductive element on the surface of the initial repair layer, which faces away from each first metal layer, comprises the following steps: and filling conductive materials into each opening to form a first external conductive member.
After the step of forming the first externally connected conductive member on the surface of the initial repair layer facing away from each first metal layer, the preparation method further includes: and removing the sacrificial layer to expose the initial repair layer between the adjacent first external connection conductive members.
In some embodiments, the method for manufacturing the chip package structure further includes: and forming a second external conductive piece on one side of the first external conductive piece, which is away from the repair layer.
On the other hand, some embodiments of the present disclosure provide a chip packaging structure, which may be formed by using the method for manufacturing the chip packaging structure in some embodiments.
Illustratively, the chip package structure includes: the chip comprises a chip, one or more rewiring layers, a chip encapsulation body, a repairing layer and a first external connection conducting piece. Wherein, the rewiring layer is arranged on the top surface of the chip. The topmost rewiring layer includes: the first metal layers are covered with the first deposition layers which are away from the surface of the chip along with the shape, and the first dielectric layers are positioned between the adjacent first deposition layers; the top surface of the first dielectric layer is lower than the top surface of the first metal layer. The chip encapsulation body encapsulates the chip and is correspondingly connected with the rewiring layer. The repair layer covers the surface of the first deposition layer exposed above the top surface of the first dielectric layer. The first external connection conductive member covers the surface of the repair layer exposed above the top surface of the first dielectric layer.
In some embodiments, the chip package structure further comprises: and a second externally connected conductive member. The second external connection conducting piece is positioned on one side of the first external connection conducting piece, which faces away from the repair layer, and is connected with the first external connection conducting piece.
In yet another aspect, some embodiments of the present disclosure provide an electronic device including the chip package structure described in some embodiments above.
In the chip packaging structure and the preparation method thereof provided by the embodiment of the disclosure, after the release adhesive layer and the carrier plate are stripped, the residual release adhesive layer and part of the first dielectric layer are removed by dry etching and the top surface of the first dielectric layer is exposed, so that the top surface of the first dielectric layer after dry etching is lower than the top surface of the first metal layer, and the height difference between the top surface of the first dielectric layer after dry etching and the top surface of the first metal layer can be utilized to provide a larger deposition area for the formation of a subsequent initial repair layer, in particular in the direction perpendicular to the top surface of the first dielectric layer. Thereby ensuring that the initial repair layer can effectively cover the first deposition layer so as to obtain the initial repair layer with continuous and complete physical structure.
Based on the method, after the first external conductive member is formed on the surface of the initial repair layer, which is away from the first metal layer, and the initial repair layer between the adjacent first external conductive members is removed to form the repair layer, not only can production failure caused by process defects and/or structural defects of the first deposition layer be avoided, but also a barrier interface can be provided for the corrosive solution of the first external conductive member by using the repair layer when the defective first external conductive member is corroded and removed, so that corrosion damage to the first metal layer is avoided. And further, the electrical performance of the rewiring layer can be effectively ensured, and a good electric signal transmission path is provided for the chip, so that the reliability of the chip and the electronic equipment is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a chip package structure provided in some embodiments of the present disclosure;
FIG. 1a is an enlarged schematic view of an M1 region of the structure shown in FIG. 1;
FIG. 2 is a schematic illustration of the resulting structure after complete removal of the release liner, as provided in some embodiments of the present disclosure;
FIG. 2a is an enlarged schematic view of an M2 region of the structure shown in FIG. 2;
FIG. 2b is an enlarged schematic view of an M3 region of the structure shown in FIG. 2;
fig. 3 is a flowchart of a method for manufacturing a chip package structure according to some embodiments of the present disclosure;
FIG. 4 is a flow chart of a method of fabricating another chip package structure provided in some embodiments of the present disclosure;
FIG. 5 is a schematic illustration of a resulting structure after forming an initial repair layer, as provided in some embodiments of the present disclosure;
FIG. 5a is an enlarged schematic view of an M4 region of the structure shown in FIG. 5;
FIG. 5b is an enlarged schematic view of an M5 region of the structure of FIG. 5;
FIG. 6 is a schematic illustration of a resulting structure after forming a sacrificial layer provided in some embodiments of the present disclosure;
FIG. 7 is a schematic illustration of a resulting structure after forming a first externally connected conductive element, as provided in some embodiments of the present disclosure;
FIG. 8 is a schematic illustration of a resulting structure after removal of a sacrificial layer provided in some embodiments of the present disclosure;
FIG. 9 is a schematic illustration of a resulting structure after formation of a repair layer, as provided in some embodiments of the present disclosure;
fig. 10 is a schematic diagram of another chip package structure provided in some embodiments of the present disclosure.
Reference numerals illustrate:
100-chip; 10-chip encapsulation body, 20-rewiring layer, 30-release adhesive layer and 40-carrier plate; 20 a-metal layer, 20 b-dielectric layer; 21-a first metal layer, 22-a first deposited layer, 23-a first dielectric layer; 221-a first barrier layer, 222-a first seed layer; 50-a repair layer, 501-a second barrier layer, 502-a second seed layer; 50A-initial repair layer, 501A-initial second barrier layer, 502A-initial second seed layer; k-opening, 60-sacrificial layer, 70-first external connection conductive member, 80-second external connection conductive member.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Embodiments of the present disclosure are illustrated in the accompanying drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present.
It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
Spatially relative terms, such as "top," "bottom," "under," "below," "beneath," "above," "over," "above," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
Currently, with the increasing demands of electronic devices for miniaturization and thinning, and the continuous progress of chip design and manufacturing technology, the manufacturing process of chips also faces many challenges.
Fig. 1 shows a wafer level fan-out package structure. Referring to fig. 1, in some embodiments, the packaging of the chip 100 may be generally implemented by a chip package 10 and a redistribution layer 20 disposed on a surface to be connected to the chip 100. As shown in fig. 1, the surface to be connected of the chip 100 may be provided with a plurality of redistribution layers 20, so as to electrically connect the internal circuit of the chip 100 with the external circuit (such as a package substrate) through the interconnection of each redistribution layer 20. Any of the redistribution layers 20 may be formed of a metal layer 20a and a dielectric layer 20b for electrically insulating adjacent metal layers 20 a. The chip package 10 contacts with the bottom edge of the redistribution layer 20, and may form an enclosed space capable of accommodating one or more chips 100, so as to perform package protection on the chips 100.
It will be appreciated that the rewiring layer 20 of the surface to which the chip 100 is to be attached is typically adhesively attached to the carrier 40 by a release liner 30, matching the implementation of the chip 100 packaging process. In addition, as shown in fig. 1a, in the topmost re-wiring layer 20 directly connected to the release adhesive layer 30, the metal layer in the re-wiring layer 20 is used as a first metal layer 21, the dielectric layer in the re-wiring layer 20 is used as a first dielectric layer 23, the re-wiring layer 20 further includes a first deposition layer 22 disposed on the surface of the first metal layer 21, and the first deposition layer 22 includes a first barrier layer 221 and a first seed layer 222 stacked in a direction away from the first metal layer 21. In this manner, after the chip 100 is covered with the chip package 10, the carrier 40 and the release adhesive layer 30 may be peeled off from the surface of the redistribution layer 20 by means of debonding.
However, in the process of peeling the carrier 40 and the release adhesive layer 30 from the surface of the redistribution layer 20, the release adhesive layer 30 that needs to be peeled still has a strong adhesion due to insufficient laser bonding or thermal bonding. Therefore, for the release glue layer 30 remaining on the surface of the first deposition layer 22, a further removal treatment is required to achieve complete removal of the release glue layer 30.
Referring to fig. 2, after the release liner 30 is completely removed, the structural integrity of the surface of the first deposited layer 22 is easily damaged. For example, due to the randomness of the adhesion strength of the release glue layer 30 around the surface of the redistribution layer 20, as shown in fig. 2a, the first seed layer 222 and the first barrier layer 221 located on the top surface of the first metal layer 21 in the M2 region may be removed by random portions; alternatively, as shown in fig. 2b, the first seed layer 222 and the first barrier layer 221 located on the top surface of the first metal layer 21 in the M3 region may be entirely removed, etc. In addition, even a portion of the first metal layer 21 may be randomly removed.
Thus, after the release liner 30 is completely removed, the surface of the first deposited layer 22 is easily damaged. If the subsequent process is directly performed on the damaged surface of the first deposition layer 22, for example, the external conductive component such as the conductive post interconnected with the external circuit (such as the package substrate) is directly prepared, the production defect is easily caused by the process defect and/or the structural defect, or the exposed first metal layer 21 is easily corroded and damaged when the external conductive component such as the defective conductive post is corroded and removed, so that the electrical performance of the redistribution layer 20 is affected, and the electric signal transmission of the chip is adversely affected.
Based on this, some embodiments of the present disclosure provide a chip packaging structure, a manufacturing method thereof, and an electronic device, which can provide a good electrical signal transmission path for a chip, thereby effectively improving the reliability of the chip and the electronic device. The chip package structure is, for example, a wafer level fan-out package structure.
Referring to fig. 3, a method for manufacturing a chip package structure according to some embodiments of the present disclosure includes S100 to S600.
S100, preparing a chip packaging initial structure. The chip package initial structure comprises: the chip comprises a chip, one or more rewiring layers arranged on one side of the chip, a chip encapsulation body which encapsulates the chip and is correspondingly connected with the rewiring layers, and a carrier plate which is correspondingly bonded with the rewiring layers through a release adhesive layer; wherein, the rewiring layer that contacts bonding with release glue film includes: the first metal layers are formed in a conformal manner, cover the first deposition layer of each first metal layer close to the surface of the release adhesive layer, and the first dielectric layer is located between the adjacent first deposition layers.
The initial structure of the chip package may be understood herein in connection with the description of some of the embodiments described above. The preparation method provided by the embodiment of the disclosure is performed on the basis.
S200, stripping the release adhesive layer and the carrier plate.
Illustratively, the release liner may be peeled by laser or thermal bonding. As such, it can be understood from the foregoing description of some embodiments that the release adhesive layer and the carrier plate are easily limited to insufficient laser bonding or thermal bonding during the process of peeling, so that the release adhesive layer that needs to be peeled still has a strong adhesion and remains.
And S300, removing the residual release glue layer and part of the first dielectric layer by dry etching and exposing the top surface of the first dielectric layer, so that the top surface of the first dielectric layer after dry etching is lower than the top surface of the first metal layer.
Here, the release glue layer can be completely removed by dry etching the remaining release glue layer. But inevitably, as shown in fig. 2 and fig. 2a and fig. 2b, after the release glue layer 30 is completely removed, the top surface of the first dielectric layer 23 and the top surface of the first deposition layer 22 may be exposed. Also, the top surface of the first deposition layer 22 is easily damaged by the complete removal of the release liner 30, for example, a portion of the first seed layer 222 and the first barrier layer 221 in the first deposition layer 22 may be randomly removed, for example, the first seed layer 222 and the first barrier layer 221 in the first deposition layer 22 may be completely removed, etc.
Based on this, in step S300, part of the first dielectric layer is removed while the residual release glue layer is removed by dry etching, and it is ensured that the top surface of the first dielectric layer after dry etching is significantly lower than the top surface of the first metal layer, so as to form a target height difference between the top surface of the first dielectric layer after dry etching and the top surface of the first metal layer.
S400, forming an initial repair layer covering the top surface of the first dielectric layer after dry etching and the exposed surface of the first deposition layer.
S500, forming a first external conductive element on the surface of the initial repair layer, which is away from each first metal layer.
And S600, removing the initial repair layer between the adjacent first external connection conductive members to form a repair layer.
In the embodiment of the disclosure, after the release adhesive layer and the carrier are peeled off, the residual release adhesive layer and part of the first dielectric layer are removed by dry etching and the top surface of the first dielectric layer is exposed, so that the top surface of the first dielectric layer after dry etching is lower than the top surface of the first metal layer, and a larger deposition area can be provided for the formation of the subsequent initial repair layer by utilizing the height difference between the top surface of the first dielectric layer after dry etching and the top surface of the first metal layer, especially in the direction perpendicular to the top surface of the first dielectric layer. Thereby ensuring that the initial repair layer can effectively cover the first deposition layer so as to obtain the initial repair layer with continuous and complete physical structure.
Based on the method, after the first external conductive member is formed on the surface of the initial repair layer, which is away from the first metal layer, and the initial repair layer between the adjacent first external conductive members is removed to form the repair layer, not only can production failure caused by process defects and/or structural defects of the first deposition layer be avoided, but also a barrier interface can be provided for the corrosive solution of the first external conductive member by using the repair layer when the defective first external conductive member is corroded and removed, so that corrosion damage to the first metal layer is avoided. And further, the electrical performance of the rewiring layer can be effectively ensured, and a good electric signal transmission path is provided for the chip, so that the reliability of the chip and the electronic equipment is effectively improved.
In some embodiments, referring to fig. 4, step S500 further includes the following steps before the step of forming the first external conductive member on the surface of the initial repair layer facing away from each of the first metal layers.
S410, forming a sacrificial layer covering the initial repair layer.
S420, patterning the sacrificial layer to form a plurality of openings in the sacrificial layer; the opening exposes the initial repair layer on the corresponding first metal layer.
Accordingly, step S500 includes the step of forming a first external conductive member on a surface of the initial repair layer facing away from each of the first metal layers, including: and filling conductive materials into each opening to form a first external conductive member.
Step S500 further includes S510 after the step of forming the first external conductive member on the surface of the initial repair layer facing away from each of the first metal layers.
S510, removing the sacrificial layer to expose the initial repair layer between the adjacent first external connection conductive members.
In some embodiments, referring to fig. 4, the method for manufacturing the chip package structure further includes S700.
S700, forming a second external conductive piece on one side of the first external conductive piece, which faces away from the repair layer.
In order to more clearly illustrate the preparation methods described in the above embodiments, the following embodiments describe some specific implementations of steps S300 to S700 in conjunction with fig. 5 to 10.
In step S300, referring to fig. 5 and fig. 5a and 5b, the dry etching removes the residual release glue layer 30 and part of the first dielectric layer 23 and exposes the top surface of the first dielectric layer 23, such that the top surface of the first dielectric layer 23 after dry etching is lower than the top surface of the first metal layer 21.
In some embodiments, please understand with reference to fig. 1 and 1a, the first deposited layer 22 includes: the first barrier layer 221 and the first seed layer 222 are stacked in this order in a direction away from the first metal layer 21. Wherein the first barrier layer 221 includes, but is not limited to, a titanium barrier layer and the first seed layer 222 includes, but is not limited to, a copper seed layer.
It can be appreciated that, when the step S200 is performed to debond the release adhesive layer 30 and the carrier 40, the materials of the first barrier layer 221 and the first seed layer 222 are different, such that there is an interface with an incomplete lattice matching between the first barrier layer 221 and the first seed layer 222; similarly, there is an interface between the first barrier layer 221 and the first metal layer 21 where the lattice is not perfectly matched. Also, the deposition thickness of the first barrier layer 221 and the first seed layer 222 is typically in the nanometer range, such as a typical deposition thickness of 100nm for the first barrier layer 221 and 500nm for the first seed layer 222. Therefore, after step S200 is performed, removing the residual release glue layer 30 may cause a portion of the first seed layer 222 in the first deposited layer 22, or a portion of the first seed layer 222 and a portion of the first barrier layer 221 in the first deposited layer 22, and even a portion of the first metal layer 21 may be peeled off along with the residual adhesion of the release glue layer 30, so as to form the first seed layer 222 and the first barrier layer 221 with discontinuous physical structures.
In some embodiments, the material of the first dielectric layer 23 includes: polyimide photoresists, polybenzoxazole (PBO) photoresists or Benzocyclobutene (BCB) photoresists. However, the present invention is not limited thereto, and other similar photopolymer materials may be used for the first dielectric layer 23.
In some embodiments, the material of the first dielectric layer 23 is a polyimide photoresist, such as a polyimide photoresist cured at a high temperature. Based on this, although the structural stability of the first dielectric layer 23 can be enhanced by curing at high temperature, the elastic modulus of the first dielectric layer 23 is still much smaller than that of the first metal layer 21. Therefore, after step S200 is performed, removing the residual release glue layer 30 also causes the portion of the first dielectric layer 23 contacting with the release glue layer 30 to be partially peeled off due to the adhesive force, so that the portion of the top surface of the first dielectric layer 23 exposed after releasing the glue layer 30 is lower than the initial top surface contacting with the release glue layer 30, thereby forming a top angle similar to a positive trapezoid shape around the first metal layer 21 by the first dielectric layer 23, and making the surface of the first deposited layer 22 present a state with discontinuous physical structure. Based on this, if the subsequent process is directly performed on the top surface of the first deposition layer 22, for example, directly preparing the externally connected conductive component such as the conductive post, and corroding to remove the externally connected conductive component such as the defective conductive post, the chemical liquid is easily caused to permeate into the first metal layer 21 along the first deposition layer 22 with discontinuous physical structure, and react with the first metal layer 21, so that the physical structure and the conductive structure of the first metal layer 21 are incomplete, thereby affecting the electrical performance of the redistribution layer 20.
However, in the embodiment of the disclosure, the residual release glue layer 30 and a portion of the first dielectric layer 23 are removed by dry etching in step S300 and the top surface of the first dielectric layer 23 is exposed, so that the etched top surface of the first dielectric layer 23 is significantly lower than the top surface of the first metal layer 21, so as to provide a larger deposition area for the formation of the subsequent initial repair layer 50A, especially in a direction perpendicular to the top surface of the first dielectric layer 23 by using the height difference between the etched top surface of the first dielectric layer 23 and the top surface of the first metal layer 21. Thereby ensuring that the initial repair layer 50A effectively encapsulates the first deposited layer 22 to obtain a continuous and complete initial repair layer 50A of physical structure.
Optionally, the step of dry etching in step S300 removes the remaining release liner 30 and a portion of the first dielectric layer 23 and exposes the top surface of the first dielectric layer 23, including: the etching is performed using a plasma etching process that includes oxygen atoms.
Optionally, the step of dry etching in step S300 removes the remaining release glue layer 30 and a portion of the first dielectric layer 23 and exposes the top surface of the first dielectric layer 23, and further includes: the removal thickness of the first dielectric layer 23 is controlled by controlling the oxygen flow, etching time and etching power.
In the embodiment of the disclosure, the removal thickness of the first dielectric layer 23 is controlled by controlling the oxygen flow, the etching time and the etching power, so that the height difference between the etched top surface of the first dielectric layer 23 and the top surface of the first metal layer 21 can be reasonably controlled to provide a larger deposition area for the formation of the subsequent initial repair layer 50A, and ensure that the subsequent initial repair layer 50A can relatively uniformly cover the exposed surface of the first deposition layer 22 and even the first metal layer 21 (depending on whether a part of the first metal layer 21 is exposed after the release glue layer 30 is removed), thereby obtaining the initial repair layer 50A with a surface physical structure connection.
In step S400, referring to fig. 5 and fig. 5a and 5b, the top surface S1 of the first dielectric layer 23 after dry etching is lower than the top surface S2 of the first metal layer 21, and an initial repair layer 50A is formed to cover the top surface of the first dielectric layer 23 after dry etching and the exposed surface of the first deposition layer 22.
In step S400, the step of forming the initial repair layer 50A covering the top surface of the first dielectric layer 23 after dry etching and the exposed surface of the first deposition layer 22 includes S401 and S402.
S401, forming an initial second barrier layer 501A covering the top surface of the first dielectric layer 23 after dry etching and the exposed surface of the first deposition layer 22.
Illustratively, the initial second barrier 501A includes, but is not limited to, a titanium barrier.
S402, an initial second seed layer 502A is formed overlying the initial second barrier layer 501A.
Illustratively, the initial second seed layer 502A includes, but is not limited to, a copper seed layer.
In steps S410 and S420, referring to fig. 6, a sacrificial layer 60 is formed to cover the initial repair layer 50A. Patterning the sacrificial layer 60 to form a plurality of openings K in the sacrificial layer 60; the opening K exposes the initial repair layer 50A on the corresponding first metal layer 21.
Illustratively, the material of the sacrificial layer 60 includes, but is not limited to, photoresist.
Optionally, the material of the sacrificial layer 60 includes: polyimide-based resin, polyamide-based resin, acrylic resin, epoxy-based resin, polybenzoxazole-based resin, silicone-based resin, benzocyclobutene-based resin, or any combination thereof.
In step S500, referring to fig. 7, a first external conductive member 70 is formed on a surface of the initial repair layer 50A facing away from each of the first metal layers 21.
Illustratively, as shown in fig. 7, the first outer conductive member 70 may be formed by filling a conductive material in each opening K.
Illustratively, the first externally connected conductive element 70 includes, but is not limited to, a conductive post. And, optionally, a plurality of first externally connected conductive elements 70 are distributed in an array.
Optionally, the first external connection conductive member 70 is a copper pillar.
In step S510, referring to fig. 8, the sacrificial layer 60 is removed, exposing the initial repair layer 50A between adjacent first external connection conductive members 70.
Illustratively, the sacrificial layer 60 may be removed using a cleaning process (i.e., a wet etching process).
In step S600, referring to fig. 9, the initial repair layer 50A between the adjacent first external connection conductive members 70 is removed to form the repair layer 50.
For example, the initial repair layer 50A between adjacent first outer link conductors 70 may be removed using a cleaning process (i.e., a wet etching process).
In the embodiment of the disclosure, after the first external conductive member 70 is formed on the surface of the initial repair layer 50A facing away from the first metal layer 21 and the repair layer 50 is removed from the initial repair layer 50A between adjacent first external conductive members 70, not only can poor production caused by the process defect and/or the structural defect of the first deposition layer 22 be avoided, but also a barrier interface can be provided for the corrosive solution of the first external conductive member 70 by using the repair layer 50 when the defective first external conductive member 70 is corroded and removed, so that corrosion damage to the first metal layer 21 is avoided, further electrical performance of the rewiring layer 20 can be effectively ensured, and a good electrical signal transmission path can be provided for the chip 100, so that reliability of the chip 100 and electronic equipment thereof can be effectively improved.
In step S700, referring to fig. 10, a second external conductive member 80 is formed on a side of the first external conductive member 70 facing away from the repair layer 50.
Illustratively, the second externally connected conductive element 80 includes, but is not limited to, solder balls.
Optionally, the second externally connected conductive element 80 is a tin-based alloy solder ball.
For example, before forming the second external conductive member 80 on the side of the first external conductive member 70 facing away from the repair layer 50, a third barrier layer may be formed prior to forming the surface of the first external conductive member 70 facing away from the repair layer 50, and then forming the second external conductive member 80 on the surface of the third barrier layer facing away from the first external conductive member 70. In this way, the third barrier layer can effectively block the atomic diffusion between the first external conductive member 70 and the second external conductive member 80, so as to effectively ensure the electrical connection performance of the first external conductive member 70 and the second external conductive member 80.
Optionally, the third barrier layer includes, but is not limited to, a nickel barrier layer, a nickel-based alloy barrier layer, a titanium barrier layer, or a titanium-based alloy barrier layer.
The chip packaging structure provided by some embodiments of the present disclosure may be formed by using the method for manufacturing the chip packaging structure in some embodiments. The above preparation method has technical advantages, and the chip package structure is also provided, which will not be described in detail herein.
For example, referring to fig. 10, the chip package structure includes: chip 100, one or more redistribution layers 20, chip package 10, repair layer 50, and first external connection conductive member 70.
The redistribution layer 20 is disposed on the top surface of the chip 10. Any of the redistribution layers 20 may be formed by a metal layer 20a and a dielectric layer 20b for isolating adjacent metal layers 20 a. And, the topmost rewiring layer 20 includes: a plurality of first metal layers 21, a first deposition layer 22 conformally covering a surface of each first metal layer 21 facing away from the chip 100, and a first dielectric layer 23 between adjacent first deposition layers 22; the top surface of the first dielectric layer 23 is lower than the top surface of the first metal layer 21.
The chip package 10 encapsulates the chip 100 and is correspondingly connected to the redistribution layer 20. The chip package 10, for example, in contact with the bottom edge of the redistribution layer 20, may form an enclosed space capable of accommodating one or more chips 100 to encapsulate the chips 100.
The repair layer 50 covers the surface of the first deposited layer 22 exposed above the top surface of the first dielectric layer 23.
The first outer conductive member 70 covers the surface of the repair layer 50 exposed above the top surface of the first dielectric layer 23.
Illustratively, the materials of the first dielectric layer 23 include: polyimide photoresists, polybenzoxazole (PBO) photoresists or Benzocyclobutene (BCB) photoresists. However, the present invention is not limited thereto, and other similar photopolymer materials may be used for the first dielectric layer 23.
Illustratively, the first deposited layer 22 includes: the first barrier layer 221 and the first seed layer 222 are stacked in this order in a direction away from the first metal layer 21. The repair layer 50 includes: a second barrier layer 501 and a second seed layer 502 are stacked in this order in a direction away from the first metal layer 21.
Optionally, the first barrier layer 221 and the second barrier layer 501 are the same material, including but not limited to a titanium barrier layer.
Optionally, the first seed layer 222 and the second seed layer 502 are the same material, including but not limited to a copper seed layer.
Illustratively, the first externally connected conductive element 70 includes, but is not limited to, a conductive post. And, optionally, a plurality of first externally connected conductive elements 70 are distributed in an array.
Optionally, the first external connection conductive member 70 is a copper pillar.
In some embodiments, referring to fig. 9, the chip package structure further includes: and a second externally connected conductive element 80. The second outer conductive member 80 is located on a side of the first outer conductive member 70 facing away from the repair layer 50 and is connected to the first outer conductive member 70.
Illustratively, the second externally connected conductive element 80 includes, but is not limited to, solder balls.
Optionally, the second externally connected conductive element 80 is a tin-based alloy solder ball.
Illustratively, the chip package structure further comprises: a third barrier layer (not shown in fig. 9) is disposed between the first and second outer conductive members 70 and 80.
Optionally, the third barrier layer includes, but is not limited to, a nickel barrier layer, a nickel-based alloy barrier layer, a titanium barrier layer, or a titanium-based alloy barrier layer.
Some embodiments of the present disclosure provide an electronic device including the chip package structure in any one of the above embodiments.
In some embodiments, the electronic device further includes a printed circuit board electrically connected to the chip package structure.
Optionally, the electronic device includes, but is not limited to, a smart phone, a smart television set-top box, a personal computer (personal computer, PC), a wearable device, a smart broadband, and other terminal devices; or telecommunication devices such as wireless networks, fixed networks, servers, and electronic devices such as chip modules and memories, to mention a few.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. The preparation method of the chip packaging structure is characterized by comprising the following steps:
preparing a chip packaging initial structure; the chip package initial structure comprises: the chip comprises a chip, one or more rewiring layers arranged on one side of the chip, a chip encapsulation body which is used for coating the chip and is correspondingly connected with the rewiring layers, and a carrier plate which is correspondingly bonded with the rewiring layers through a release adhesive layer; wherein the rewiring layer in contact bonding with the release adhesive layer comprises: the first metal layers are covered on the first deposition layer, which is close to the surface of the release adhesive layer, of each first metal layer in a conformal manner, and a first dielectric layer is positioned between the adjacent first deposition layers;
stripping the release adhesive layer and the carrier plate;
removing the residual release adhesive layer and part of the first dielectric layer by dry etching and exposing the top surface of the first dielectric layer, so that the top surface of the first dielectric layer after dry etching is lower than the top surface of the first metal layer;
forming an initial repair layer covering the top surface of the first dielectric layer after dry etching and the exposed surface of the first deposition layer;
forming a first externally connected conductive element on the surface of the initial repair layer, which is away from each first metal layer;
and removing the initial repair layer between the adjacent first external connection conducting pieces to form a repair layer.
2. The method of claim 1, wherein the step of dry etching to remove the remaining release glue layer and a portion of the first dielectric layer and expose a top surface of the first dielectric layer comprises: the etching is performed using a plasma etching process that includes oxygen atoms.
3. The method of manufacturing a chip package structure according to claim 2, wherein the dry etching removes the remaining release glue layer and part of the first dielectric layer and exposes the top surface of the first dielectric layer, further comprising:
and controlling the removal thickness of the first dielectric layer by controlling the oxygen flow, the etching time and the etching power.
4. The method of manufacturing a chip package according to claim 2, wherein the material of the first dielectric layer comprises: polyimide photoresists, polybenzoxazole photoresists or benzocyclobutene photoresists.
5. The method of manufacturing a chip package structure according to claim 1, wherein the first deposition layer comprises: a first barrier layer and a first seed layer sequentially stacked in a direction away from the first metal layer; the step of forming an initial repair layer covering the top surface of the first dielectric layer after dry etching and the exposed surface of the first deposition layer comprises the following steps:
forming an initial second barrier layer covering the top surface of the first dielectric layer after dry etching and the exposed surface of the first deposition layer;
an initial second seed layer is formed overlying the initial second barrier layer.
6. The method of claim 1, wherein before the step of forming the first external conductive member on the surface of the initial repair layer facing away from each of the first metal layers, the method further comprises:
forming a sacrificial layer covering the initial repair layer;
patterning the sacrificial layer to form a plurality of openings in the sacrificial layer; the opening exposes the initial repair layer corresponding to the first metal layer;
wherein the step of forming a first external conductive member on the surface of the initial repair layer facing away from each first metal layer includes: filling conductive materials into each opening to form the first externally connected conductive piece;
after the step of forming the first external conductive member on the surface of the initial repair layer facing away from each first metal layer, the preparation method further includes: and removing the sacrificial layer to expose the initial repair layer between the adjacent first external connection conductive members.
7. The method for manufacturing a chip package structure according to any one of claims 1 to 6, further comprising:
and forming a second external conductive piece on one side of the first external conductive piece, which is away from the repair layer.
8. A chip package structure, comprising:
a chip;
one or more rewiring layers arranged on the top surface of the chip; wherein the topmost layer of the rewiring layer comprises: the first metal layers are covered with the first deposition layers facing away from the surface of the chip in a conformal manner, and the first dielectric layers are positioned between the adjacent first deposition layers; the top surface of the first dielectric layer is lower than the top surface of the first metal layer;
the chip encapsulation body is used for coating the chip and is correspondingly connected with the rewiring layer;
a repair layer covering a surface of the first deposited layer exposed above a top surface of the first dielectric layer;
and the first external connection conductive piece covers the surface of the repair layer exposed above the top surface of the first dielectric layer.
9. The chip package structure of claim 8, further comprising:
the second external connection conducting piece is positioned on one side of the first external connection conducting piece, which is away from the repair layer, and is connected with the first external connection conducting piece.
10. An electronic device comprising the chip package structure according to claim 8 or 9.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040004284A1 (en) * | 2002-07-05 | 2004-01-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Microelectronic device with a redistribution layer having a step shaped portion and method of making the same |
| US20140252548A1 (en) * | 2013-03-08 | 2014-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Filter and Capacitor Using Redistribution Layer and Micro Bump Layer |
| US20150187710A1 (en) * | 2011-12-30 | 2015-07-02 | Deca Technologies Inc. | Semiconductor device and method comprising thickened redistribution layers |
| US20160276237A1 (en) * | 2014-06-16 | 2016-09-22 | STATS ChipPAC Pte. Ltd. | Semiconductor Device and Method to Minimize Stress on Stack Via |
| WO2017164447A1 (en) * | 2016-03-24 | 2017-09-28 | 주식회사 코윈디에스티 | Method for repairing metal wiring |
| TW201806049A (en) * | 2016-05-17 | 2018-02-16 | 力成科技股份有限公司 | Manufacturing method of package structure |
| CN110620053A (en) * | 2019-09-06 | 2019-12-27 | 广东佛智芯微电子技术研究有限公司 | Fan-out type packaging structure with laser opening blocking layer and preparation method thereof |
| US20210242117A1 (en) * | 2020-01-31 | 2021-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method of manufacturing the same |
| US20210375809A1 (en) * | 2020-05-28 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and manufacturing method thereof |
| US20220077078A1 (en) * | 2020-09-04 | 2022-03-10 | Samsung Electronics Co., Ltd. | Semiconductor package |
| CN114724965A (en) * | 2020-12-22 | 2022-07-08 | 华泰电子股份有限公司 | Method for manufacturing semiconductor package |
| CN115148615A (en) * | 2022-09-05 | 2022-10-04 | 长电集成电路(绍兴)有限公司 | Method for repairing chip packaging structure |
-
2023
- 2023-04-24 CN CN202310443760.9A patent/CN116169030B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040004284A1 (en) * | 2002-07-05 | 2004-01-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Microelectronic device with a redistribution layer having a step shaped portion and method of making the same |
| US20150187710A1 (en) * | 2011-12-30 | 2015-07-02 | Deca Technologies Inc. | Semiconductor device and method comprising thickened redistribution layers |
| US20140252548A1 (en) * | 2013-03-08 | 2014-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Filter and Capacitor Using Redistribution Layer and Micro Bump Layer |
| US20160276237A1 (en) * | 2014-06-16 | 2016-09-22 | STATS ChipPAC Pte. Ltd. | Semiconductor Device and Method to Minimize Stress on Stack Via |
| WO2017164447A1 (en) * | 2016-03-24 | 2017-09-28 | 주식회사 코윈디에스티 | Method for repairing metal wiring |
| TW201806049A (en) * | 2016-05-17 | 2018-02-16 | 力成科技股份有限公司 | Manufacturing method of package structure |
| CN110620053A (en) * | 2019-09-06 | 2019-12-27 | 广东佛智芯微电子技术研究有限公司 | Fan-out type packaging structure with laser opening blocking layer and preparation method thereof |
| US20210242117A1 (en) * | 2020-01-31 | 2021-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method of manufacturing the same |
| US20210375809A1 (en) * | 2020-05-28 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and manufacturing method thereof |
| US20220077078A1 (en) * | 2020-09-04 | 2022-03-10 | Samsung Electronics Co., Ltd. | Semiconductor package |
| CN114724965A (en) * | 2020-12-22 | 2022-07-08 | 华泰电子股份有限公司 | Method for manufacturing semiconductor package |
| CN115148615A (en) * | 2022-09-05 | 2022-10-04 | 长电集成电路(绍兴)有限公司 | Method for repairing chip packaging structure |
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|---|---|
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