WO2017202037A1 - Conductor post and manufacturing method thereof, chip packaging method, and flip chip product - Google Patents

Abstract

Provided are a conductor post (20) and a manufacturing method thereof, a chip packaging method, and a flip chip product. The method for manufacturing the conductor post (20) comprises the following steps of: a surface of a chip electrode (12), or a hole wall in a hole (28) formed in a chip (10), or the line surface of a package substrate (40) are subjected to an ion implantation and/or a plasma deposition process by using a target material, so as to form a conductive seed layer (16) (S1); and a columnar conductor thickened layer (18) is formed over the conductive seed layer (16), the conductor thickened layer (18) and the conductive seed layer (16) constituting a conductor post (20) (S2).

Description

Conductor column and manufacturing method thereof, method for packaging chip and chip flip product Technical field

The present invention relates to the field of chip packaging for electronic products, and more particularly to a conductor post and a method of manufacturing the same, a method of packaging a chip using the conductor post, and a flip chip product manufactured by the packaging method, the conductor post being suitable for an electrode on a chip Electrically connected to a package substrate, such as a single-layer printed wiring board, a laminated multi-layer substrate, or a buried-line coreless board.

Background technique

Along with the trend of high integration, miniaturization and thinning of electronic products, the corresponding printed circuit boards or integrated circuit package substrates are required to be light, thin and short, while satisfying good electrical and thermal performance. Small trends have led to increased integration of electronic components, high density of packages, miniaturization and multi-pinning. Based on this demand, in addition to design and manufacturing technology, IC packaging manufacturers are constantly developing more advanced packaging technologies to achieve high-density integration, making the package structure from the early QFP (square flat package technology), BGA ( Solder ball array packages have evolved to more advanced CSP (chip size packages) and even WLP CSP (silicon wafer level packages). Flip chip flip chip connection technology is a kind of packaging technology developed in recent years. It has the advantages of short connection path between chip and circuit board, low impedance, small signal loss, less parasitic signal of electric signal, etc. Long wire bonding is used in many high-end electronic products.

The traditional flip chip connection technology uses solder balls to solder chip nodes and circuit board nodes together by high temperature reflow soldering. As the line density and CSP chip density increase, the spacing between the electrodes for external connection becomes smaller and smaller. As the design density of butt joints increases, current and thermal effects also increase. Due to the influence of the electron transfer factor of the solder ball, the reliability of the product is lowered, and the problem of short circuit is caused by bridging between the electrodes at the time of high temperature reflow soldering. To this end, the copper pillar (Cu pillar) has been gradually replaced by the tin ball. The mainstream technology of flip chip connection. It is expected that the copper column technology will be developed in the direction of further reducing the pitch and increasing the density, and is suitable for processes below 28/20 nm and extended to all flip chip products. Thanks to the material properties of copper, copper pillar connections have superior electrical conductivity, thermal performance and reliability, and meet ROHS environmental requirements, which can be widely used in transceivers, embedded processors, power management, baseband chips, ASICs. And some SOCs that require fine pitch, ROHS standards, low cost, and good electrical performance. This chip interconnect technology reduces the number of substrate layers used, reduces overall package cost (approximately 20% savings compared to wire bonding), and provides high electromigration and current carrying capability.

The copper posts can be fabricated on a chip or on a package substrate or printed circuit board. When making copper pillars on a chip, since the chip is usually small in wafer area (only about 200 mm in diameter), advanced plating equipment and syrup are required, and the plating ability is strong but the manufacturing cost is high. When a copper pillar is fabricated on a package substrate or a printed wiring board, a subtractive method is usually used. However, since the etching solution is used to etch the copper foil, the etching liquid attacks the copper not only downward but also from the side, and thus side etching occurs. The resulting copper column is a cone. This is not conducive to the fabrication of smaller pitch copper pillars, and is not conducive to the integrity of signal transmission. Recently, attempts have been made to form a metal seed layer containing titanium or copper on a chip electrode or a printed wiring board by chemical copper or sputtering, followed by growing a cylindrical copper pillar on the metal seed layer, and then using the copper pillar. Come flip the chip. However, although these existing copper pillar flip-chip technologies can meet the requirements of small pitch, the metal seed layer bonding strength between the copper pillar and the package substrate line, or the junction between the copper pillar and the semiconductor chip electrode is weak and easy. Cracks are generated, and the electrodes are easily broken due to stress caused by uneven thermal expansion during the packaging process, and the copper pillars are peeled off from the package substrate or the chip electrodes, thereby causing the electronic product to fail.

Summary of the invention

The present invention has been made in view of the above problems, and an object thereof is to provide a conductor post having a high bonding force with a chip electrode or a package substrate line, a method of manufacturing the same, a method of packaging the chip using the conductor post, and A chip flip product produced by the packaging method.

A first technical solution of the present invention is a method of manufacturing a conductor post, comprising the steps of: using a target to perform ions on a surface of a chip electrode, or a hole wall formed in a hole in a chip, or a line surface of a package substrate Injecting and/or plasma deposition treatment to form a conductive seed layer (step S1); and forming a columnar conductor thickening layer over the conductive seed layer, the conductor thickening layer and the conductive seed layer forming a conductor post ( Step S2).

According to a second aspect of the present invention, in the first aspect, plasma deposition is performed after ion implantation.

According to a third aspect of the present invention, in the first aspect, during the ion implantation, the ions of the target material obtain an energy of 1-1000 keV and are injected into the surface of the chip electrode or the hole wall of the hole or the circuit of the package substrate. Below the surface, an ion implantation layer is formed as at least a portion of the conductive seed layer.

According to a fourth aspect of the present invention, in the first aspect, during the plasma deposition, the ions of the target material obtain an energy of 1-1000 eV and are deposited on the surface of the chip electrode or the hole wall of the hole or the package substrate. Above the surface of the line, a plasma deposited layer is formed as at least a portion of the conductive seed layer.

According to a fifth aspect of the present invention, in the first aspect, the conductive seed layer includes Ti, Cr, Ni, Cu, Ag, Al, Au, V, Zr, Mo, Nb, In, Sn, Tb, and One or more of the alloys between, the thickened layer of the conductor comprises one or more of Cu, Ag, Al, Au, and alloys therebetween.

According to a sixth aspect of the present invention, in the first aspect, the conductor post is in the form of a solid or hollow column, and one end thereof is buried inside the chip or the package substrate, and the other end is located above the surface of the chip or the package substrate.

According to a seventh aspect of the present invention, in any one of the first to sixth aspects, in the step S1, the insulating layer provided with the hole is first covered on the periphery of the chip electrode, and then the hole wall and the hole are exposed to the hole. Performing ion implantation and/or plasma deposition treatment on the surface of the chip electrode of the hole to form a conductive seed layer; in step S2, first covering the insulating layer with a photoresist, and forming a photoresist in the photoresist by photolithography a hole communicating with the hole, then filling the hole and the opening with a conductive material, and forming a conductor after removing the photoresist and the conductive seed layer below it column.

According to an eighth aspect of the present invention, in any one of the first to sixth aspects, in step S1, a chip or two or more chips stacked together are drilled through holes. The periphery of the hole is covered with an insulating layer, and then the hole wall of the through hole is subjected to ion implantation and/or plasma deposition treatment to form a conductive seed layer of two or more chips which are passed through one chip or stacked together; in step S2 The via hole is filled with a conductive material, and the conductor post is formed after the insulating layer is removed.

According to a ninth aspect of the present invention, in any one of the first to sixth aspects, in the step S1, the surface of the package substrate is subjected to ion implantation and/or plasma deposition treatment to form a conductive seed layer. In step S2, the photoresist is first covered on the package substrate, an opening is formed in the photoresist by photolithography to expose the wiring surface of the package substrate, and then the opening is filled with a conductive material, and the photoresist is removed and under the photoresist. A conductive pillar is formed after the conductive seed layer.

According to a tenth aspect of the present invention, in the ninth aspect, two or more chips are directly laminated together, or an insulating isolation layer is disposed between the chips.

An eleventh technical solution of the present invention is a conductor post comprising a conductive seed layer and a columnar conductor thickening layer formed over the conductive seed layer, the conductive seed layer being disposed on the surface of the chip electrode, or The pore walls of the holes formed in the chip, or on the wiring surface of the package substrate, and include an ion implantation layer and/or a plasma deposition layer.

According to a twelfth aspect of the present invention, in the eleventh aspect, the ion implantation layer is located on a surface of the chip electrode or a hole wall of the hole or a line surface of the package substrate, and is a chip electrode material or a chip substrate or A wiring material of the package substrate, and a doped structure composed of a conductive material.

According to a thirteenth aspect of the present invention, in the eleventh aspect, the plasma deposition layer is located on a surface of the chip electrode or a hole wall of the hole or a line surface of the package substrate.

According to a fourteenth aspect of the present invention, in the eleventh aspect, the conductive seed layer includes Ti, Cr, Ni, Cu, Ag, Al, Au, V, Zr, Mo, Nb, In, Sn, and Tb. And one or more of the alloys between them, the conductor thickening layer comprising one or more of Cu, Ag, Al, Au, and alloys therebetween.

According to a fifteenth aspect of the present invention, in the eleventh aspect, the conductor post is in the form of a solid or hollow column, one end of which is embedded in the inside of the chip or the package substrate, and the other end is located above the surface of the chip or the package substrate.

According to the present invention, ions during the ion implantation are forcibly injected into the substrate (herein generally referred to as the chip substrate, the chip electrode material, and the package substrate material) at a high speed, between the substrate and the substrate material. Forming a stable doped structure corresponds to the formation of a large number of sub-piles below the surface of the substrate (here generally referred to as the surface of the chip electrode, the surface of the package substrate, and the walls of the holes that are formed in the holes in the chip). Because of the existence of the pile and the subsequent thickened layer of the conductor is connected to the pile, the joint between the conductor column including the conductive seed layer and the thick layer of the conductor and the substrate is high. It is higher than the bonding force obtained by magnetron sputtering in the prior art (up to 0.5 N/mm). In addition, during plasma deposition, ions of the conductive material fly to the substrate at a higher velocity under the action of an accelerating electric field and are deposited thereon to form a plasma deposited layer. The plasma deposition layer and the base material have a large bonding force (greater than 0.5 N/mm), so that the finally produced conductor post is not easily peeled off or peeled off from the substrate. On the other hand, conductive material ions for ion implantation and plasma deposition generally have a size on the order of nanometers, are more uniformly distributed during implantation or deposition, and have little difference in incident angle to the surface of the substrate. Therefore, it is possible to ensure that the obtained conductive seed layer has good uniformity and compactness, and pinholes or cracks are less likely to occur, which is advantageous for improving the structural integrity, rigidity, and electrical conductivity of the conductor post.

A sixteenth technical solution of the present invention is a method of packaging a chip using a conductor post, comprising the steps of: forming a first conductor post on a chip, and/or forming a second conductor post on a wiring surface of the package substrate ( Step S1); electrically connecting between the first conductor post and the wiring surface of the package substrate, or between the second conductor post and the surface of the chip electrode, or between the first conductor post and the second conductor post (step S2), wherein the first conductor post and/or the second conductor post is a conductor post obtained by any one of the above first to tenth aspects, or in the eleventh to fifteenth aspects described above Any type of conductor column.

According to a seventeenth aspect of the present invention, in the sixteenth aspect, the chip includes two or more chips stacked together, and the first conductor column penetrates two or more chips.

According to an eighteenth aspect of the present invention, in the sixteenth aspect, the electrical connection is performed by reflow soldering.

According to a nineteenth aspect of the present invention, in the sixteenth aspect, the wiring surface of the package substrate includes a pad for soldering the first conductor post, or the surface of the chip electrode includes a pad for soldering the second conductor column.

A twentieth technical solution of the present invention is a chip flip-chip product comprising a package substrate, a chip, and a conductor post between the package substrate and the chip and electrically connecting the same, the conductor post comprising a conductive seed layer and the conductive seed a columnar conductor thickening layer formed above the crystal layer, the conductive seed layer being disposed on the surface of the chip electrode, or on the hole wall of the hole formed in the chip, or on the wiring surface of the package substrate, and including the ion implantation layer And/or a plasma deposited layer.

According to a twenty-first aspect of the present invention, in the twentieth aspect, the ion implantation layer is located on a surface of the chip electrode or a hole wall of the hole or a line surface of the package substrate, and is a chip electrode material or a chip substrate. Or a wiring material of the package substrate and a doped structure composed of a conductive material.

According to a twenty-second aspect of the present invention, in the twentieth aspect, the plasma deposition layer is located on a surface of the chip electrode or a hole wall of the hole or a line surface of the package substrate.

According to a twenty-third aspect of the present invention, in the twentieth aspect, the conductor post is in the form of a solid or hollow column, one end of which is buried inside the chip or the package substrate, and the other end is located above the surface of the chip or the package substrate.

According to a twenty-fourth aspect of the present invention, in the twentieth aspect, the conductive seed layer of the conductor post penetrates one chip or two or more chips stacked together.

In accordance with the present invention, in a flip chip product, a conductor post electrically connecting a chip to a package substrate has a conductive seed layer including an ion implantation layer and/or a plasma deposition layer. As described above, the conductor post has a high bonding force with the substrate, so that the chip is flipped The product will also have high stability and reliability, and it is not prone to failure or circuit failure. In addition, since the ion implantation layer and/or the plasma deposition layer have good uniformity and compactness, pinholes or cracks are less likely to occur, and the conductor column thus has good structural integrity, rigidity, and electrical conductivity, and thus Chip flip-chip products will also have excellent robustness, electrical conductivity and thermal properties, and can be widely used in various electronic products.

DRAWINGS

These and other features, aspects and advantages of the present invention will become more readily apparent to those skilled in the <RTI For the sake of clarity, the figures are not necessarily to scale, and some parts may be exaggerated to show specific details. Throughout the drawings, the same reference numerals will be given to the

1 is a flow chart generally showing a method of manufacturing a conductor post in accordance with the present invention.

2 is a flow chart showing a method of manufacturing a conductor post according to a first embodiment of the present invention;

3(a)-(e) are schematic cross-sectional views showing the structure corresponding to the steps of the method shown in Fig. 2 when manufacturing a conductor post;

Figure 4 is a schematic cross-sectional view showing another conductor post produced by the method shown in Figure 2;

5(a)-(e) are schematic cross-sectional views showing various conductive seed layers in accordance with the present invention;

Figure 6 is a flow chart showing a method of manufacturing a conductor post according to a second embodiment of the present invention;

7(a)-(d) are schematic cross-sectional views showing the structure corresponding to the steps of the method shown in Fig. 6 when manufacturing a conductor post;

Figure 8 is a flow chart showing a method of manufacturing a conductor post according to a third embodiment of the present invention;

9(a)-(d) are schematic cross-sectional views showing the structure corresponding to the steps of the method shown in Fig. 8 when manufacturing a conductor post;

Figure 10 is a flow chart showing a method of packaging a chip using a conductor post in accordance with the present invention;

11(a)-(e) are schematic cross-sectional views showing the structure of a flip chip product after a chip is packaged using a conductor post.

Reference number:

10 chips

12 chip electrodes

14 chip electrode surface

16 conductive seed layer

161 ion implantation layer

162 plasma deposition layer

18 conductor thickening layer

20 conductor column

22 base

24 base surface

26 insulation

28 holes

30 photoresist

32 openings

34 insulation isolation layer

36 through holes

38 hole wall

40 package substrate

42 surface of the package substrate

44 The wiring surface of the package substrate.

detailed description

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Those skilled in the art should understand that the description is merely illustrative of exemplary embodiments of the invention and is not intended to limit the scope of the invention. For example, in one drawing or embodiment of the invention The elements or features described may be combined with other elements or features shown in one or more other figures or embodiments. In addition, in order to facilitate the description of the positional relationship between the layers of materials, spatially relative terms such as "above" and "below", and "inside" and "outside" are used herein, and the terms are relative to the chip or The surface of the package substrate or the hole wall of the hole. If the layer A material is in a direction toward the outside of the chip, package substrate or hole wall relative to the layer B material, then the layer A material is considered to be above or outside of the layer B material, and vice versa.

1 is a flow chart generally showing a method of manufacturing a conductor post according to the present invention, the conductor post being adapted to electrically connect electrodes on a chip to a package substrate, such as a single-layer printed wiring board, a multilayer printed substrate, or buried Line without core board, etc. Specifically, the method of manufacturing a conductor post according to the present invention includes the steps of: ion-implanting a surface of a chip electrode, or a hole wall formed in a hole in a chip, or a wiring surface of a package substrate using a target, and/or Plasma deposition treatment to form a conductive seed layer (step S1); and forming a columnar conductor thickening layer above the conductive seed layer, the conductor thickening layer and the conductive seed layer forming a conductor post (step S2) . In other words, the conductor post of the present invention may be formed on the surface of the chip electrode, on the hole wall of the hole formed in the chip (particularly the chip electrode), or on the wiring surface of the package substrate. Wherein, the line surface of the package substrate refers to the surface of the line pattern formed on the package substrate. The conductor bars of these three forms and the method of manufacturing the same will be specifically described below. It should be understood that in the following description, the serial numbers of the embodiments are merely for convenience of description, and do not represent the advantages and disadvantages of the embodiments. The description of the various embodiments has been emphasized, and portions not detailed in a certain embodiment can be referred to the related description of other embodiments.

<First Embodiment>

2 is a flow chart showing a method of manufacturing a conductor post according to a first embodiment of the present invention. The method relates to forming a conductor post on a surface of a chip electrode, and comprising the steps of: covering an insulating layer provided with a hole at a periphery of the chip electrode (step S11); performing a hole wall of the hole and a surface of the chip electrode exposed to the hole Ion implantation and/or plasma deposition treatment to form a conductive seed layer (step S12); covering the insulating layer with a photoresist, forming an opening in the photoresist in contact with the hole by photolithography (step S21); Conductive material fills holes and openings (steps S22); and removing the photoresist and the conductive seed layer underneath to form a conductor post (step S23). Among them, steps S11 and S12 correspond to step S1 shown in FIG. 1, and steps S21, S22 and S23 correspond to step S2 shown in FIG. 1. In addition, FIGS. 3(a)-(e) are schematic cross-sectional views showing the structure corresponding to the steps of the method shown in FIG. 2 when manufacturing the conductor post, which will be described in detail below.

In step S11, as shown in FIG. 3(a), first, the insulating layer 26 provided with the holes 28 is covered on the periphery of the electrode 12 of the chip 10. The insulating layer 26 may include a material such as polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), and the holes 28 formed in the insulating layer 26 may have a cylindrical shape as needed. Various cross-sectional shapes such as rectangles, squares, triangles, and inverted trapezoids. In addition, a passivation layer may be first covered on the periphery of the chip electrode, and then the insulating layer is covered on the passivation layer and a hole is formed. The passivation layer may include an oxide material such as silicon oxide or silicon nitride. It is easy to understand that although the electrodes 12 shown in FIG. 3(a) are embedded in the chip 10 such that the outer surfaces of both of them are flush, this is merely for convenience of illustration, and in fact the electrodes 12 may also be from the chip. The surface of 10 is protruded and has a protruding structure.

In step S12, the hole wall of the hole 28 and the surface of the chip electrode 12 exposed to the hole 28 may be subjected to an ion implantation process to form an ion implantation layer 161, followed by a plasma deposition process to form a plasma deposition layer 162. The plasma deposition layer 162 and the ion implantation layer 161 together constitute a conductive seed layer 16. As shown in FIG. 3(b), the ion implantation layer 161 is located below the surface 14 of the chip electrode 12, below the hole wall of the hole 28, and below the surface of the insulating layer 26, and the plasma deposition layer 162 is correspondingly located in the ion implantation layer 161. Above, the ion implantation layer 161 and the plasma deposition layer 162 together constitute a conductive seed layer. In addition to plasma deposition after ion implantation, when a conductive seed layer is formed, a conductive material may be implanted only under the surface of the chip electrode, the wall of the hole, and the surface of the insulating layer by ion implantation to form an ion implantation layer. As the conductive seed layer, a conductive material may be deposited only on the surface of the chip electrode, the walls of the holes, and the surface of the insulating layer by plasma deposition to form a plasma deposited layer as a conductive seed layer. Alternatively, it is also possible to perform plasma implantation after ion implantation to form a surface of the chip electrode and a hole. A plasma deposition layer is formed over the surface of the wall and the insulating layer, and an ion implantation layer is formed under the surface of the plasma deposition layer. Further, in various methods of forming a conductive seed layer, one or more ion implantation and/or plasma deposition processes may be performed to form one or more ion implantation layers and/or plasma deposition layers.

5(a)-(e) are schematic cross-sectional views showing various conductive seed layers according to the present invention, wherein the substrate 22 represents an object on which ion implantation and/or plasma deposition is performed, which may include the following The described chip electrode material, chip substrate, package substrate material, package substrate wiring material, insulating layer material, and the like. In this embodiment, the substrate 22 generally represents a chip electrode material and an insulating layer material, and the surface 24 of the substrate generally represents the surface of the chip electrode, the surface of the insulating layer, and the hole walls of the holes formed in the insulating layer. In FIG. 5(a), the conductive seed layer includes only the ion implantation layer 161 formed under the surface 24 of the substrate 22. In FIG. 5(b), the conductive seed layer includes only the plasma deposited layer 162 deposited over the surface 24 of the substrate 22. In FIG. 5(c), the conductive seed layer includes both an ion implantation layer 161 formed under the surface 24 of the substrate 22 and a plasma deposition layer 162 attached over the ion implantation layer 161. In FIG. 5(d), the conductive seed layer includes a plasma deposition layer 162 directly above the surface 24 of the substrate 22, and an ion implantation layer 161 implanted below the surface of the plasma deposition layer 162, at this time, ion implantation. The inner surface of layer 161 will be in plasma deposition layer 162 while the outer surface will be flush with the outer surface of plasma deposited layer 162. Fig. 5(e) shows a cross-sectional structure of a conductive seed layer obtained by ion implantation and plasma deposition twice, wherein the ion implantation layer 161 and the plasma deposition layer 162 in the conductive seed layer are divided into two layers. . The second ion implantation layer will penetrate deep into the interior of the first implantation layer, while the second plasma deposition layer is attached above the first deposition layer. It will be readily understood that the structures illustrated in Figures 5(a)-(e) are merely exemplary illustrations of conductive seed layers, and are not exhaustive. For example, the conductive seed layer in each of the figures may have an ion implantation layer and/or a plasma deposition layer divided into two or more layers, or may be stacked on each other to form a complicated multilayer structure, such as ion implantation. Layer/plasma deposition layer/ion implantation layer/plasma deposition layer configuration, and the like.

Ion implantation can be performed by using a conductive material as a target, in the true In an empty environment, the conductive material in the target is ionized by an arc to generate ions, and then the ions are accelerated under an electric field to obtain a certain energy. The energetic conductive material ions then impinge directly onto the surface of the chip electrode, the pore walls of the pores, and the surface of the insulating layer at a relatively high velocity, and are implanted to a surface or a depth below the pore walls. A relatively stable chemical bond, such as an ionic bond or a covalent bond, is formed between the implanted conductive material ions and the material molecules of the chip electrode and the insulating layer, which together constitute a doped structure. The outer surface of the doped structure (ie, the ion implantation layer) is flush with the surface of the chip electrode, the hole wall of the hole or the surface of the insulating layer, and the inner surface thereof penetrates into the inside of the chip electrode and the insulating layer, that is, Located on the surface of the chip electrode, the hole wall of the hole, and the surface of the insulating layer. In the ion implantation process, the depth of ion implantation and the substrate can be easily adjusted by controlling various parameters such as electric field voltage, current, degree of vacuum, ion implantation dose, etc. (referring herein as chip electrode material and insulating layer material) The bonding force with the conductive seed layer. For example, the implantation energy of ions can be adjusted to 1-1000 keV (for example, 5, 10, 50, 100, 200, 300, 400, 500, 600, 700, 800, 900 keV, etc.), and the implantation depth can be adjusted to 1-500 nm. (eg 5, 10, 50, 100, 200, 300, 400 nm, etc.).

Plasma deposition can be performed in a similar manner to ion implantation, except that a lower accelerating voltage is applied during operation. That is, the conductive material is also used as a target, and in a vacuum environment, the conductive material in the target is ionized by an arc to generate ions, and then the ion is accelerated under an electric field to obtain a certain energy and deposited on the surface of the chip electrode. The wall of the hole and the surface of the insulating layer constitute a plasma deposition layer. During plasma deposition, the ions of the conductive material can be obtained from 1-1000 eV (for example, 5, 10, 50, 100, 200, 300, 400, 500, 600, 700, 800, 900 eV, etc.) by adjusting the accelerating voltage of the electric field. The energy, and a plasma deposition layer having a thickness of 10 to 1000 nm (for example, 50, 100, 200, 300, 400, 500, 600, 700, 800, 900 nm, etc.) can be obtained by controlling the ion deposition time, passing current, or the like.

In ion implantation and/or plasma deposition, the target used is a conductive material, which may be a metal target, an oxide target, a sulfide target (eg, CdS, ZnS, etc.), a nitride target (eg, TiN, etc.). ), one or more of a carbide target (e.g., WC, VC, Cr ₄ C _{3 ,} etc.). The metal target may include, for example, one or more of Ti, Cr, Ni, Cu, Ag, Al, Au, V, Zr, Mo, Nb, In, Sn, Tb, and an alloy therebetween, and the oxide The target may include, for example, one or more of In ₂ O ₃ , SnO ₂ , TiO ₂ , WO ₃ , MoO _{3 ,} and Ga ₂ O ₃ . Preferably, the target material used tends to form a large bonding force with the chip electrode material and the insulating layer material, for example, the same conductive material as the chip electrode can be used. It is easy to understand that the targets used during ion implantation and plasma deposition may be the same target or different targets, thereby correspondingly containing the same or different conductive material groups in the finally obtained conductive seed layer. Minute. Further, ion implantation or plasma deposition may be performed successively using different targets such that the ion implantation layer or the plasma deposition layer is divided into one or more layers in the finally obtained conductive seed layer. The inventors have found that if the substrate is first subjected to ion implantation (injection energy is 1-1000 KeV) and plasma deposition (deposition energy is 1-1000 eV), the bonding force between the conductive seed layer and the substrate thus formed will be It is greatly increased and is therefore preferred. In the case where a conductive copper pillar is to be formed, a Ti, Cr, Ni or Cr-Ni alloy is preferably used as a target for forming a conductive seed layer.

During ion implantation, ions of the conductive material are forcibly injected into the interior of the substrate at a very high rate to form a stable doped structure with the matrix material, which is equivalent to forming a large number of piles under the surface of the substrate. Because of the existence of the pile and the subsequent thickened layer of the conductor is connected to the pile, the joint between the conductor column including the conductive seed layer and the thick layer of the conductor and the substrate is high. It is higher than the bonding force obtained by magnetron sputtering in the prior art (up to 0.5 N/mm). During plasma deposition, ions of the conductive material fly to the substrate at a higher velocity under the action of an accelerating electric field and are deposited thereon to form a plasma deposited layer. The plasma deposition layer and the base material have a large bonding force (greater than 0.5 N/mm), so that the finally produced conductor post is not easily peeled off or peeled off from the substrate. On the other hand, conductive material ions for ion implantation and plasma deposition generally have a size on the order of nanometers, are more uniformly distributed during implantation or deposition, and have little difference in incident angle to the surface of the substrate. Therefore, it is ensured that the obtained conductive seed layer has good uniformity and compactness, and pinholes or cracks are less likely to occur, which is advantageous for improving the junction of the conductor column. Structural integrity, rigidity and electrical conductivity.

After the conductive seed layer is formed, the photoresist is then overlaid on the insulating layer, and an opening is formed in the photoresist by a process such as photolithography which is common in the prior art (step S21). The opening in the photoresist is in communication with a hole previously formed in the insulating layer to expose the surface of the chip electrode, and more specifically to expose a conductive seed layer formed on the surface of the chip electrode. As shown in FIG. 3(c), a photoresist 30 is overlaid over the insulating layer 26, and a hole formed in the insulating layer 26 as shown in FIG. 3(b) is formed in the photoresist 30. 28 connected openings 32. It is easily understood that although the inner wall of the opening 32 shown in FIG. 3(c) is continuous and aligned with the inner wall of the conductive seed layer formed on the wall of the hole 28 in the insulating layer 26, the present invention is not limited thereto. this. For example, the inner diameter of the opening 32 can also be wider than the inner diameter of the aperture 28 or the conductive seed layer formed on the aperture wall of the aperture 28.

Then, in step S22, the holes and openings are filled with a conductive material to form a columnar conductor thickened layer over the conductive seed layer. The thickened layer of the conductor may be treated by one or more of electroplating, electroless plating, vacuum evaporation plating, sputtering, etc., using, for example, Al, Mn, Fe, Ti, Cr, Co, Ni, Cu, Ag, Au. Formed by one or more of V, Zr, Mo, Nb, and an alloy therebetween. Cu, Ag, Au, and Al are widely used in conductive pillars because of their good electrical conductivity. Because of the high speed and low cost of electroplating, and the wide range of electroplatable materials, especially for Cu, Ni, Sn, Ag, and alloys between them, electroplating is commonly used to prepare conductor thickened layers. For some conductive materials (especially Al, Cu, Ag and their alloys), the sputtering speed can reach 100 nm/min, so the conductor thickening layer can be quickly plated on the conductive seed layer using a sputtering method. . Since a uniform, dense conductive seed layer has been formed by ion implantation and/or plasma deposition, it is easy to form a uniform, dense conductor thick layer on the conductive seed layer by the above various methods, and then conduct electricity. The seed layers together form a conductor post. As shown in FIG. 3(d), the hole 28 and the opening 32 are filled with a conductor thickened layer 18 by an electroplating method. When copper is used for electroplating to form the conductor thickened layer 18, a conventional copper pillar is obtained.

Finally, in step S23, the photoresist and the conductive seed layer under it are removed to form a conductor post. As shown in FIG. 3(e), the photoresist 30 around the conductor thickened layer 18 has been removed. In addition, the conductive seed layer under the photoresist 30 has also been removed by etching or the like, resulting in two conductor posts 20 electrically separated from each other. Each conductor post 20 includes a conductive seed layer 16 disposed on the chip electrode surface 12 and a columnar conductor thick layer 18 formed over the conductive seed layer 16. Due to the presence of the ion implantation layer 161, one end of the conductor post 20 is buried inside the chip 10 (specifically, the chip electrode 12), and the other end is located above the surface of the chip 10. Although two separate conductor posts 20 are shown in the figures, it will be readily understood that the number of the resulting conductor posts 20 may be one, or three or more, depending on the number of chip electrodes 12 and, if desired. . Further, it is easily understood that although the conductor post 20 shown in Fig. 3(e) is a solid columnar shape, the present invention is not limited thereto, and the conductor post 20 may be hollow.

4 is a schematic cross-sectional view showing another conductor post produced using the method shown in FIG. 2. In this example, the chip electrode 12 protrudes from the surface of the chip 10 and has a protruding structure. Accordingly, the insulating layer 26 covers the periphery of the chip electrode 12 and the portion of the surface of the chip 10 where the electrode is not formed, and the conductive seed layer 16 is formed on the surface of the chip electrode 12 and on the inner wall of the hole 28 of the insulating layer 26. .

<Second embodiment>

Figure 6 is a flow chart showing a method of manufacturing a conductor post according to a second embodiment of the present invention. The method relates to forming a conductor post on a wall of a hole formed in a hole in a chip, comprising the steps of: drilling a through hole in a chip or two or more chips stacked together, and covering an insulating layer around the through hole ( Step S11); performing ion implantation and/or plasma deposition treatment on the hole walls of the through holes to form a conductive seed layer of two or more chips that are passed through one chip or stacked together (step S12); using a conductive material The via hole is filled (step S21); and, the insulating layer is removed to form a conductor post (step S22). Among them, steps S11 and S12 correspond to step S1 shown in FIG. 1, and steps S21 and S22 correspond to step S2 shown in FIG. 1. Further, FIGS. 7(a)-(d) are schematic cross-sectional views showing the structure corresponding to the steps of the method shown in FIG. 6 in the manufacture of the conductor post, which will be described in detail below.

In step S11, as shown in FIG. 7(a), first, a chip 10 including the chip electrodes 12 or two or more chips 10 stacked together are drilled through holes 36, and then passed through. The periphery of the hole 36 is covered with an insulating layer 26. The through holes 36 may extend through the chip electrodes 12 on the respective chips 10, or may only penetrate the electrodes on some of the chips or some of the electrodes on a particular chip. For example, the through hole 36 may only pass through the left side electrode in the upper layer chip 10 shown in FIG. 7(a) without penetrating the right side electrode. As described in the first embodiment, the insulating layer 26 employed herein may also include materials such as polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), and the like. When two or more chips stacked together are used, the two or more chips may be directly stacked together, or the insulating isolation layer 34 may be interposed between the respective chips as shown in Fig. 7(a). The insulating isolation layer 34 typically uses a common prepreg, and can also use organic highs such as PP, PI, PTO, PC, PSU, PES, PPS, PS, PE, PEI, PTFE, PEEK, PA, PET, PEN, LCP, PPA, etc. Molecular film. Moreover, although embodiments of through holes are common in the art, the invention is not limited thereto. In fact, in addition to the through holes, it is also possible to drill a blind hole for one chip or two or more chips stacked together as long as the blind holes can penetrate the corresponding chip electrodes on the respective chips. When drilling, mechanical drilling, punching, laser drilling, plasma etching and reactive ion etching can be used. Laser drilling can also use infrared laser drilling, YAG laser drilling and UV laser drilling. Micropores having a pore diameter of 2 to 5 μm can be formed on the substrate. The cross-sectional shape of the hole may be various shapes such as a circular shape, a rectangular shape, a ladder shape, and the like, and a hole having an inverted vertical trapezoidal shape in a longitudinal section is usually formed in laser drilling. After the drilling and before the formation of the conductive seed layer on the wall of the hole, the plasma removal or chemical etching method may be used for the removal of the resin to remove the resin or the cutting debris remaining on the wall of the hole during the drilling. Avoid problems with interlayer interconnection and reliability.

In step S12, the hole walls of the via holes are subjected to ion implantation and/or plasma deposition processing to form a conductive seed layer of two or more chips that are passed through one chip or stacked together. At this time, a conductive seed layer including an ion implantation layer and/or a plasma deposition layer is formed on the pore walls of the via holes and on the surface of the insulating layer. As described above, the cross-sectional structure of the conductive seed layer may be any of those shown in FIGS. 5(a) to 5(e), wherein the substrate 22 in this embodiment represents a chip electrode material or a chip substrate, And an insulating layer covering the through hole, and the surface of the substrate 22 indicates the hole wall of the through hole 36 formed in the chip, and the insulating layer s surface. For example, the conductive seed layer formed in step S12 may include only an ion implantation layer implanted under the surface of the substrate, or a plasma deposition layer deposited over the surface of the substrate, or a plasma deposition layer located above the surface of the substrate. And an ion implantation layer implanted into the interior of the plasma deposition layer. Each of the ion implantation layer and the plasma deposition layer may be further divided into two or more layers. In the example shown in FIG. 7(b), the conductive seed layer includes an ion implantation layer 161 formed under the surface of the hole wall 38 of the via hole 36 and the insulating layer 26, and deposited over the ion implantation layer 161. Plasma deposited layer 162. The ion implantation and plasma deposition method can produce a conductive seed layer having a large bonding force with the base material as described above, and the conductive seed layer has good uniformity and compactness, and is not easy to appear. Pinhole or crack phenomenon.

After the conductive seed layer is formed, then in step S21, the via holes in the chip are filled with a conductive material to form a columnar conductor thickened layer over the conductive seed layer. As described above, the conductor thickened layer can be formed by one or more of the methods of electroplating, electroless plating, vacuum evaporation plating, sputtering, and the like. In the example shown in FIG. 7(c), the conductor thickened layer 18 is filled in the through hole 36 formed in the chip 10 by an electroplating method. Although the conductor thickening layer 18 shown in FIG. 7(c) is a solid columnar shape, it is easily understood that the conductor thickening layer 18 may not completely fill the through hole 36, but only has a certain inner wall of the through hole 36. The thickness becomes a hollow column shape. Further, although the conductor thickening layer 18 shown in FIG. 7(c) is formed only in the through hole 36 and is flush with the outer surface of the conductive seed layer formed on the surface of the insulating layer 26, the present invention is not limited. herein. For example, a conductor thickened layer 18 may also be formed on the outside of the via 36 and over the insulating layer 26.

Subsequently, in step S22, the insulating layer is removed to form a conductor post. As shown in Figure 7(d), both the insulating layer 26 and the conductive seed layer above it have been removed, resulting in two conductor posts 20 that are electrically separated from each other. Each of the conductor posts 20 includes a conductive seed layer 16 disposed on the walls of the holes formed in the holes in the chip 10 and a columnar conductor thickened layer 18 formed over the conductive seed layer 16. Both ends of each of the conductor posts 20 protrude outward from the surface of the chip 10 to facilitate subsequent electrical connection to the package substrate. Of course, in the case of forming a blind hole, the conductor post 20 protrudes outward from the surface of the chip 10 only at one end thereof. Although two are shown in the figure The conductor posts 20 are separated, but it will be readily understood that only one, or three or more conductor posts 20 may be prepared corresponding to the number of chip electrodes 12 and as desired. When the insulating layer is removed to form a conductor post, an appropriate stripping solution such as an organic solvent or an alkali solution may be used to dissolve the insulating layer while removing the conductive seed layer above it. In addition, as in the first embodiment, the photoresist may be overlaid over the insulating layer 26, and a portion of the conductive seed layer that does not need to form a conductor post is exposed by photolithography (ie, formed over the insulating layer 26). A portion of the conductive seed layer) is then removed by rapid etching to remove the portion of the conductive seed layer; thereafter, the insulating layer 26 may be stripped or the insulating layer 26 may remain to provide insulating protection to the chip electrodes 12 on the chip 10.

<Third embodiment>

Figure 8 is a flow chart showing a method of manufacturing a conductor post according to a third embodiment of the present invention. The method relates to forming a conductor post on a wiring surface of a package substrate, and comprising the steps of: performing ion implantation and/or plasma deposition processing on a surface of the package substrate to form a conductive seed layer (step S1); on the package substrate Covering the photoresist, forming an opening in the photoresist by photolithography to expose the wiring surface of the package substrate (step S21); filling the opening with a conductive material (step S22); removing the photoresist and the conductive seed layer underneath, To form a conductor post (step S23). Among them, steps S21, S22, and S23 correspond to step S2 shown in FIG. 1. Further, FIGS. 9(a)-(d) are schematic cross-sectional views showing the structure corresponding to the steps of the method shown in FIG. 8 when manufacturing the conductor post. The package substrate used in this embodiment may be a single-layer printed wiring board, or may be a laminated multi-layer substrate with a multilayer wiring pattern or a buried-line coreless board. For ease of understanding, only a single-layer printed wiring board will be described below as an example. Further, the substrate on which the package substrate is prepared may include an organic resin such as BT (bismaleimide triazine) resin, epoxy resin, cyanate resin, polyphenylene ether resin, modified resins thereof, or various thereof. combination.

In step S1, as shown in FIG. 9(a), the surface 42 of the package substrate 40 is successively subjected to ion implantation and plasma deposition processing to form a conductive seed layer including the ion implantation layer 161 and the plasma deposition layer 162. . The ion implantation layer 161 is located below the surface 42 of the package substrate 40, and its outer surface is flush with the surface 42 of the package substrate 40. Isolate The daughter deposited layer 162 is then attached over the ion implantation layer 161 and over the surface 42 of the package substrate 40, the inner surface of which is flush with the surface 42 of the package substrate 40. Although a conductive seed layer including both the ion implantation layer 161 and the plasma deposition layer 162 is shown in FIG. 9(a), it is easily understood that the cross-sectional structure of the conductive seed layer may also be as described above. Any one of 5(a) to 5(e), wherein the substrate 22 in this embodiment represents a wiring material for encapsulating the substrate material and the package substrate (i.e., a material constituting the wiring pattern). For example, the conductive seed layer may include only an ion implantation layer implanted below the surface of the substrate, or a plasma deposition layer deposited over the surface of the substrate, or a plasma deposition layer over the surface of the substrate and implantation into the plasma deposition layer. An ion implantation layer inside the layer. Each of the ion implantation layer and the plasma deposition layer may be further divided into two or more layers. The ion implantation and plasma deposition method can produce a conductive seed layer having a large bonding force with the base material as described above, and the conductive seed layer has good uniformity and compactness, and is not easy to appear. Pinhole or crack phenomenon.

It is easy to understand that although in the example shown in FIG. 9(a), a conductive seed layer is formed directly on the surface 42 of the package substrate, it may be similar to that of FIGS. 3(a) to 3(b). The wiring surface 44 of the package substrate is covered with an insulating layer provided with a hole to expose the surface of the wiring, and then the wiring surface and the insulating layer are simultaneously ion-implanted and/or plasma-deposited to form a pattern similar to FIG. 3 (b). ) a conductive seed layer as shown. In this case, the insulating layer may be left as in the first embodiment to provide insulation protection for the wiring pattern on the package substrate. Further, although the package substrate 40 used in this embodiment is a substrate in which a wiring pattern is buried, a substrate in which a common wiring pattern protrudes from the surface of the substrate may be used. In this case, it is preferable to form a conductive seed layer using a scheme of using an insulating layer as shown in FIGS. 3(a) to 3(b).

Thereafter, a photoresist is coated on the conductive seed layer, and an opening is formed in the photoresist by a conventional photolithography process (step S21) to expose the wiring surface of the package substrate, more specifically, the exposure is formed on A conductive seed layer above the surface of the line. As shown in FIG. 9(b), a photoresist 30 is overlaid over the conductive seed layer, and the photoresist 30 forms an opening 32 directly above the line surface 44.

Then, in step S22, the opening in the photoresist is filled with a conductive material to form a columnar conductor thickened layer over the conductive seed layer. As described above, the conductor thickened layer can be formed by one or more of the methods of electroplating, electroless plating, vacuum evaporation plating, sputtering, and the like. As shown in FIG. 9(c), the conductor thickened layer 18 is filled in the opening 32 formed in the photoresist 30 by an electroplating method. The conductor thickening layer 18 may have a solid column shape as shown in FIG. 9(c), or may have a certain thickness on the inner wall of the opening 32 to have a hollow column shape, for example, when the plating time is short. In addition, although the conductor thickening layer 18 shown in FIG. 9(c) is located in the opening 32 and lower than the outer surface of the photoresist 30, it is easily understood that the conductor thickening layer 18 may also be external to the photoresist 30. The surface is flush or protrudes from the outer surface of the photoresist 30.

Finally, in step S23, the photoresist and the conductive seed layer under it are removed to form a conductor post. As shown in FIG. 9(d), the photoresist 30 around the conductor thickening layer 18 has been removed, and the conductive seed layer under the photoresist 30 has also been removed by etching or the like to obtain two. A conductor post 20 that is electrically separated from each other. Since a conductive seed layer is formed directly on the surface 42 of the package substrate 40 in this embodiment, the material of the package substrate 40 and a portion of the material of the wiring surface thereof are also etched away, resulting in a reduction in the overall thickness of the package substrate 40. small. Each of the two conductor posts 20 includes a conductive seed layer 16 disposed on a wiring surface of the package substrate and a columnar conductor thick layer 18 formed over the conductive seed layer 16. Due to the presence of the ion implantation layer 161, one end of the conductor post 20 is buried inside the package substrate 40 (specifically, the wiring pattern of the package substrate), and the other end is located above the surface of the package substrate 40. Although two separate conductor posts 20 are shown in the figures, it will be readily appreciated that only one, or three or even three or more conductor posts 20 may be fabricated corresponding to the line patterns on the surface of the package substrate and as desired. Further, although the conductor post 20 is shown as a solid column shape in FIG. 9(d), it may be a hollow column shape.

Various methods of making a conductor post in accordance with the present invention are described above. Next, a method of packaging a chip using the conductor post, and a chip flip product manufactured by the packaging method will be described. 10 is a flow chart showing a method of packaging a chip using a conductor post according to the present invention, and FIGS. 11(a)-(e) are diagrams showing a flip chip production after the chip is packaged using a conductor post. Schematic diagram of the structure of the product.

Referring to FIG. 10, a method of packaging a chip using a conductor post according to the present invention includes the steps of: forming a first conductor post on a chip, and/or forming a second conductor post on a wiring surface of the package substrate (step S1); The first conductor post is electrically connected to the wiring surface of the package substrate, or between the second conductor post and the surface of the chip electrode, or between the first conductor post and the second conductor post (step S2). Wherein, the first conductor post and/or the second conductor post may be any one of the conductor posts as described above. That is, the first conductor post may be a conductor post formed on the surface of the chip electrode as shown in FIG. 3(e) or a hole formed in the hole in the chip as shown in FIG. 7(d). A conductor post formed on the wall and penetrating one or more chips, and the second conductor post may be a conductor post formed on the wiring surface of the package substrate as shown in FIG. 9(d). In the case where two conductor posts are used, one of the conductor posts can be a conductor post according to the invention, and the other conductor post can be a conductor post in the prior art. Moreover, the electrical connections can be implemented in any manner known in the art. For example, a solder bump may be placed between the first conductor post and the wiring surface of the package substrate, or between the second conductor post and the surface of the chip electrode, or between the first conductor post and the second conductor post. The following reflow soldering is used to achieve electrical connection. In this case, the wiring surface of the package substrate may include a pad for soldering the first conductor post on the chip side, or the electrode surface of the chip includes a pad for soldering the second conductor post on the package substrate side. In addition, the first conductor post may also be formed on the pad in the chip electrode, and the second conductor post may also be formed on the pad in the circuit pattern of the package substrate. After the electrical connection, the resin may be filled with a resin in the gap between the package substrate and the chip to fix the respective devices, so that the entire package structure is not easily damaged during use or fails due to various environmental factors.

11(a) and 11(b) respectively show a conductor post 20 formed on the surface 14 of the chip electrode as shown in Fig. 3(e), which is opened in the chip as shown in Fig. 7(d) The cross-sectional structure of the chip flip-chip obtained by forming the conductor post 20 of one or more chips on the hole wall of the hole and electrically connecting to the wiring surface 44 of the package substrate 40. Figure 11 (c) shows a cross section of the flip chip product obtained by electrically connecting the conductor post 20 formed on the wiring surface 44 of the package substrate 40 to the chip electrode 12 on the chip 10 as shown in Figure 9 (d). structure. In addition, the map 11(d) and 11(e) respectively show a conductor post 20 formed on the surface 14 of the chip electrode as shown in Fig. 3(e), which is opened in the chip as shown in Fig. 7(d) Flip chip formed by the conductor post 20 formed on the hole wall of the hole and penetrating through the conductor post 20 of one or more chips and the conductor post 20 formed on the line surface 44 of the package substrate 40 shown in FIG. 9(d) The cross-sectional structure of the product. Each of the chip flip products comprises a package substrate, a chip, and a conductor post between the package substrate and the chip and electrically connected thereto. The conductor post comprises a conductive seed layer and a columnar conductor thickened formed above the conductive seed layer. a layer, the conductive seed layer being disposed on a surface of the chip electrode, or on a hole wall of a hole formed in the chip, or on a wiring surface of the package substrate, and including an ion implantation layer and/or a plasma deposition layer.

In the resulting chip flip chip product, the conductor post 20 electrically connecting the chip 10 to the package substrate 40 has a conductive seed layer including an ion implantation layer and/or a plasma deposition layer. As described above, the conductor post has a high bonding force with the substrate, and the resulting chip flip product will also have high stability and reliability, and it is not prone to failure or circuit failure. In addition, since the ion implantation layer and/or the plasma deposition layer have good uniformity and compactness, pinholes or cracks are less likely to occur, and the conductor column also has good structural integrity, rigidity, and electrical conductivity, and thus the resulting The chip flip-chip products will also have excellent robustness, electrical conductivity and thermal properties, and can be widely used in various electronic products.

The above description refers only to the preferred embodiment of the invention. However, the invention is not limited to the specific embodiments described herein. It will be readily apparent to those skilled in the art that various modifications, adaptations and substitutions may be made to these embodiments to adapt to a particular situation without departing from the scope of the invention. Indeed, the scope of the invention is defined by the claims, and may include other examples that are contemplated by those skilled in the art. If such other examples have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements that are not significantly different from the literal language of the claims, they are intended to fall within the scope of the appended claims .

Claims (24)

1. A method of manufacturing a conductor post comprising the steps of:

   S1: performing ion implantation and/or plasma deposition treatment on the surface of the chip electrode, or the hole wall of the hole formed in the chip, or the wiring surface of the package substrate to form a conductive seed layer using the target;

   S2: forming a columnar conductor thickening layer above the conductive seed layer, the conductor thickening layer and the conductive seed layer forming the conductor post.
2. The method according to claim 1, wherein in step S1, plasma deposition is performed after ion implantation.
3. The method according to claim 1, wherein during ion implantation, ions of said target obtain an energy of 1-1000 keV and are injected into a surface of said chip electrode or a hole wall or said hole of said hole Below the surface of the wiring of the package substrate, an ion implantation layer is formed as at least a portion of the conductive seed layer.
4. The method according to claim 1, wherein during the plasma deposition, the ions of the target obtain an energy of 1-1000 eV and are deposited on the surface of the chip electrode or the hole wall of the hole or Above the wiring surface of the package substrate, a plasma deposition layer is formed as at least a portion of the conductive seed layer.
5. The method according to claim 1, wherein said conductive seed layer comprises Ti, Cr, Ni, Cu, Ag, Al, Au, V, Zr, Mo, Nb, In, Sn, Tb, and the like One or more of the intervening alloys, the conductor thickening layer comprising one or more of Cu, Ag, Al, Au, and an alloy therebetween.
6. The method according to claim 1, wherein the conductor post is in the form of a solid or hollow column, one end of which is buried inside the chip or the package substrate, and the other end is located above the surface of the chip or the package substrate.
7. A method according to any one of claims 1 to 6, wherein

   In step S1, an insulating layer provided with a hole is first covered on a periphery of the chip electrode, and then a hole wall of the hole and a surface of the chip electrode exposed to the hole are performed. Ion implantation and/or plasma deposition treatment to form the conductive seed layer,

   In step S2, a photoresist is first coated on the insulating layer, an opening communicating with the hole is formed in the photoresist by photolithography, and then the hole and the opening are filled with a conductive material, and The conductor post is formed after the photoresist and the conductive seed layer below it are removed.
8. A method according to any one of claims 1 to 6, wherein

   In step S1, a chip or two or more chips stacked together are drilled through, and an insulating layer is covered around the through hole, and then the ion implantation is performed on the hole wall of the through hole. And/or plasma deposition treatment to form a conductive seed layer of the two or more chips that are passed through the chip or stacked together,

   In step S2, the via hole is filled with a conductive material, and the conductor post is formed after the insulating layer is removed.
9. A method according to any one of claims 1 to 6, wherein

   In step S1, performing the ion implantation and/or plasma deposition treatment on the surface of the package substrate to form the conductive seed layer.

   In step S2, a photoresist is first coated on the package substrate, an opening is formed in the photoresist by photolithography to expose a wiring surface of the package substrate, and then the opening is filled with a conductive material, and The conductor post is formed after removing the photoresist and the conductive seed layer below it.
10. The method according to claim 9, wherein the two or more chips are directly laminated together or an insulating isolation layer is disposed between the chips.
11. A conductor post comprising a conductive seed layer and a columnar conductor thickening layer formed over the conductive seed layer, the conductive seed layer being disposed on a surface of the chip electrode or in a hole formed in the chip The hole walls, or on the wiring surface of the package substrate, and include an ion implantation layer and/or a plasma deposition layer.
12. The conductor post according to claim 11, wherein the ion implantation layer is located on a surface of the chip electrode or a hole wall of the hole or a line surface of the package substrate, and is made of a chip electrode material or Chip substrate or circuit board of package substrate a doped structure composed of a material and a conductive material.
13. The conductor post according to claim 11, wherein the plasma deposition layer is located on a surface of the chip electrode or a hole wall of the hole or a wiring surface of the package substrate.
14. The conductor post according to claim 11, wherein said conductive seed layer comprises Ti, Cr, Ni, Cu, Ag, Al, Au, V, Zr, Mo, Nb, In, Sn, Tb and One or more of the alloys between, the conductor thickening layer comprising one or more of Cu, Ag, Al, Au, and an alloy therebetween.
15. The conductor post according to claim 11, wherein the conductor post is in the form of a solid or hollow column, one end of which is buried inside the chip or the package substrate, and the other end is located above the surface of the chip or the package substrate. .
16. A method of packaging a chip using a conductor post, comprising the steps of:

    S1: forming a first conductor post on the chip, and/or forming a second conductor post on a line surface of the package substrate;

    S2: between the first conductor post and the wiring surface of the package substrate, or between the second conductor post and the surface of the chip electrode, or between the first conductor post and the second conductor post Electrical connection,

    Wherein the first conductor post and/or the second conductor post is a conductor post produced by the method according to any one of claims 1 to 10, or the method according to any one of claims 11 to 15. Conductor column.
17. The method of claim 16 wherein said chip comprises two or more chips stacked together and said first conductor post extends through said two or more chips.
18. The method of claim 16 wherein said electrical connection is performed by reflow soldering.
19. The method of claim 16 wherein the wiring surface of the package substrate includes a pad for soldering the first conductor post, or the surface of the chip electrode includes a pad for soldering Second conductor post.
20. A chip flip-chip product comprising a package substrate, a chip, and a conductor post between the package substrate and the chip and electrically connecting the same, the conductor post comprising a conductive seed layer and the conductive seed layer a columnar conductor thickening layer formed above, the conductive seed layer being disposed on a surface of the chip electrode, or on a hole wall of a hole formed in the chip, or on a wiring surface of the package substrate, and including an ion implantation layer And/or a plasma deposited layer.
21. The flip chip product according to claim 20, wherein the ion implantation layer is located on a surface of the chip electrode or a hole wall of the hole or below a line surface of the package substrate, and is a chip electrode A doped structure composed of a material or a chip substrate or a wiring material of the package substrate, and a conductive material.
22. The chip flip-chip product according to claim 20, wherein the plasma deposition layer is located on a surface of the chip electrode or a hole wall of the hole or a wiring surface of the package substrate.
23. The flip chip product according to claim 20, wherein the conductor post is in the form of a solid or hollow column, one end of which is buried inside the chip or the package substrate, and the other end of which is located on the chip or the package substrate. Above the surface.
24. The chip flip-chip product according to claim 20, wherein the conductive seed layer of the conductor post runs through a chip or two or more chips stacked together.

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