JPH0974097A - Formation of barrier metal - Google Patents
Formation of barrier metalInfo
- Publication number
- JPH0974097A JPH0974097A JP7230406A JP23040695A JPH0974097A JP H0974097 A JPH0974097 A JP H0974097A JP 7230406 A JP7230406 A JP 7230406A JP 23040695 A JP23040695 A JP 23040695A JP H0974097 A JPH0974097 A JP H0974097A
- Authority
- JP
- Japan
- Prior art keywords
- film
- barrier metal
- solder
- wafer
- subjected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00015—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はバリアメタルの形成
方法に関し、詳しくはフリップチップＩＣのバンプの下
地となるバリアメタルの形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a barrier metal, and more particularly, to a method of forming a barrier metal which is a base of bumps of a flip chip IC.
【０００２】[0002]
【従来の技術】電子機器の小型化をより一層進展させる
ためには、部品実装密度を如何に向上させるかが重要な
ポイントとなる。こと半導体ＩＣに関しても、従来のパ
ッケージ実装の代替えとして、フリップチップによる高
密度実装技術の開発が盛んに行われている。フリップチ
ップ実装法には、Ａｕスタッドバンプ法や半田ボールバ
ンプ法等いくつかの手法があるが、いずれの場合も半導
体ＩＣの電極パッドとバンプ材料との間には、密着性向
上や相互拡散防止等を目的にバリアメタルが使われる。
半田ボールバンプの場合、このバリアメタルがバンプの
仕上がり形状を決定する役目をなす意味から、ＢＬＭ
（Ｂａｌｌ Ｌｉｍｉｔｔｉｎｇ Ｍｅｔａｌ）とも呼
ばれている。半田バンプに於けるＢＬＭ膜の構造として
は、Ｃｒ、Ｃｕ、Ａｕの三層構造が最も一般的である。
このうち、下層のＣｒ層は電極パッドとの密着層とし
て、Ｃｕ膜は半田の拡散防止層として、上層のＡｕ金属
膜はＣｕの酸化防止膜としてそれぞれ作用する。2. Description of the Related Art In order to further reduce the size of electronic equipment, it is important to improve the component mounting density. Regarding semiconductor ICs, high-density packaging technology using flip chips has been actively developed as an alternative to conventional package packaging. There are several methods such as Au stud bump method and solder ball bump method in the flip chip mounting method. In any case, the adhesion between the electrode pad of the semiconductor IC and the bump material is improved and mutual diffusion is prevented. Barrier metal is used for the purpose.
In the case of solder ball bumps, this barrier metal plays the role of determining the finished shape of the bumps, and therefore BLM
It is also called (Ball Limiting Metal). The most common structure of the BLM film in the solder bump is a three-layer structure of Cr, Cu, and Au.
Among them, the lower Cr layer acts as an adhesion layer with the electrode pad, the Cu film acts as a solder diffusion preventing layer, and the upper Au metal film acts as a Cu antioxidant film.
【０００３】このＢＬＭ膜をＩＣのＡｌ電極パッド上に
パターンニングした後、半田を成膜し、加熱して最終的
にボール状のバンプを形成する。その工程の例を図１を
参照して説明する。After patterning this BLM film on the Al electrode pads of the IC, solder is formed and heated to finally form ball-shaped bumps. An example of the process will be described with reference to FIG.
【０００４】フリップチップＩＣの接合部は、シリコン
等の半導体基体２の上にＡｌ等の電極パッド３をスパッ
タやエッチングを用いて形成し、ポリイミドやシリコン
窒化膜等による表面保護膜４ａを全面に被覆した後、電
極パッド３上に接続孔５を形成して、ＢＬＭ膜６を形成
する（図１（ａ）参照）。さらに、ＢＬＭ膜６の上に、
接続孔５を有するレジスト膜７を形成し（図１（ｂ）参
照）、その全面に半田膜８を成膜して（図１（ｃ）参
照）、リフトオフによるパターンニングを行った後（図
１（ｄ）参照）、加熱し半田を溶融して、最終的に図１
（ｅ）に示すような半田のボール状バンプ９を形成す
る。（ウエットバック工程と称される）。At the bonding portion of the flip chip IC, an electrode pad 3 made of Al or the like is formed on a semiconductor substrate 2 made of silicon or the like by sputtering or etching, and a surface protective film 4a made of polyimide or a silicon nitride film is formed on the entire surface. After covering, the connection hole 5 is formed on the electrode pad 3 to form the BLM film 6 (see FIG. 1A). Furthermore, on the BLM film 6,
After forming a resist film 7 having connection holes 5 (see FIG. 1B), forming a solder film 8 on the entire surface (see FIG. 1C), and performing patterning by lift-off (see FIG. 1C). 1 (d)), heat to melt the solder, and finally
The ball-shaped bumps 9 of solder as shown in (e) are formed. (It is called a wet back process).
【０００５】この際、最後のウエットバック工程の熱処
理条件によっては、バンプの密着強度が低下してしま
い、プリント配線基板へのチップ実装時にバンプがチッ
プから欠落したり、Ａｌ電極との電気的コンタクト特性
に不良が生じる等の問題が起きる。これらの問題は、主
としてＣｕ層の半田に対するバリア効果が充分に得られ
ていないことが原因であり、種々の熱処理によってＣｕ
中を半田が拡散してＣｕ層を分離したり、下層のＣｒ層
にまで半田が達してしまうことで、Ａｌ電極パッドと半
田バンプとの界面での密着力が大きく低下するために生
じている。こうした背景から、半田の熱拡散に対するバ
リア効果に優れるＢＬＭ膜の成膜方法を確立することが
必要となっている。At this time, depending on the heat treatment conditions of the final wet-back step, the adhesion strength of the bumps is lowered, and the bumps may be missing from the chip when the chip is mounted on the printed wiring board or may be electrically contacted with the Al electrode. Problems such as defective characteristics occur. These problems are mainly due to the fact that the barrier effect of the Cu layer on the solder is not sufficiently obtained, and the various heat treatments cause the Cu effect.
This is caused by the fact that the solder diffuses inside to separate the Cu layer and reach the lower Cr layer, so that the adhesion at the interface between the Al electrode pad and the solder bump is greatly reduced. . From such a background, it is necessary to establish a film forming method of a BLM film having an excellent barrier effect against thermal diffusion of solder.
【０００６】[0006]
【発明が解決しようとする課題】そこで本発明の課題
は、フリップチップＩＣ等のボールバンプ形成の際のバ
リアメタル（ＢＬＭ膜）の形成方法を改良し、半田の熱
拡散を生じない等のバリア効果の良いバリアメタルの形
成方法を提供することである。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to improve the method of forming a barrier metal (BLM film) when forming a ball bump of a flip chip IC or the like, and to prevent thermal diffusion of solder. It is to provide a method for forming an effective barrier metal.
【０００７】[0007]
【課題を解決するための手段】かかる課題を解決するた
めに、請求項１の発明に係るバリアメタルの形成方法
は、異種金属を含有したターゲットを用いてスパッタに
より成膜し、成膜後にパターンニングをする構成とし、
バリアメタルの結晶粒界に金属間化合物を偏析させ、半
田の熱拡散を防止する。In order to solve such a problem, the method of forming a barrier metal according to the invention of claim 1 forms a film by sputtering using a target containing a dissimilar metal, and then forms a pattern. Configuration
Intermetallic compounds are segregated at the crystal grain boundaries of the barrier metal to prevent thermal diffusion of solder.
【０００８】請求項２の発明に係るバリアメタルの形成
方法は、パターンニングの後に、１００℃〜４００℃以
下の温度で、且つ低酸素濃度の雰囲気下でアニール処理
を行うことを特徴とする請求項１記載のバリアメタルの
形成方法の構成とし、バリアメタルの結晶粒界に金属間
化合物を偏析させ、半田の熱拡散を防止する。The barrier metal forming method according to the invention of claim 2 is characterized in that after patterning, an annealing treatment is performed at a temperature of 100 ° C. to 400 ° C. or less and in an atmosphere of low oxygen concentration. The structure of the method for forming a barrier metal according to Item 1, wherein an intermetallic compound is segregated at a crystal grain boundary of the barrier metal to prevent thermal diffusion of solder.
【０００９】請求項３の発明に係るバリアメタルの形成
方法はターゲットがＳｎ、Ｔｉ、Ａｌ、Ｍｇ、Ｓｉ、Ｐ
ｔ、Ｐｄ、Ｓｃ、Ｃｒ、Ｔａ、Ｃｕから選ばれた少なく
とも１種類の金属を不純物として含有し、Ｃｕ、Ｎｉ、
Ｔｉ、Ｗ、Ａｇ、Ｍｏから選ばれる少なくとも１種類の
金属を基にする金属材料であることを特徴とする請求項
１記載のバリアメタルの形成方法の構成とし（但し、同
種金属の組み合わせは除外する）、バリアメタルの結晶
粒界に金属間化合物を偏析させ、半田の熱拡散を防止す
る。In the method of forming a barrier metal according to the third aspect of the invention, the target is Sn, Ti, Al, Mg, Si, P.
At least one metal selected from t, Pd, Sc, Cr, Ta and Cu is contained as an impurity, and Cu, Ni,
The method of forming a barrier metal according to claim 1, wherein the metal material is a metal material based on at least one metal selected from Ti, W, Ag, and Mo (however, a combination of the same metal is excluded. Yes, the intermetallic compound is segregated at the crystal grain boundaries of the barrier metal to prevent thermal diffusion of the solder.
【００１０】[0010]
【実施例】以下、図１ないし図３を参照して本発明のバ
リアメタルの形成方法について説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for forming a barrier metal according to the present invention will be described below with reference to FIGS.
【００１１】実施例１ 本実施例は、半田のボール状バンプ形成プロセスにおけ
るＢＬＭ（ＢａｌｌＬｉｍｉｔｔｉｎｇ Ｍｅｔａｌ）
膜の形成方法に本発明を適用したものである。本実施例
において、サンプルとして使用した被処理基板１（ウエ
ハ）は、図２（ａ）に示す様に、半導体基体２のアルミ
ニューム（Ａｌ）から成る電極パッド３上にポリイミド
またはシリコン窒化膜等のパッシベイション膜（表面保
護膜）４ａを形成し、所定の寸法に接続孔５が穿孔さ
れ、さらにその上層にフォトレジスト膜４ｂがパッシベ
イション膜４ａよりも大きな開口径でパターニングされ
たものを準備した。Example 1 In this example, a BLM (Ball Limiting Metal) in a process of forming a ball-shaped bump of solder is used.
The present invention is applied to a film forming method. The substrate 1 (wafer) to be processed used as a sample in this embodiment is, as shown in FIG. 2A, a polyimide or silicon nitride film or the like on the electrode pad 3 made of aluminum (Al) of the semiconductor substrate 2. A passivation film (surface protection film) 4a is formed, a connection hole 5 is punched to a predetermined size, and a photoresist film 4b is further patterned thereon with an opening diameter larger than that of the passivation film 4a. Prepared.
【００１２】このウエハ１をスパッタ装置にセットし、
高周波プラズマによる成膜前処理を行った後（図２
（ｂ）参照）、以下の条件でＢＬＭ膜を成膜した。 １．Ｔｉ膜の成膜（Ａｌとの密着層形成） ＤＣ電力：４．０ｋＷ、Ａｒ：１００ｓｃｃｍ、圧力：
０．７Ｐａ、ウエハステージ：室温、厚さ：０．１μｍ ２．Ｃｕ−Ｔｉの成膜（半田のバリアメタル形成） Ｃｕ−３％Ｔｉ合金ターゲットを使用 ＤＣ電力：６．０ｋＷ、Ａｒ：１００ｓｃｃｍ、圧力：
０．７Ｐａ、ウエハステージ：室温、厚さ：１．０μｍ ３．Ａｕ成膜（バリアメタルの酸化防止膜形成） ＤＣ電力：４．０ｋＷ、Ａｒ：１００ｓｃｃｍ、圧力：
０．７Ｐａ、ウエハステージ：室温、厚さ：０．１μｍThis wafer 1 is set in a sputtering device,
After performing pretreatment for film formation with high-frequency plasma (Fig. 2
(See (b)), the BLM film was formed under the following conditions. 1. Formation of Ti film (formation of adhesion layer with Al) DC power: 4.0 kW, Ar: 100 sccm, pressure:
0.7 Pa, wafer stage: room temperature, thickness: 0.1 μm 2. Cu-Ti film formation (formation of solder barrier metal) Cu-3% Ti alloy target is used DC power: 6.0 kW, Ar: 100 sccm, pressure:
0.7 Pa, wafer stage: room temperature, thickness: 1.0 μm 3. Au film formation (formation of barrier metal anti-oxidation film) DC power: 4.0 kW, Ar: 100 sccm, pressure:
0.7 Pa, wafer stage: room temperature, thickness: 0.1 μm
【００１３】ＢＬＭ成膜後の状態を図２（ｃ）に示す。
高周波プラズマによる成膜前処理によって、オーバーハ
ング状に形状制御された下地レジストパターンの側壁面
には、メタルが成膜されることなく、ＢＬＭ膜６は電極
パッド３上の接続孔５とフォトレジスト膜４ｂ上で分断
された。そして、この状態のウエハ１をレジスト剥離液
に浸して加熱揺動処理した結果、図２（ｄ）に示す様
に、フォトレジスト膜４ｂ上に成膜された不要なＢＬＭ
膜は、レジスト剥離と同時にリフトオフされ、接続孔５
の所定の場所へＢＬＭ膜のパターンが形成された。The state after the BLM film formation is shown in FIG.
The BLM film 6 is formed on the side wall surface of the underlying resist pattern whose shape is controlled to be overhanged by the film forming pretreatment by the high frequency plasma without forming the metal, and the BLM film 6 is formed on the contact hole 5 on the electrode pad 3 and the photoresist. It was split on membrane 4b. Then, the wafer 1 in this state is dipped in a resist stripping solution and subjected to a heating and rocking process, and as a result, as shown in FIG. 2D, unnecessary BLM formed on the photoresist film 4b.
The film is lifted off at the same time when the resist is peeled off, and the connection hole 5
The pattern of the BLM film was formed at a predetermined position of.
【００１４】次に、この状態のウエハを加熱処理装置に
セットし、以下の条件でアニール処理した。 条件：窒素雰囲気、酸素濃度５０ｐｐｍ以下、温度３０
０℃、時間３０分 この結果、バリアメタルのＣｕ層の結晶粒界にはＣｕＴ
ｉ化合物が偏析し、粒界強度が増加した。Next, the wafer in this state was set in a heat treatment apparatus and annealed under the following conditions. Conditions: nitrogen atmosphere, oxygen concentration 50 ppm or less, temperature 30
As a result, CuT is present at the crystal grain boundaries of the barrier metal Cu layer at 0 ° C. for 30 minutes.
The i compound was segregated and the grain boundary strength increased.
【００１５】この後、高融点半田（Ｐｂ：Ｓｎ＝９７：
３）の成膜とパターンニングを行い（図１（ａ）〜
（ｄ）参照）、ウエットバック工程でフラックス塗布と
加熱処理を行った結果、図１（ｅ）に示す様に半田のボ
ール状バンプ９が形成できた。After this, high melting point solder (Pb: Sn = 97:
3) Film formation and patterning are performed (FIG. 1 (a)-
(D)), as a result of performing flux application and heat treatment in the wet back process, solder ball-shaped bumps 9 were formed as shown in FIG. 1 (e).
【００１６】この様にしてバンプが形成されたＩＣチッ
プを印刷配線基板上にフリップチップ実装した製品は、
過酷な条件下で熱サイクル試験を施した場合でも、ＢＬ
Ｍ膜の半田に対するバリア効果が向上した結果、半田バ
ンプとＡｌ電極パッドとのコンタクト界面での電気特性
や密着度の劣化を招くことがなくなり、製品の信頼性及
び耐久性が大幅に改善された。A product in which an IC chip having bumps thus formed is flip-chip mounted on a printed wiring board is
Even if a thermal cycle test is performed under severe conditions, BL
As a result of the improvement of the barrier effect of the M film against solder, deterioration of electrical characteristics and adhesion at the contact interface between the solder bump and the Al electrode pad is not caused, and the product reliability and durability are significantly improved. .
【００１７】尚、図３に示すスパッタ装置は良く知られ
た平行平板型の高周波プラズマ装置であるが、その構成
と動作について簡単に説明する。まず基板ステージ１１
上には、被処理基板１２が載置され、所定間隔をおいて
陽極板１３が配置され、これらは密閉室１４内に置かれ
る。密閉室１４内にはＡｒガスが供給される。そして、
基板ステージ１１には結合コンデンサ１５を通じて、高
周波電源１６が接続される。一方、陽極板１３は接地さ
れる。The sputtering apparatus shown in FIG. 3 is a well-known parallel plate type high frequency plasma apparatus, but its configuration and operation will be briefly described. First, the substrate stage 11
A substrate 12 to be processed is placed on top of which an anode plate 13 is arranged at a predetermined interval, and these are placed in a closed chamber 14. Ar gas is supplied into the closed chamber 14. And
A high frequency power supply 16 is connected to the substrate stage 11 through a coupling capacitor 15. On the other hand, the anode plate 13 is grounded.
【００１８】この構成によって、基板ステージ１１と陽
極板１３の間にプラズマが発生され基板ステージ１１上
に載置された被処理基板１２を前処理できる。With this structure, plasma can be generated between the substrate stage 11 and the anode plate 13 to pretreat the substrate 12 to be processed placed on the substrate stage 11.
【００１９】実施例２ 本実施例は、同じく半田のボール状バンプ形成プロセス
におけるＢＬＭ膜の形成に本発明を適用した他の例であ
り、図２を参照しながら説明する。本実施例においてサ
ンプルとして使用したウエハは、前述の実施例で用いた
ものと同じである（図２（ａ）参照）。このウエハ１を
スパッタ装置にセットし、高周波プラズマによる成膜前
処理を行った後（図２（ｂ）参照）、以下の条件でＢＬ
Ｍ膜を成膜した。Example 2 This example is another example in which the present invention is applied to the formation of the BLM film in the ball-shaped bump forming process of the solder, and will be described with reference to FIG. The wafer used as a sample in this example is the same as that used in the above-described example (see FIG. 2A). After setting this wafer 1 in the sputtering apparatus and performing pretreatment for film formation by high-frequency plasma (see FIG. 2B), BL under the following conditions
An M film was formed.
【００２０】条件 １．Ｃｒ成膜（Ａｌとの密着層形成） ＤＣ電力：４．０ｋＷ、Ａｒ：１００ｓｃｃｍ、圧力：
０．７Ｐａ、ウエハステージ：室温、厚さ：０．１μｍ ２．Ｃｕ−Ｓｎの成膜（半田のバリアメタル形成） Ｃｕ−３％Ｓｎ合金ターゲットを使用 ＤＣ電力：６．０ｋＷ、Ａｒ：１００ｓｃｃｍ、圧力：
０．７Ｐａ、ウエハステージ：室温、厚さ：１．０μｍ ３．Ａｕ成膜（バリアメタルの酸化防止膜形成） ＤＣ電力：４．０ｋＷ、Ａｒ：１００ｓｃｃｍ、圧力：
０．７Ｐａ、ウエハステージ：室温、厚さ：０．１μｍConditions 1. Cr film formation (adhesion layer formation with Al) DC power: 4.0 kW, Ar: 100 sccm, pressure:
0.7 Pa, wafer stage: room temperature, thickness: 0.1 μm 2. Cu-Sn film formation (formation of solder barrier metal) Cu-3% Sn alloy target is used DC power: 6.0 kW, Ar: 100 sccm, pressure:
0.7 Pa, wafer stage: room temperature, thickness: 1.0 μm 3. Au film formation (formation of barrier metal anti-oxidation film) DC power: 4.0 kW, Ar: 100 sccm, pressure:
0.7 Pa, wafer stage: room temperature, thickness: 0.1 μm
【００２１】次に、実施例１と同様にしてリフトオフに
よるＢＬＭ膜のパターンニングを行い、以下の条件でア
ニール処理した。 条件：窒素雰囲気、酸素濃度５０ｐｐｍ以下、温度３０
０℃、時間３０分 この結果、バリアメタルのＣｕ層の結晶粒界にはＣｕＳ
ｎ化合物が偏析し、粒界強度が増加した。この後、高融
点半田のパターンニングとウエットバック処理を行った
結果、実施例１と同様に図１（ｅ）に示すごとく、半田
のボール状バンプが形成された。最終的に金属膜（ＢＬ
Ｍ膜）の良好なパターン形成を実現できた。Next, the BLM film was patterned by lift-off in the same manner as in Example 1 and annealed under the following conditions. Conditions: nitrogen atmosphere, oxygen concentration 50 ppm or less, temperature 30
As a result, CuS is present at the crystal grain boundaries of the barrier metal Cu layer.
The n compound segregated and the grain boundary strength increased. After that, patterning of the high melting point solder and wet back processing were performed, and as a result, solder ball-shaped bumps were formed as shown in FIG. Finally the metal film (BL
Good pattern formation of (M film) could be realized.
【００２２】本実施例を用いて、バンプを形成したＩＣ
チップを印刷配線基板上にフリップチップ実装した製品
についても、ＢＬＭ膜の半田に対するバリア効果が向上
した結果、過酷な熱サイクル試験を施した場合の半田バ
ンプとＡｌ電極パッドとのコンタクト界面での電気特性
や密着強度の劣化が抑制され、製品の信頼性および耐久
性が大幅に改善された。さらに、本実施例の場合、アニ
ール処理によってバリアメタルの結晶粒界にＣｕＳｎ化
合物が均一に析出するため、バリアメタルのＣｕと半田
中のＳｎとの相互拡散速度の違いに起因して従来頻繁に
生じていたバリアメタル中のボイド不良（カーケンダル
効果）の発生も完全に抑制されるようになった。An IC having bumps formed by using this embodiment
As for the product in which the chip is flip-chip mounted on the printed wiring board, the barrier effect against the solder of the BLM film is improved, and as a result, the electrical property at the contact interface between the solder bump and the Al electrode pad when subjected to a severe thermal cycle test Deterioration of properties and adhesion strength was suppressed, and product reliability and durability were greatly improved. Further, in the case of the present embodiment, since the CuSn compound is uniformly deposited on the crystal grain boundaries of the barrier metal by the annealing treatment, it is frequently used conventionally due to the difference in the mutual diffusion rate between Cu of the barrier metal and Sn in the solder. The occurrence of void defects (Kirkendal effect) in the barrier metal, which had occurred, is now completely suppressed.
【００２３】以上、本発明を２種類の実施例に基づいて
説明したが、本発明はこれらの実施例に何ら限定される
ものではない。例えば、バリアメタルを形成する合金タ
ーゲットとして本実施例では、Ｃｕ−Ｔｉ合金、Ｃｕ−
Ｓｎ合金を用いた例を示したが、これ以外にもＣｕ−Ｎ
ｉ合金、Ｃｕ−Ｐｔ合金、Ｃｕ−Ｐｔ合金、Ｃｕ−Ａｌ
合金、Ｎｉ−Ａｌ合金、Ｎｉ−Ｐｔ合金、Ｎｉ−Ｐｄ合
金、Ｎｉ−Ｃｕ合金、Ｔｉ−Ｗ、Ｗ−Ｍｇ、Ａｇ−Ｓ
ｉ、Ｍｏ−Ｓｃ、Ｃｕ−Ｔａ、Ｃｕ−Ｓｉ合金を用いる
ことができる。Although the present invention has been described based on the two embodiments, the present invention is not limited to these embodiments. For example, in the present embodiment, as an alloy target for forming a barrier metal, Cu-Ti alloy, Cu-
An example using a Sn alloy is shown, but Cu-N is also available.
i alloy, Cu-Pt alloy, Cu-Pt alloy, Cu-Al
Alloy, Ni-Al alloy, Ni-Pt alloy, Ni-Pd alloy, Ni-Cu alloy, Ti-W, W-Mg, Ag-S
i, Mo-Sc, Cu-Ta, and Cu-Si alloys can be used.
【００２４】また本実施例ではバリアメタルのパターン
形成方法として、フォトレジストのリフトオフを用いた
例を示したが、それ以外のエッチング方法等を用いた製
法への適用も可能である。さらに、本実施例ではバリア
メタルのパターン形成方法として、真空蒸着による成膜
とフォトレジストのリフトオフを用いて説明したが、そ
れ以外の電解メッキ等を用いた製法への適用も可能であ
る。それ以外にも、サンプル構造、メタル成膜条件、ア
ニール条件等発明の主旨を逸脱しない範囲で適宜選択可
能であることは言うまでもない。Further, in this embodiment, as an example of using the lift-off of the photoresist as the method of forming the barrier metal pattern, the manufacturing method using an etching method other than that is applicable. Further, in the present embodiment, the barrier metal pattern forming method has been described by using the film formation by vacuum evaporation and the lift-off of the photoresist, but it can be applied to other manufacturing methods using electrolytic plating or the like. It goes without saying that other than that, the sample structure, the metal film forming condition, the annealing condition and the like can be appropriately selected without departing from the spirit of the invention.
【００２５】[0025]
【発明の効果】本発明の採用により、バリアメタルのＣ
ｕやＮｉの結晶粒界が強化され、半田の熱拡散を効果的
に防止できる。これにより、バンプが形成されたＩＣチ
ップを印刷配線基板上にフリップチップ実装して組立て
られた製品の信頼性や耐久性を大幅に向上することがで
きる。したがって、本発明によれば、更に微細化の進ん
だデザインルールに基づいて設計され、高集積度、高性
能、高信頼性が要求される半導体装置の製造に極めて有
効である。By adopting the present invention, the barrier metal C
The crystal grain boundaries of u and Ni are strengthened, and thermal diffusion of solder can be effectively prevented. As a result, it is possible to significantly improve the reliability and durability of the product assembled by flip-chip mounting the IC chip having the bumps formed on the printed wiring board. Therefore, according to the present invention, it is extremely effective for manufacturing a semiconductor device which is designed based on a design rule which is further miniaturized and which requires high integration, high performance and high reliability.
【図１】 半田のボール状バンプの製造工程におけるウ
エハの側断面図であり、（ａ）は電極パッド上にＢＬＭ
膜が成膜された状態、（ｂ）はレジスト膜が形成された
状態、（ｃ）はウエハ全面に半田膜が成膜された状態、
（ｄ）は不要な半田膜が除去された状態、（ｅ）はウエ
ットバック工程によって半田のボール状バンプが形成さ
れた状態を示す。FIG. 1 is a side cross-sectional view of a wafer in a solder ball bump manufacturing process, in which (a) is a BLM on an electrode pad.
A state where a film is formed, (b) a state where a resist film is formed, (c) a state where a solder film is formed on the entire surface of the wafer,
(D) shows a state in which an unnecessary solder film is removed, and (e) shows a state in which solder ball-shaped bumps are formed by a wet-back process.
【図２】 ＢＬＭ膜が形成されるまでの各工程における
ウエハの側断面図であり、（ａ）はフォトレジスト膜が
形成された状態、（ｂ）は高周波プラズマによる成膜前
処理によって、フォトレジストパターンの開口端がオー
バーハング状に変化した状態、（ｃ）はウエハ全面にＢ
ＬＭ膜が成膜された状態、（ｄ）はＢＬＭ膜のパターン
ニングが終了した状態を示す。2A and 2B are side cross-sectional views of a wafer in respective steps until a BLM film is formed. FIG. 2A is a state in which a photoresist film is formed, and FIG. A state in which the opening end of the resist pattern is changed to an overhang shape, (c) shows B over the entire surface of the wafer
The state where the LM film is formed, and (d) shows the state where the patterning of the BLM film is completed.
【図３】 成膜前処理に用いる平行平板型プラズマ処理
装置の概略の原理図である。FIG. 3 is a schematic principle view of a parallel plate type plasma processing apparatus used for film formation pretreatment.
１ ウエハ（被処理基板） ２ 半導体基体 ３ 電極パッド ４ａ パッシベーション膜（表面保護膜） ４ｂ フォトレジスト膜 ５ 接続孔 ６ バリアメタル（ＢＬＭ膜） ７ レジスト膜 ８ 半田膜 ９ バンプ １０ 平行平板型高周波プラズマ装置 １１ 基板ステージ（陰極板） １２ 被処理基板 １３ 陽極板 １４ 密閉室 １５ 結合コンデンサ １６ 高周波電源 DESCRIPTION OF SYMBOLS 1 Wafer (substrate to be processed) 2 Semiconductor substrate 3 Electrode pad 4a Passivation film (surface protection film) 4b Photoresist film 5 Connection hole 6 Barrier metal (BLM film) 7 Resist film 8 Solder film 9 Bump 10 Parallel plate type high frequency plasma device 11 substrate stage (cathode plate) 12 substrate to be processed 13 anode plate 14 closed chamber 15 coupling capacitor 16 high frequency power supply
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/92 ６０４Ｎ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H01L 21/92 604N
Claims (3)
スパッタにより成膜し、 前記成膜後にパターンニングをすることを特徴とするバ
リアメタルの形成方法。1. A method of forming a barrier metal, comprising forming a film by sputtering using a target containing a different metal, and patterning after the film formation.
４００℃以下の温度で、且つ低酸素濃度の雰囲気下でア
ニール処理を行うことを特徴とする請求項１記載のバリ
アメタルの形成方法。2. After the patterning, 100 ° C. to
The method for forming a barrier metal according to claim 1, wherein the annealing treatment is performed at a temperature of 400 ° C. or less and in an atmosphere of low oxygen concentration.
ｇ、Ｓｉ、Ｐｔ、Ｐｄ、Ｓｃ、Ｃｒ、Ｔａ、Ｃｕから選
ばれた少なくとも１種類の金属を不純物として含有し、
Ｃｕ、Ｎｉ、Ｔｉ、Ｗ、Ａｇ、Ｍｏから選ばれる少なく
とも１種類の金属を基にする金属材料であることを特徴
とする請求項１記載のバリアメタルの形成方法。3. The target is Sn, Ti, Al, M
g, Si, Pt, Pd, Sc, Cr, Ta, Cu containing at least one metal selected as an impurity,
The method for forming a barrier metal according to claim 1, wherein the metal material is a metal material based on at least one metal selected from Cu, Ni, Ti, W, Ag, and Mo.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23040695A JP3362573B2 (en) | 1995-09-07 | 1995-09-07 | Formation method of barrier metal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23040695A JP3362573B2 (en) | 1995-09-07 | 1995-09-07 | Formation method of barrier metal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0974097A true JPH0974097A (en) | 1997-03-18 |
| JP3362573B2 JP3362573B2 (en) | 2003-01-07 |
Family
ID=16907392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23040695A Expired - Lifetime JP3362573B2 (en) | 1995-09-07 | 1995-09-07 | Formation method of barrier metal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3362573B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005041290A1 (en) * | 2003-10-24 | 2005-05-06 | Nikko Materials Co., Ltd. | Nickel alloy sputtering target and nickel alloy thin film |
| CN105870093A (en) * | 2016-05-25 | 2016-08-17 | 武汉光谷创元电子有限公司 | Conducting cylinder, manufacturing method thereof, chip packaging method and flip chip product |
| CN107022747A (en) * | 2017-04-05 | 2017-08-08 | 武汉光谷创元电子有限公司 | Microwave-medium part and its manufacture method |
| US9853005B2 (en) | 2014-07-09 | 2017-12-26 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| WO2021156970A1 (en) * | 2020-02-05 | 2021-08-12 | 石原ケミカル株式会社 | STRUCTURE CONTAINING Sn LAYER OR Sn ALLOY LAYER |
-
1995
- 1995-09-07 JP JP23040695A patent/JP3362573B2/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005041290A1 (en) * | 2003-10-24 | 2005-05-06 | Nikko Materials Co., Ltd. | Nickel alloy sputtering target and nickel alloy thin film |
| US7605481B2 (en) | 2003-10-24 | 2009-10-20 | Nippon Mining & Metals Co., Ltd. | Nickel alloy sputtering target and nickel alloy thin film |
| US9853005B2 (en) | 2014-07-09 | 2017-12-26 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| CN105870093A (en) * | 2016-05-25 | 2016-08-17 | 武汉光谷创元电子有限公司 | Conducting cylinder, manufacturing method thereof, chip packaging method and flip chip product |
| WO2017202037A1 (en) * | 2016-05-25 | 2017-11-30 | 武汉光谷创元电子有限公司 | Conductor post and manufacturing method thereof, chip packaging method, and flip chip product |
| CN105870093B (en) * | 2016-05-25 | 2021-02-02 | 武汉光谷创元电子有限公司 | Conductor pillar, manufacturing method thereof, method for packaging chip and flip chip product |
| CN107022747A (en) * | 2017-04-05 | 2017-08-08 | 武汉光谷创元电子有限公司 | Microwave-medium part and its manufacture method |
| CN107022747B (en) * | 2017-04-05 | 2019-12-31 | 武汉光谷创元电子有限公司 | Microwave dielectric member and method for manufacturing same |
| US11552617B2 (en) | 2017-04-05 | 2023-01-10 | Richview Electronics Co., Ltd. | Microwave dielectric component and manufacturing method thereof |
| WO2021156970A1 (en) * | 2020-02-05 | 2021-08-12 | 石原ケミカル株式会社 | STRUCTURE CONTAINING Sn LAYER OR Sn ALLOY LAYER |
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| JP3362573B2 (en) | 2003-01-07 |
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