CN205984964U - Conducting cylinder and chip flip -chip product - Google Patents
Conducting cylinder and chip flip -chip product Download PDFInfo
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- CN205984964U CN205984964U CN201620482783.6U CN201620482783U CN205984964U CN 205984964 U CN205984964 U CN 205984964U CN 201620482783 U CN201620482783 U CN 201620482783U CN 205984964 U CN205984964 U CN 205984964U
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Abstract
The utility model relates to a conducting cylinder and chip flip -chip product. A conducting cylinder (20) including electrically conductive seeding layer (16) and cylindrical conductor thickening layer (18) that form in electrically conductive seeding layer's top, the electrically conductive seeding layer of sets up on the surface of chip electrode or at the pore wall in the hole in the chip, or at package substrate's circuit on the surface to including ion implantation layer and/or plasma sedimentary deposit.
Description
Technical field
This utility model is related to the chip package field of electronic product, more particularly, to conductor pin and its manufacture method, use
Come the method to encapsulate chip and the flip-chip product being obtained by this method for packing, this conductor pin is applied to core conductor pin
Electrode on piece is electrically connected to base plate for packaging, such as monolayer printed wiring board, lamination multilager base plate or road no central layer etc. of sunkening cord.
Background technology
Along with electronic product towards the trend of high integration, miniaturization and slimming development, need corresponding printed wiring
Plate or IC substrate package are also sent out towards light, thin, short, little trend on the premise of meeting good electrical properties and hot property
Exhibition, this requires electronic devices and components integrated level to improve, encapsulates high density, miniaturization and many pinizations.Based on this demand, except setting
Outside meter and manufacturing technology, IC package manufacturer also develops more advanced packaging to realize High Density Integration constantly, makes
Obtain encapsulating structure and develop into more advanced CSP from the QFP (Quad Flat formula encapsulation technology) of early stage, BGA (welded ball array encapsulation)
(chip size packages), even WLP CSP (encapsulation of silicon wafer level).Flip-chip (flip chip) flip interconnection technique is near
A kind of encapsulation technology of developing over year, has that chip is short with wiring board access path, impedance is low, the loss of signal is little, the signal of telecommunication is posted
The advantages of life phenomenon is few, just progressively replaces longer wire bonding (wire bonding) packaged type of circuit and is applied to many
In high-end electronic product.
Chip node is welded by way of high temperature reflux weldering with circuit plate node by traditional flip interconnection technique using stannum ball
It is connected together.With line density, being continuously increased of CSP chip density, less and less for the spacing between external electrode.
When the design density docking solder joint increases, electric current and heat effect are consequently increased.Due to the impact of stannum ball electron transfer factor,
Product reliability can reduce, and the problems such as easily cause bridge joint between electrode when high temperature reflux welds and lead to short circuit.For
This, progressively adopted now copper post (Cu pillar) to replace stannum ball, become the mainstream technology of flip connection.Estimated copper post skill
Art will develop it is adaptable to below 28/20nm processing procedure towards the direction reducing spacing further, increasing density, and expands to all
Flip-chip products on.Have benefited from the material behavior of copper, copper post connects and has superior electric conductivity, hot property and reliability
Property, and meet ROHS environmental requirement, is widely portable to transceiver, flush bonding processor, power management, baseband chip, special
Integrated circuit and some require thin space, SOC etc. of ROHS standard, low cost and good electrical properties.Mutual using this chip
Even technology can reduce the substrate number of plies used, realizes the reduction (can save about 20% compared with wire bonding) of overall package cost,
And very high electric migration performance and current carrying capacity can be had.
Copper post can be produced on chip, also can be produced on base plate for packaging or printed substrate.Copper post is made on chip
When, due to the wafer area residing for chip generally less (diameter only about 200mm) so that using senior electroplating device and
Liquid medicine, throwing power is strong but cost of manufacture is higher.When base plate for packaging or printed wiring board make copper post, generally using subtracting into
Method, but because need are etched to Copper Foil using etching solution, etching solution is not only downwards but also from side attack copper, thus can go out
Existing side etching phenomenon, leads to gained copper post to be cone.This is unfavorable for the making of more Small Distance copper post, is also unfavorable for signal transmission
Integrity.Recently, have tried to be formed on chip electrode or printed wiring board by electroless copper plating or sputtering method comprise titanium, copper
Metal seed layer, then grow on this metal seed layer cylinder copper post, recycle this copper post to carry out flip-chip.Can
Be, although these existing copper post flip chip technologies can meet closely spaced requirement, in copper post and base plate for packaging circuit or
The metal seed layer adhesion of the junction between copper post and semiconductor chip electrode is weaker, easily crack, and due to
The uneven stress leading to of thermal expansion in encapsulation process and easily cause lead rupture, copper post and base plate for packaging or chip electrode
Peel off, thus leading to electronic product to lose efficacy.
Utility model content
This utility model is made in view of the above problems, it is intended that provide a kind of with chip electrode or envelope
Be there is between dress base plate line conductor pin and its manufacture method, the method being encapsulated chip using this conductor pin compared with high-bond
And by the prepared flip-chip product of this method for packing.
First technical scheme of the present utility model is a kind of method manufacturing conductor pin, and it comprises the following steps：Using target
Material, the circuit surface of the surface to chip electrode or the hole wall or base plate for packaging that are formed at the hole in chip carries out ion note
Enter and/or plasma-deposited process, to form conductive seed layer (step S1)；And form post above conductive seed layer
The conductor thickening layer of shape, this conductor thickening layer and conductive seed layer composition conductor pin (step S2).
Second technical scheme of the present utility model is, in above-mentioned first scheme, carry out after first carrying out ion implanting etc. from
Daughter deposits.
3rd technical scheme of the present utility model is, in above-mentioned first scheme, during ion implanting, the ion of target
Obtain the energy of 1-1000keV, and be injected into the surface of chip electrode or the circuit surface of the hole wall in hole or base plate for packaging
Lower section, formed ion implanted layer as conductive seed layer at least a portion.
4th technical scheme of the present utility model is, in above-mentioned first scheme, in plasma-deposited period, target
Ion obtains the energy of 1-1000eV, and is deposited to the surface of chip electrode or the circuit table of the hole wall in hole or base plate for packaging
The top in face, forms plasma deposited layers as at least a portion of conductive seed layer.
5th technical scheme of the present utility model is, in above-mentioned first scheme, conductive seed layer comprise Ti, Cr, Ni,
One or more of Cu, Ag, Al, Au, V, Zr, Mo, Nb, In, Sn, Tb and the alloy between them, conductor thickening layer bag
One or more of alloy containing Cu, Ag, Al, Au and between them.
6th technical scheme of the present utility model is, in above-mentioned first scheme, conductor pin is in solid or hollow column,
Its one end imbeds the inside of chip or base plate for packaging, and the other end is located at the surface of chip or base plate for packaging.
7th technical scheme of the present utility model is, in any one of the above-mentioned first to the 6th scheme, in step S1
In, first the periphery in chip electrode covers the insulating barrier being provided with hole, then the hole wall of device to hole and the chip electrode being exposed to hole
Surface carries out ion implanting and/or plasma-deposited process, to form conductive seed layer；In step s 2, first in insulating barrier
Upper covering photoresist, forms, by photoetching, the opening connecting with hole in the photoresist, then fills hole and opening with conductive material,
And form conductor pin after removing photoresist and conductive seed layer below.
8th technical scheme of the present utility model is, in any one of the above-mentioned first to the 6th scheme, in step S1
In, first holes drilled through is carried out to chip piece or stacked together two pieces or many chip blocks, covering insulation around through hole
Layer, then carries out ion implanting and/or plasma-deposited process to the hole wall of through hole, runs through chip piece or layer to be formed
Two pieces or the conductive seed layer of many chip blocks stacking；In step s 2, fill through hole with conductive material, and removing absolutely
Form conductor pin after edge layer.
9th technical scheme of the present utility model is, in any one of the above-mentioned first to the 6th scheme, in step S1
In, ion implanting and/or plasma-deposited process are carried out to the surface of base plate for packaging, to form conductive seed layer；In step
In S2, first on base plate for packaging, cover photoresist, the circuit that opening exposes base plate for packaging is formed in the photoresist by photoetching
Surface, then fills opening with conductive material, and forms conductor pin after removing photoresist and conductive seed layer below.
Tenth technical scheme of the present utility model is, in above-mentioned 9th scheme, two pieces or many chip blocks are directly layered in
Together, or it is provided with dielectric isolation layer between each chip.
11st technical scheme of the present utility model is a kind of conductor pin, and it includes conductive seed layer and in conductive seed layer
The conductor thickening layer of column that formed of top, conductive seed layer is arranged on the surface of chip electrode or in being formed at chip
The hole wall in hole or in the circuit surface of base plate for packaging, and include ion implanted layer and/or plasma deposited layers.
12nd technical scheme of the present utility model is, in above-mentioned 11st scheme, ion implanted layer is located at chip electricity
The lower section of the circuit surface of the hole wall in the surface of pole or hole or base plate for packaging, be by chip electrode material or chip substrates or
The line material of base plate for packaging and the doped structure of conductive material composition.
13rd technical scheme of the present utility model is, in above-mentioned 11st scheme, plasma deposited layers are located at core
The top of the circuit surface of the hole wall in the surface of plate electrode or hole or base plate for packaging.
14th technical scheme of the present utility model is, in above-mentioned 11st scheme, conductive seed layer comprise Ti, Cr,
One or more of Ni, Cu, Ag, Al, Au, V, Zr, Mo, Nb, In, Sn, Tb and the alloy between them, conductor thickening layer
Comprise one or more of Cu, Ag, Al, Au and the alloy between them.
15th technical scheme of the present utility model is, in above-mentioned 11st scheme, conductor pin is in solid or hollow
Column, its one end imbeds the inside of chip or base plate for packaging, and the other end is located at the surface of chip or base plate for packaging.
According to this utility model, during ion implanting, the ion of conductive material is forcibly injected into very high speed
The inside of matrix (here is generally referred chip substrates, chip electrode material and base plate for packaging material), and matrix material between
Form stable doped structure, be equivalent to that (here is generally referred chip electrode surface, base plate for packaging surface on the surface of matrix
Hole wall with the hole being opened in chip) large number of foundation pile formed below.Due to there is foundation pile and subsequently prepared leading
Body thickening layer is connected with this foundation pile, thus the conductor pin in the inclusion conductive seed layer being finally obtained and conductor thickening layer and matrix
Between there is very high adhesion, far above the adhesion (being 0.5N/mm to the maximum) obtaining by magnetron sputtering in prior art.
Additionally, in plasma-deposited period, the ion of conductive material flies to matrix with higher speed in the presence of accelerating field
And be deposited on above, form plasma deposited layers.There is between plasma deposited layers and matrix material larger adhesion
(more than 0.5N/mm) is so that the conductor pin being finally obtained is not easy to come off from matrix or peel off.On the other hand, note for ion
Enter, with plasma-deposited conductive material ion, generally there is nano level size, be distributed more equal during injection or deposition
Even, and little to the incident angle difference of matrix surface.It is accordingly possible to ensure the conductive seed layer of gained have good equal
, it is not easy to pin hole or seminess, this is conducive to improving the structural intergrity of conductor pin, rigidity and leads for evenness and compactness
Electrically.
16th technical scheme of the present utility model is a kind of method encapsulating chip using conductor pin, and it includes following
Step：First conductor pin is formed on chip, and/or the second conductor pin (step is formed on the circuit surface of base plate for packaging
Rapid S1)；Between the first conductor pin and the circuit surface of base plate for packaging, or the surface of the second conductor pin and chip electrode it
Between, or it is electrically connected (step S2) between the first conductor pin and the second conductor pin, and wherein, the first conductor pin and/or
Two conductor pins be by any one method in the above-mentioned first to the tenth scheme be obtained conductor pin or be the above-mentioned 11st to
Any one conductor pin in 15th scheme.
17th technical scheme of the present utility model is that, in above-mentioned 16th scheme, chip includes stacked together
Two pieces or many chip blocks, and the first conductor pin runs through two pieces or many chip blocks.
18th technical scheme of the present utility model is, in above-mentioned 16th scheme, fetches enforcement electricity by Reflow Soldering
Connect.
19th technical scheme of the present utility model is, in above-mentioned 16th scheme, the circuit table bread of base plate for packaging
Include pad for welding the first conductor pin, or the surface of chip electrode includes pad for welding the second conductor pin.
20th technical scheme of the present utility model be a kind of flip-chip product, it include base plate for packaging, chip and
The conductor pin electrically connecting between base plate for packaging and chip and by them, conductor pin includes conductive seed layer and in conductive seed layer
The conductor thickening layer of the column that the top of layer is formed, conductive seed layer is arranged on the surface of chip electrode or is being formed at chip
In the hole wall in hole or in the circuit surface of base plate for packaging, and include ion implanted layer and/or plasma-deposited
Layer.
21st technical scheme of the present utility model is, in above-mentioned 20th scheme, ion implanted layer is located at chip
The lower section of the circuit surface of the hole wall in the surface of electrode or hole or base plate for packaging, be by chip electrode material or chip substrates or
The line material of person's base plate for packaging and the doped structure of conductive material composition.
22nd technical scheme of the present utility model is that, in above-mentioned 20th scheme, plasma deposited layers are located at
The top of the circuit surface of the hole wall in the surface of chip electrode or hole or base plate for packaging.
23rd technical scheme of the present utility model is, in above-mentioned 20th scheme, conductor pin is in solid or hollow
Column, its one end imbeds the inside of chip or base plate for packaging, and the other end is located at the surface of chip or base plate for packaging.
24th technical scheme of the present utility model is, in above-mentioned 20th scheme, the conductive seed layer of conductor pin
Run through chip piece or stacked together two pieces or many chip blocks.
According to this utility model, in flip-chip product, the conductor pin that chip is electrically connected to base plate for packaging has bag
Include the conductive seed layer of ion implanted layer and/or plasma deposited layers.As it was noted above, having between this conductor pin and matrix
There is very high adhesion, thus this flip-chip product also will have very high stability and reliability it is not easy to lose efficacy
Or fault.Further, since ion implanted layer and/or plasma deposited layers have the good uniformity and compactness, no
Pin hole or seminess easily occur, conductor pin also therefore has good structural intergrity, rigidity and electric conductivity, thus this core
Piece upside-down mounting product also will have excellent robustness, electric conductivity and hot property, can be widely used in various electronic products.
Brief description
After reading the following detailed description referring to the drawings, those skilled in the art will be better understood this utility model
These and other feature, aspect and advantage.For the sake of clarity, accompanying drawing is not drawn necessarily to scale, but some of which
Detail partly may be exaggerated to show.In all of the figs, identical reference number represents same or analogous part,
Wherein：
Fig. 1 is the flow chart being indicated generally by according to the method manufacturing conductor pin of the present utility model.
Fig. 2 is the flow chart of the method representing the manufacture conductor pin according to first embodiment of the present utility model；
Fig. 3 (a)-(e) is to be shown in illustrate with the corresponding structural profile of each step of method shown in Fig. 2 when manufacturing conductor pin
Figure；
Fig. 4 is the generalized section of another conductor pin that the method shown in Fig. 2 that is shown with is obtained；
Fig. 5 (a)-(e) is the generalized section illustrating according to various conductive seed layer of the present utility model；
Fig. 6 is the flow chart of the method representing the manufacture conductor pin according to second embodiment of the present utility model；
Fig. 7 (a)-(d) is to be shown in illustrate with the corresponding structural profile of each step of method shown in Fig. 6 when manufacturing conductor pin
Figure；
Fig. 8 is the flow chart of the method representing the manufacture conductor pin according to 3rd embodiment of the present utility model；
Fig. 9 (a)-(d) is to be shown in illustrate with the corresponding structural profile of each step of method shown in Fig. 8 when manufacturing conductor pin
Figure；
Figure 10 is the flow chart representing according to the method encapsulating chip using conductor pin of the present utility model；
Figure 11 (a)-(e) is to be shown with the structural profile signal that conductor pin encapsulates the flip-chip products after chip
Figure.
Reference number：
10 chips
12 chip electrodes
The surface of 14 chip electrodes
16 conductive seed layer
161 ion implanted layers
162 plasma deposited layers
18 conductor thickening layers
20 conductor pins
22 matrixes
24 matrix surfaces
26 insulating barriers
28 holes
30 photoresists
32 openings
34 dielectric isolation layers
36 through holes
The hole wall of 38 through holes
40 base plate for packaging
The surface of 42 base plate for packaging
The circuit surface of 44 base plate for packaging.
Specific embodiment
Hereinafter, with reference to the accompanying drawings, describe embodiment of the present utility model in detail.Those skilled in the art should manage
Solution, these descriptions only list exemplary embodiment of the present utility model, and are in no way intended to limit protection of the present utility model
Scope.For example, the element described in an accompanying drawing of the present utility model or embodiment or feature can with one or more its
Other elements shown in its accompanying drawing or embodiment or feature combine.Additionally, for the ease of describing the position between each material layer
Put relation, used herein space relative terms, such as " top " and " lower section " and " interior " and " outward " etc., these arts
Language is all for the surface of chip or base plate for packaging or the hole wall in hole.If A layer material is with respect to B layer material position
Then it is assumed that A layer material is located at top or the position of B layer material on the direction in the outside towards chip, base plate for packaging or hole wall
Outside it, vice versa.
Fig. 1 is the flow chart being indicated generally by according to the method manufacturing conductor pin of the present utility model, and this conductor pin is suitable for
In the electrode on chip is electrically connected to base plate for packaging, such as monolayer printed wiring board, lamination multilager base plate or sunken cord road no
Central layer etc..Specifically, comprised the following steps according to the method manufacturing conductor pin of the present utility model：Using target, to chip
The circuit surface of the surface of electrode or the hole wall or base plate for packaging that are formed at the hole in chip carries out ion implanting and/or waits
Plasma deposition is processed, to form conductive seed layer (step S1)；And, the pillared conductor of shape above conductive seed layer
Thickening layer, this conductor thickening layer and conductive seed layer composition conductor pin (step S2).In other words, conductor pin of the present utility model
May be formed on the hole wall in the hole being formed on the surface of chip electrode, in chip (especially chip electrode) or in encapsulation
In the circuit surface of substrate.Wherein, the circuit surface of base plate for packaging refers to the surface of the line pattern of formation on base plate for packaging.
Conductor pin and its manufacture method of these three forms hereinafter will be described in detail.It should be appreciated that in the following description, embodiment
Sequence number be merely convenient of description, and do not represent the quality of embodiment.Description to each embodiment is given priority to, certain enforcement
The part describing in detail is not had to may refer to the associated description of other embodiments in example.
<First embodiment>
Fig. 2 is the flow chart of the method representing the manufacture conductor pin according to first embodiment of the present utility model.The method
It is related to form conductor pin on the surface of chip electrode, and comprise the following steps：Cover in the periphery of chip electrode and be provided with hole
Insulating barrier (step S11)；The surface of the hole wall of device to hole and the chip electrode being exposed to hole carries out ion implanting and/or plasma
Body deposition processes, to form conductive seed layer (step S12)；Cover photoresist on the insulating layer, by photoetching in the photoresist
Form the opening (step S21) connecting with hole；Fill hole and opening (step S22) with conductive material；And, remove photoresist and
Conductive seed layer below, to form conductor pin (step S23).Wherein, step S11 and S12 correspond to the step shown in Fig. 1
S1, and step S21, S22 and S23 then correspond to step S2 shown in Fig. 1.Additionally, Fig. 3 (a)-(e) is to be shown in manufacture conductor
During post, each step corresponding structural profile schematic diagram with method shown in Fig. 2, will be described in detail below.
In step s 11, as shown in Fig. 3 (a), the periphery in the electrode 12 of chip 10 covers the insulation being provided with hole 28 first
Layer 26.Insulating barrier 26 may include the materials such as polyimides (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), and is formed
It is various that hole 28 in insulating barrier 26 can have cylinder, rectangle, square, triangle, inverted trapezoidal etc. as desired
Section shape.Further, it is also possible to first cover last layer passivation layer in the periphery of chip electrode, then cover absolutely on this passivation layer
Edge layer simultaneously opens up hole, and wherein passivation layer may include the oxide materials such as silicon oxide or silicon nitride.Easy to understand, although in Fig. 3 (a)
Shown in electrode 12 be embedded in chip 10 so that the outer surface of both flushes, but this be used for the purpose of convenient
Diagram, actual Top electrode 12 can also project from the surface of chip 10, becomes the structure of overshooting shape.
In step s 12, the hole wall of first device to hole 28 and the surface of the chip electrode 12 being exposed to hole 28 ion note can be carried out
Enter to process, to form ion implanted layer 161, then carry out plasma-deposited process, to form plasma deposited layers 162,
This plasma deposited layers 162 forms conductive seed layer 16 together with ion implanted layer 161.As shown in Fig. 3 (b), ion implanting
Layer 161 is located at surface 14 lower section of chip electrode 12, below the hole wall in hole 28 and insulating barrier 26 lower face, and plasma
Sedimentary 162 is then correspondingly situated at the top of ion implanted layer 161, and ion implanted layer 161 is together with plasma deposited layers 162
Composition conductive seed layer.Except carry out after first carrying out ion implanting plasma-deposited in addition to, when forming conductive seed layer, also
Only by ion implanting, conductive material can be injected into the lower section of chip electrode surface, hole wall and surface of insulating layer, to be formed
Ion implanted layer is as conductive seed layer, or only by plasma-deposited, conductive material can be deposited to chip electrode table
The top of face, hole wall and surface of insulating layer, to form plasma deposited layers as conductive seed layer.Alternatively, can also be first
Carry out plasma-deposited after carry out ion implanting process, thus above chip electrode surface, hole wall and surface of insulating layer
Form plasma deposited layers, and the lower face in this plasma deposited layers forms ion implanted layer.Additionally, in various shapes
Become in the method for conductive seed layer, all can carry out one or many ion implanting and/or plasma-deposited process, to be formed
One or more ion implanted layers and/or plasma deposited layers.
Fig. 5 (a)-(e) is the generalized section illustrating according to various conductive seed layer of the present utility model, wherein, matrix
22 expressions carry out ion implanting and/or plasma-deposited object in the above, it may include chip electricity described below
Pole material, chip substrates, base plate for packaging material, base plate for packaging line material, insulating layer material etc..In this embodiment, base
Body 22 generally represents chip electrode material and insulating layer material, and the surface 24 of matrix then generally represents the table of chip electrode
Face, the surface of insulating barrier and the hole wall being formed at the hole in insulating barrier.In Fig. 5 (a), conductive seed layer only includes being formed
Ion implanted layer 161 in surface 24 lower section of matrix 22.In Fig. 5 (b), conductive seed layer only includes depositing to matrix 22
Surface 24 top plasma deposited layers 162.In Fig. 5 (c), conductive seed layer both includes being formed at the surface of matrix 22
The ion implanted layer 161 of 24 lower sections, includes being attached to the plasma deposited layers 162 of this ion implanted layer 161 top again.In figure
In 5 (d), conductive seed layer includes being located immediately at the plasma deposited layers 162 of surface 24 top of matrix 22 and is injected into
The ion implanted layer 161 of the lower face of this plasma deposited layers 162, now the inner surface of ion implanted layer 161 will be located at
In plasma deposited layers 162, and outer surface is then flushed with the outer surface of plasma deposited layers 162.Fig. 5 (e) represents successively
Ion implanting, the cross-section structure of plasma-deposited obtained conductive seed layer are twice carried out, wherein in conductive seed layer
Ion implanted layer 161 and plasma deposited layers 162 be divided into two-layer.Second ion implanted layer will be deep into the first implanted layer
Inside, and the second plasma deposited layers are then attached to the top of the first sedimentary.Easy to understand, shown in Fig. 5 (a)-(e)
Structure is only the graphical representation of exemplary of conductive seed layer, rather than the enumerating of exhaustive.For example, the conductive seed layer of each in figure
All can have the ion implanted layer being divided into two-layer or more layers and/or plasma deposited layers it is also possible to stacked on top of each other together
And become complicated multi-ply construction, such as ion implanted layer/plasma deposited layers/ion implanted layer/plasma deposited layers
Construction, etc..
Ion implanting can be carried out by the following method：Conductive material is used as target, under vacuum conditions, by electricity
Arc effect makes the conductive material in target ionize and produce ion, then makes this acceleration of ions obtain certain energy under the electric field
Amount.The conductive material ion of high energy then directly impinges the surface of chip electrode, the hole wall in hole and insulation with higher speed
On the surface of layer, and it is injected into certain depth below surface or hole wall.In the conductive material ion being injected and chip
Relatively stable chemical bond, such as ionic bond or covalent bond is defined, the two is common between electrode and the material molecule of insulating barrier
Constitute doped structure.The outer surface of this doped structure (that is, ion implanted layer) and the surface of chip electrode, the hole wall in hole or exhausted
The surface of edge layer flushes, and its inner surface is then deep into the inside of chip electrode and insulating barrier, i.e. positioned at the table of chip electrode
The lower face in face, the hole wall in hole and insulating barrier.In ion implantation process, can be by controlling various parameters (such as electric field electricity
Pressure, electric current, vacuum, ion implantation dosage etc.) and easily adjust the depth of ion implanting and matrix (herein means Dai Xin
Plate electrode material and insulating layer material) adhesion and conductive seed layer between.For example, the Implantation Energy of ion can be adjusted to
1-1000keV (such as 5,10,50,100,200,300,400,500,600,700,800,900keV etc.), injection depth can quilt
Be adjusted to 1-500nm (such as 5,10,50,100,200,300,400nm etc.).
Plasma-deposited to be carried out by the way of similar to ion implanting, only apply relatively in the course of the work
Low accelerating potential.That is, equally it is used conductive material as target, under vacuum conditions, made in target by arcing
Conductive material ionizes and produces ion, then orders about this acceleration of ions under the electric field and obtains certain energy and deposit to chip
On the surface on the surface of electrode, the hole wall in hole and insulating barrier, constitute plasma deposited layers.In plasma-deposited period, can
With by adjust electric field accelerating potential and make conductive material ion obtain 1-1000eV (such as 5,10,50,100,200,
300th, 400,500,600,700,800,900eV etc.) energy, and can be by controlling the ion deposition time, passing through electric current
Deng and obtain thickness be 10-1000nm (such as 50,100,200,300,400,500,600,700,800,900nm etc.) etc. from
Daughter sedimentary.
Ion implanting and/or plasma-deposited when, target used is conductive material, can be metal targets, oxygen
Compound target, sulfide target (such as CdS, ZnS etc.), nitride target (such as TiN etc.), carbide target (such as WC,
VC、Cr4C3One or more of Deng).Metal targets for example may include Ti, Cr, Ni, Cu, Ag, Al, Au, V, Zr, Mo, Nb,
One or more of In, Sn, Tb and the alloy between them, and oxide target material for example may include In2O3、SnO2、
TiO2、WO3、MoO3And Ga2O3One or more of.Preferably, target material used easily and chip electrode material and
Form larger adhesion between insulating layer material, for example, can adopt and chip electrode identical conductive material.Easy to understand,
The target that ion implanting, plasma-deposited period adopt can be identical target or different targets, thus phase
Identical or different conductive material components should be comprised in ground in the conductive seed layer finally giving.In addition it is also possible to one after the other
Using different targets carry out ion implanting or carry out plasma-deposited so that in the final conductive seed layer obtaining,
Ion implanted layer or plasma deposited layers are divided into one or more layers.This utility model people finds, if first entered to matrix
Carry out plasma-deposited (sedimentary energy is 1-1000eV), such shape after row ion implanting (Implantation Energy is 1-1000KeV)
Adhesion between the conductive seed layer becoming and matrix will greatly increase, thus is preferred.In conduction copper column to be formed
In the case of, it is preferred to use Ti, Cr, Ni or Cr-Ni alloy is as the target forming conductive seed layer.
During ion implanting, the ion of conductive material is forcibly injected into the inside of matrix with very high speed, with base
Form stable doped structure between body material, be equivalent to the lower face in matrix and define large number of foundation pile.Due to
The conductor thickening layer that there is foundation pile and be subsequently obtained is connected with this foundation pile, thus in the inclusion conductive seed layer being finally obtained and leads
There is very high adhesion, far above obtain by magnetron sputtering in prior art between the conductor pin of body thickening layer and matrix
Adhesion (is 0.5N/mm to the maximum).In plasma-deposited period, the ion of conductive material is in the presence of accelerating field with relatively
High speed flies to matrix and is deposited on above, forms plasma deposited layers.Between plasma deposited layers and matrix material
There is larger adhesion (more than 0.5N/mm) so that the conductor pin being finally obtained is not easy to come off from matrix or peel off.Another
Aspect, generally has nano level size for ion implanting and plasma-deposited conductive material ion, in injection or heavy
During long-pending, distribution is more uniform, and little to the incident angle difference of matrix surface.It is accordingly possible to ensure the conductive seed of gained
Crystal layer has the good uniformity and compactness it is not easy to pin hole or seminess, and this is conducive to improving the knot of conductor pin
Structure integrity, rigidity and electric conductivity.
After defining conductive seed layer, above insulating barrier, then cover photoresist, by normal in prior art
The techniques such as the photoetching seen form opening (step S21) in this photoresist.Opening in photoresist be formed at insulating barrier before
In hole be connected so that expose chip electrode surface, more specifically be expose be formed at leading on chip electrode surface
Electric inculating crystal layer.As shown in Fig. 3 (c), cover photoresist 30 above insulating barrier 26, and be formed with this photoresist 30
The opening 32 being connected with the hole 28 being formed in insulating barrier 26 such as Fig. 3 (b) Suo Shi.Easy to understand, although shown in Fig. 3 (c)
The inwall of opening 32 is mutually continuous with the inwall of the conductive seed layer being formed on the hole wall in the hole 28 in insulating barrier 26 and aligns,
But this utility model is not limited to this.For example, the hole that the internal diameter of opening 32 can also be wider than hole 28 or be formed at hole 28
The internal diameter of the conductive seed layer on wall.
Then, in step S22, hole and opening are filled with conductive material, to form the post being located above conductive seed layer
Shape conductor thickening layer.Conductor thickening layer can pass through one of method such as plating, chemical plating, vacuum evaporation coating, sputtering or many
Plant processing mode, in the alloy using such as Al, Mn, Fe, Ti, Cr, Co, Ni, Cu, Ag, Au, V, Zr, Mo, Nb and between them
One or more being formed.Cu, Ag, Au and Al are widely used in conductive pole due to having good electric conductivity.Cause
For plating speed is fast, low cost, and the scope of electrodepositable material is widely, be particularly suited for Cu, Ni, Sn, Ag and
Alloy between them etc., thus galvanoplastic are usually used to prepare conductor thickening layer.For some conductive materials (particularly
Al, Cu, Ag and its alloy) for, the speed of sputtering can reach 100nm/min, thus can be using sputtering method in conductive seed
Rapidly plating conductor thickening layer on crystal layer.Due to having passed through ion implanting before and/or plasma-deposited having defined all
Even, fine and close conductive seed layer, so be easy to form uniform, fine and close leading in conductive seed layer by above-mentioned various methods
Body thickening layer, and then form conductor pin together with conductive seed layer.As shown in Fig. 3 (d), by electro-plating method in hole 28 and opening
It is filled with conductor thickening layer 18 in 32.When being electroplated using copper and being formed conductor thickening layer 18, just obtain conventional copper post.
Finally, in step S23, photoresist and conductive seed layer below are removed, thus forming conductor pin.As Fig. 3
E, shown in (), the photoresist 30 around conductor thickening layer 18 is removed, the conductive seed layer of photoresist 30 lower section has also passed through erosion
Carve etc. mode and be removed, obtained two conductor pins 20 electrically separated from each other.Each conductor pin 20 all includes being arranged on chip
Conductive seed layer 16 on electrode surface 12 and the conductor thickening layer 18 of the column being formed above this conductive seed layer 16.By
In the presence of ion implanted layer 161, one end of conductor pin 20 is embedded in the inside of chip 10 (specifically chip electrode 12),
The other end is then located at the surface of chip 10.Although showing two separate conductor pins 20 in figure, it will be readily appreciated that
Number corresponding to chip electrode 12 and as needed, the quantity of gained conductor pin 20 can be only one or three
Individual or more than three.In addition it is readily appreciated that, although the conductor pin shown in Fig. 3 (e) 20 is solid column, this practicality is newly
Type is not limited to this, and this conductor pin 20 can also be hollow.
Fig. 4 is the generalized section of another conductor pin that the method shown in Fig. 2 that is shown with is obtained.In this example, chip
Electrode 12 projects from the surface of chip 10, becomes the structure of overshooting shape.Correspondingly, insulating barrier 26 covers the periphery of chip electrode 12
And the part not forming electrode on chip 10 surface, and conductive seed layer 16 is then formed on the surface of chip electrode 12 and opens
On the inwall in the hole 28 of insulating barrier 26.
<Second embodiment>
Fig. 6 is the flow chart of the method representing the manufacture conductor pin according to second embodiment of the present utility model.The method
It is related to form conductor pin on the hole wall in the hole in being formed at chip, comprise the following steps：To chip piece or be layered in one
Rise two pieces or many chip blocks carry out holes drilled through, covering insulating barrier (step S11) around through hole；The hole wall of through hole is carried out
Ion implanting and/or plasma-deposited process, run through chip piece or stacked together two pieces or polylith core to be formed
The conductive seed layer (step S12) of piece；Fill through hole (step S21) with conductive material；And, remove insulating barrier to form conductor
Post (step S22).Wherein, step S11 and S12 correspond to step S1 shown in Fig. 1, and step S21 and S22 then correspond to Fig. 1
Shown step S2.Additionally, Fig. 7 (a)-(d) is corresponding with each step of method shown in Fig. 6 when being shown in manufacture conductor pin knot
Structure generalized section, will be described in detail below.
In step s 11, as shown in Fig. 7 (a), first to the chip piece 10 including chip electrode 12 or be layered in one
Rise two pieces or many chip blocks 10 carry out holes drilled through 36, then covering insulating barrier 26 around through hole 36.This through hole 36 is permissible
Run through chip electrode 12 on each chip 10 it is also possible to the only electrode on some chips or certain specific core therethrough
Some electrodes on piece.For example, through hole 36 can only run through the left electrodes in the upper strata chip 10 shown in Fig. 7 (a), and not
Run through right electrodes.As described in the first embodiment, the insulating barrier 26 that here adopts may also comprise polyimides (PI), polyphenyl simultaneously
The materials such as azoles (PBO), benzocyclobutene (BCB).When using stacked together two pieces or many chip blocks, this two pieces or many
Chip block can be directly stacked upon together it is also possible between each chip, dielectric isolation layer is placed in intervention as shown in Fig. 7 (a)
34.Dielectric isolation layer 34 is typically using common prepreg, it is possible to use PP, PI, PTO, PC, PSU, PES, PPS,
The organic polymer thin film such as PS, PE, PEI, PTFE, PEEK, PA, PET, PEN, LCP, PPA.In addition although the embodiment party of through hole
Formula is more universal in the art, but this utility model is not limited to this.It is true that it is also possible to right in addition to through hole
Chip piece or stacked together two pieces or many chip blocks drilling blind hole, as long as this blind hole can run through the phase on each chip
Answer chip electrode.In boring, can be using machine drilling, punching, laser boring, plasma etching and reactive ion
Etching etc., wherein laser boring again can be using iraser punching, YAG laser boring and ultraviolet laser drillings, can be on base material
Form the micropore that aperture reaches 2-5 micron.The section shape in hole can be the various shape such as circle, rectangle, trapezoidal shape,
It is usually formed the hole that longitudinal profile is upside-down trapezoid in laser drill.Form conductive seed layer after drilling and on hole wall
Before, glue residue removal process can be carried out with using plasma cleaning or chemical corrosion method, residual during holing to remove
Stay resin or cutting fragment on hole wall etc., it is to avoid interlayer interconnection and reliability go wrong.
In step s 12, ion implanting and/or plasma-deposited process are carried out to the hole wall of through hole, run through with being formed
Chip piece or stacked together two pieces or the conductive seed layer of many chip blocks.Now, on the hole wall of through hole and insulation
Conductive seed layer including ion implanted layer and/or plasma deposited layers is defined on the surface of layer.As it was previously stated, this conduction
The cross-section structure of inculating crystal layer can be Fig. 5 (a) any one shown in 5 (e), and matrix 22 therein represents in this embodiment
Chip electrode material or chip substrates and cover insulating barrier around through hole, and the surface of matrix 22 then represents and is formed at
The hole wall of through hole 36 in chip and the surface of insulating barrier.For example, the conductive seed layer being formed in step s 12 can be only
The ion implanted layer only including being injected into the lower face of matrix or the surface that deposits to matrix plasma-deposited
Layer, or include the plasma deposited layers above matrix surface and be injected into the ion within plasma deposited layers
Implanted layer.Wherein, each ion implanted layer, plasma deposited layers can be divided into two-layer or more layers again.Shown in Fig. 7 (b)
In example, conductive seed layer include being formed at the hole wall 38 of through hole 36 and the ion implanted layer 161 of lower face of insulating barrier 26,
And deposit to the plasma deposited layers 162 of the top of this ion implanted layer 161.Ion implanting and plasma-deposited reality
Applying method as it was noted above, can occur in the conductive seed layer and matrix material between with very big adhesion, this conductive seed
Crystal layer has the good uniformity and compactness it is not easy to pin hole or seminess.
After defining conductive seed layer, then in the step s 21, fill the through hole in chip with conductive material, with
Form the cylindrical conductor thickening layer being located above conductive seed layer.As it was noted above, can be steamed by plating, chemical plating, vacuum
Send out one or more of the methods such as plating, sputtering processing mode to form conductor thickening layer.In example shown in Fig. 7 (c), lead to
Cross electro-plating method and be filled with conductor thickening layer 18 in the through hole 36 being formed at chip 10.Although the conductor shown in Fig. 7 (c) thickeies
Layer 18 is solid column, it will be readily appreciated that this conductor thickening layer 18 can also not exclusively fill through hole 36, but only exists
On the inwall of through hole 36, there is certain thickness and become the column of hollow.In addition although the conductor thickening layer shown in Fig. 7 (c)
18 are only formed in through hole 36 and are flushed with the outer surface of the conductive seed layer being formed on insulating barrier 26 surface, but this
Utility model is not limited to this.For example, it is also possible to form conductor in the outside of through hole 36 and above insulating barrier 26 thicken
Layer 18.
Subsequently, in step S22, remove insulating barrier to form conductor pin.As shown in Fig. 7 (d), insulating barrier 26 and its top
Conductive seed layer be all removed, obtained two conductor pins 20 electrically separated from each other.Each conductor pin 20 all includes arranging
Conductive seed layer 16 on the hole wall in the hole in being formed at chip 10 and the column being formed above this conductive seed layer 16
Conductor thickening layer 18.The two ends of each conductor pin 20 all from the surface of chip 10 outwardly, are subsequently electrically connected to encapsulate to facilitate
Substrate.Certainly, in the case of forming blind hole, conductor pin 20 is just only in one end from the surface of chip 10 outwardly.
Although showing two separate conductor pins 20 in figure, it will be readily appreciated that corresponding to chip electrode 12 number and according to
Need it is also possible to prepare the conductor pin 20 of only one or three or more than three.Removing insulating barrier to form conductor pin
When, it is possible to use the suitable stripper such as organic solvent or alkali liquor, to dissolve insulating barrier, removes the conductive seed layer above it simultaneously
Layer.In addition it is also possible to as with the first embodiment, first above insulating barrier 26, cover photoresist, exposed by photoetching
Do not need to be formed the part (that is, being formed at a part of conductive seed layer of insulating barrier 26 top) of the conductive seed layer of conductor pin,
Then this partially electronically conductive inculating crystal layer is removed by fast-etching；Afterwards, can be with stripping insulation layer 26 it is also possible to retain insulating barrier
26 to provide insulation protection to the chip electrode 12 on chip 10.
<3rd embodiment>
Fig. 8 is the flow chart of the method representing the manufacture conductor pin according to 3rd embodiment of the present utility model.The method
It is related to form conductor pin in the circuit surface of base plate for packaging, and comprise the following steps：The surface of base plate for packaging is carried out from
Son injection and/or plasma-deposited process, to form conductive seed layer (step S1)；Base plate for packaging covers photoresist,
The circuit surface (step S21) that opening exposes base plate for packaging is formed in the photoresist by photoetching；Opened with conductive material filling
Mouth (step S22)；Remove photoresist and conductive seed layer below, to form conductor pin (step S23).Wherein, step
S21, S22 and S23 correspond to step S2 shown in Fig. 1.Additionally, Fig. 9 (a)-(d) is when being shown in manufacture conductor pin and Fig. 8 institute
Show each step corresponding structural profile schematic diagram of method.The base plate for packaging using in this embodiment can be monolayer track
Road plate or the lamination multilager base plate with multilayer line pattern or road no central layer of sunkening cord.In order to make it easy to understand,
Hereinafter only illustrate taking monolayer printed substrate as a example.Additionally, the base material preparing base plate for packaging may include BT (double maleoyl
Imines triazine) organic resin such as resin, epoxy resin, cyanate ester resin, polyphenylene oxide resin, their modified resin or its
Various combinations.
In step sl, as shown in Fig. 9 (a), one after the other the surface 42 of base plate for packaging 40 is carried out ion implanting and wait from
Daughter deposition processes, to form the conductive seed layer including ion implanted layer 161 and plasma deposited layers 162.Wherein, ion
Implanted layer 161 is located at below the surface 42 of base plate for packaging 40, and its outer surface is flushed with the surface 42 of base plate for packaging 40.Plasma
Sedimentary 162 be then attached to ion implanted layer 161 top and be located at base plate for packaging 40 surface 42 above, its inner surface with
The surface 42 of base plate for packaging 40 flushes.Although showing in Fig. 9 (a) including ion implanted layer 161 and plasma deposited layers
Conductive seed layer both 162, it will be readily appreciated that the cross-section structure of this conductive seed layer can also be Fig. 5 as mentioned before
A () any one shown in 5 (e), matrix 22 therein represents base plate for packaging material and base plate for packaging in this embodiment
Line material (that is, constitutes the material of line pattern).For example, conductive seed layer can only include being injected under the surface of matrix
The ion implanted layer of side or deposit to matrix surface plasma deposited layers, or include positioned at matrix surface
Top plasma deposited layers and be injected into the ion implanted layer within plasma deposited layers.Wherein, each ion note
Enter layer, plasma deposited layers and can be divided into two-layer or more layers again.Ion implanting and plasma-deposited implementation
As it was noted above, can occur in the conductive seed layer and matrix material between with very big adhesion, this conductive seed layer has
There are the good uniformity and compactness it is not easy to pin hole or seminess occur.
Easy to understand although in the example shown in Fig. 9 (a), directly defining conduction on the surface 42 of base plate for packaging
Inculating crystal layer, but can also be similar to that Fig. 3 (a) to 3 (b) like that, first covers one layer around the circuit surface 44 of base plate for packaging
Be provided with hole to expose the insulating barrier of this circuit surface, then this circuit surface and insulating barrier are carried out simultaneously ion implanting and/or
Plasma-deposited process, to form the conductive seed layer illustrating similar to Fig. 3 (b).In this case, it is possible to as first is real
Apply example and retain insulating barrier like that, to provide insulation protection to the line pattern on base plate for packaging.In addition although in this embodiment
The base plate for packaging 40 using is line pattern to be imbedded substrate therein but it is also possible to use common line pattern from substrate table
The outstanding substrate in face.In this case it is preferably to be formed to the scheme using insulating barrier 3 (b) Suo Shi using such as Fig. 3 (a)
Conductive seed layer.
Hereafter, above conductive seed layer cover photoresist, by techniques such as conventional photoetching in this photoresist shape
Becoming opening (step S21), to expose the circuit surface of base plate for packaging, being more specifically to expose to be formed in this circuit surface
The conductive seed layer of side.As shown in Fig. 9 (b), cover photoresist 30 above conductive seed layer, this photoresist 30 is online
The surface of road surfaces 44 defines opening 32.
Then, in step S22, fill the opening in photoresist with conductive material, be located in conductive seed layer with being formed
The cylindrical conductor thickening layer of side.As it was noted above, can be by the method such as plating, chemical plating, vacuum evaporation coating, sputtering
Kind or multiple processing mode forming conductor thickening layer.As shown in Fig. 9 (c), photoresist 30 is being opened in by electro-plating method
It is filled with conductor thickening layer 18 in opening 32.This conductor thickening layer 18 can show solid column as Fig. 9 (c) it is also possible to
Only on the inwall of opening 32, there is certain thickness and become the column of hollow, such as when electroplating time is shorter.Though additionally,
So the conductor thickening layer 18 shown in Fig. 9 (c) is located in opening 32 and is less than the outer surface of photoresist 30, it will be readily appreciated that
This conductor thickening layer 18 can also be flushed with the outer surface of photoresist 30 or outstanding from the outer surface of photoresist 30.
Finally, in step S23, photoresist and conductive seed layer below are removed, thus forming conductor pin.As Fig. 9
D, shown in (), the photoresist 30 around conductor thickening layer 18 is removed, the conductive seed layer of this photoresist 30 lower section has also been led to
The modes such as overetch and be removed, obtained two conductor pins 20 electrically separated from each other.Due in this embodiment directly in envelope
Conductive seed layer is defined on the surface 42 of dress substrate 40, thus a part of material of the material of base plate for packaging 40 and its circuit surface
Material also can be etched, and the integral thickness of base plate for packaging 40 can be led to reduce.Each of two conductor pins 20 all include setting
Put the cylindrical conductor being formed in the conductive seed layer 16 in the circuit surface of base plate for packaging and above this conductive seed layer 16
Thickening layer 18.Due to the presence of ion implanted layer 161, one end of conductor pin 20 is embedded in base plate for packaging 40 and (specifically seals
Dress substrate line pattern) inside, the other end then be located at base plate for packaging 40 surface.Although showing two in figure
Separate conductor pin 20, it will be readily appreciated that corresponding to the line pattern on base plate for packaging surface and as needed, can prepare
The conductor pin 20 that only one or three are even more than three.Although in addition, conductor pin 20 be shown as in Fig. 9 (d) solid
Column but it is also possible to be hollow column.
Described above is according to the various methods manufacturing conductor pin of the present utility model.Below, description is used this conductor
Post come to encapsulate chip method and by this method for packing be obtained flip-chip product.Figure 10 is to represent according to this practicality
The flow chart of the new method encapsulating chip using conductor pin, Figure 11 (a)-(e) is to be shown with conductor pin to encapsulate core
The structural profile schematic diagram of the flip-chip products after piece.
With reference to Figure 10, comprised the following steps according to the method encapsulating chip using conductor pin of the present utility model：In core
First conductor pin is formed on piece, and/or the second conductor pin (step S1) is formed on the circuit surface of base plate for packaging；?
Between one conductor pin and the circuit surface of base plate for packaging, or between the second conductor pin and the surface of chip electrode, or
It is electrically connected (step S2) between first conductor pin and the second conductor pin.Wherein, the first conductor pin and/or the second conductor pin can
To be any conductor pin as described previously.That is, the first conductor pin can be in core as shown in Fig. 3 (e)
The conductor pin that formed on the surface of plate electrode or be to be formed on the hole wall in the hole in being opened in chip as shown in Fig. 7 (d)
, the conductor pin running through one or more chip, and the second conductor pin can be the line in base plate for packaging as shown in Fig. 9 (d)
The conductor pin being formed on road surfaces.In the case of using two conductor pins, one of conductor pin can be made to be according to this reality
With new conductor pin, and another conductor pin is conductor pin of the prior art.Additionally, electrical connection can be using in this area
Any of mode is implementing.For example, it is possible between the first conductor pin and the circuit surface of base plate for packaging, or lead second
Between scapus and the surface of chip electrode, or place solder bump between the first conductor pin and the second conductor pin, by high temperature
Under Reflow Soldering fetch realization electrical connection.In the case, the circuit surface of base plate for packaging may include pad for welding core
First conductor pin of piece side, or the electrode surface of chip include pad for weld base plate for packaging side the second conductor pin.
In addition, the first conductor pin can also be formed on the pad in chip electrode, the second conductor pin can also be formed at base plate for packaging
Line pattern in pad on.After electrical connection, potting resin can also carry out in base plate for packaging with the gap of chip
Encapsulating, to fix each device so that whole encapsulating structure is not readily susceptible to damage or due to various rings in use
Border factor and lost efficacy.
Figure 11 (a) and 11 (b) are shown respectively the conductor that will be formed on the surface 14 of chip electrode as shown in Fig. 3 (e)
The conductor of one or more chip is formed and runs through on post 20, the hole wall in the hole in being opened in chip as shown in Fig. 7 (d)
Post 20 is electrically connected to the cross-section structure of flip-chip product obtained from the circuit surface 44 of base plate for packaging 40.Figure 11 (c) shows
Conductor pin 20 in the circuit surface 44 being formed at base plate for packaging 40 as shown in Fig. 9 (d) is electrically connected on chip 10
The cross-section structure of flip-chip product obtained from chip electrode 12.Additionally, Figure 11 (d) and 11 (e) respectively illustrate such as Fig. 3
The conductor pin 20 being formed on the surface 14 of chip electrode shown in (e), the hole in being opened in chip as shown in Fig. 7 (d)
Hole wall on formed and run through the conductor pin 20 of one or more chip and be formed at base plate for packaging 40 shown in Fig. 9 (d)
Conductor pin 20 in circuit surface 44 be electrically connected to each other obtained from flip-chip product cross-section structure.These flip-chip are produced
Product all include base plate for packaging, chip and the conductor pin being located between base plate for packaging and chip and electrically connecting them, conductor pin
Including the conductor thickening layer of conductive seed layer and the column being formed above conductive seed layer, this conductive seed layer is arranged on core
The hole wall in the surface of plate electrode or the hole in being formed at chip or in the circuit surface of base plate for packaging, and include from
Sub- implanted layer and/or plasma deposited layers.
In the flip-chip product of gained, conductor pin 20 that chip 10 is electrically connected to base plate for packaging 40 have including from
Sub- implanted layer and/or the conductive seed layer of plasma deposited layers.As it was noted above, having very between this conductor pin and matrix
High adhesion, thus the flip-chip product of gained also will have very high stability and reliability it is not easy to lose efficacy
Or fault.Further, since ion implanted layer and/or plasma deposited layers have the good uniformity and compactness, no
Pin hole or seminess easily occur, conductor pin also therefore has good structural intergrity, rigidity and electric conductivity, thus gained
Flip-chip product also will there is excellent robustness, electric conductivity and hot property, can be widely used in various electronics and produce
In product.
Above-described content is only referred to preferred embodiment of the present utility model.However, this utility model is not subject to
It is limited to the specific embodiment described in literary composition.Those skilled in the art will readily occur to, without departing from main idea of the present utility model
In the range of, these embodiments can be carried out with various obvious modifications, adjustment and replacement, with make it suitable for specific feelings
Shape.In fact, protection domain of the present utility model is defined by the claims, and may include those skilled in the art can be pre-
The other examples expected.If such other examples have the structural element with the literal language zero difference of claim, or
If person they include the equivalent structural elements that there are non-limiting difference with the literal language of claim, then they will fall
In scope of the claims.
Claims (10)
1. a kind of conductor pin, the conductor including conductive seed layer and the column being formed above described conductive seed layer thickeies
Layer, described conductive seed layer is arranged on the hole wall on the surface of chip electrode or the hole in being formed at chip or is encapsulating base
In the circuit surface of plate, and include ion implanted layer and/or plasma deposited layers.
2. conductor pin according to claim 1 is it is characterised in that described ion implanted layer is located at the table of described chip electrode
The lower section of the circuit surface of the hole wall in face or described hole or described base plate for packaging, be by chip electrode material or chip substrates or
The line material of person's base plate for packaging and the doped structure of conductive material composition.
3. conductor pin according to claim 1 is it is characterised in that described plasma deposited layers are located at described chip electrode
Surface or the hole wall in described hole or described base plate for packaging circuit surface top.
4. conductor pin according to claim 1 it is characterised in that described conductive seed layer comprise Ti, Cr, Ni, Cu, Ag,
One of Al, Au, V, Zr, Mo, Nb, In, Sn, Tb and the alloy between them, described conductor thickening layer comprise Cu, Ag,
One of Al, Au and the alloy between them.
5. conductor pin according to claim 1 is it is characterised in that described conductor pin is in solid or hollow column, one
The inside of described chip or base plate for packaging is imbedded at end, and the other end is located at the surface of described chip or base plate for packaging.
6. a kind of flip-chip product, including base plate for packaging, chip and be located between described base plate for packaging and described chip simultaneously
The conductor pin that they are electrically connected, described conductor pin includes conductive seed layer and the post being formed above described conductive seed layer
The conductor thickening layer of shape, described conductive seed layer be arranged on the surface of chip electrode or the hole in being formed at chip hole wall,
Or in the circuit surface of base plate for packaging, and include ion implanted layer and/or plasma deposited layers.
7. flip-chip product according to claim 6 is it is characterised in that described ion implanted layer is located at described chip electricity
The lower section of the circuit surface of the hole wall in the surface of pole or described hole or described base plate for packaging, is by chip electrode material or chip
The line material of base material or base plate for packaging and the doped structure of conductive material composition.
8. flip-chip product according to claim 6 is it is characterised in that described plasma deposited layers are located at described core
The top of the circuit surface of the hole wall in the surface of plate electrode or described hole or described base plate for packaging.
9. flip-chip product according to claim 6 is it is characterised in that described conductor pin is in solid or hollow post
Shape, its one end imbeds the inside of described chip or base plate for packaging, and the other end is located at the surface of described chip or base plate for packaging.
10. flip-chip product according to claim 6 is it is characterised in that the conductive seed layer of described conductor pin runs through
Chip piece or stacked together two pieces or many chip blocks.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620482783.6U CN205984964U (en) | 2016-05-25 | 2016-05-25 | Conducting cylinder and chip flip -chip product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620482783.6U CN205984964U (en) | 2016-05-25 | 2016-05-25 | Conducting cylinder and chip flip -chip product |
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| Publication Number | Publication Date |
|---|---|
| CN205984964U true CN205984964U (en) | 2017-02-22 |
Family
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| CN201620482783.6U Active CN205984964U (en) | 2016-05-25 | 2016-05-25 | Conducting cylinder and chip flip -chip product |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105870093A (en) * | 2016-05-25 | 2016-08-17 | 武汉光谷创元电子有限公司 | Conducting cylinder, manufacturing method thereof, chip packaging method and flip chip product |
| CN107022747A (en) * | 2017-04-05 | 2017-08-08 | 武汉光谷创元电子有限公司 | Microwave-medium part and its manufacture method |
-
2016
- 2016-05-25 CN CN201620482783.6U patent/CN205984964U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105870093A (en) * | 2016-05-25 | 2016-08-17 | 武汉光谷创元电子有限公司 | Conducting cylinder, manufacturing method thereof, chip packaging method and flip chip product |
| WO2017202037A1 (en) * | 2016-05-25 | 2017-11-30 | 武汉光谷创元电子有限公司 | Conductor post and manufacturing method thereof, chip packaging method, and flip chip product |
| CN105870093B (en) * | 2016-05-25 | 2021-02-02 | 武汉光谷创元电子有限公司 | Conductor pillar, manufacturing method thereof, method for packaging chip and flip chip product |
| CN107022747A (en) * | 2017-04-05 | 2017-08-08 | 武汉光谷创元电子有限公司 | Microwave-medium part and its manufacture method |
| CN107022747B (en) * | 2017-04-05 | 2019-12-31 | 武汉光谷创元电子有限公司 | Microwave dielectric member and method for manufacturing same |
| US11552617B2 (en) | 2017-04-05 | 2023-01-10 | Richview Electronics Co., Ltd. | Microwave dielectric component and manufacturing method thereof |
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