TWI265559B - Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions - Google Patents

Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions Download PDF

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Publication number
TWI265559B
TWI265559B TW092105159A TW92105159A TWI265559B TW I265559 B TWI265559 B TW I265559B TW 092105159 A TW092105159 A TW 092105159A TW 92105159 A TW92105159 A TW 92105159A TW I265559 B TWI265559 B TW I265559B
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Taiwan
Prior art keywords
substrate
doped
base
doping
region
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Application number
TW092105159A
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English (en)
Chinese (zh)
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TW200305938A (en
Inventor
Andy C Wei
Derick J Writers
Mark B Fuselier
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Advanced Micro Devices Inc
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Publication of TW200305938A publication Critical patent/TW200305938A/zh
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Publication of TWI265559B publication Critical patent/TWI265559B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6706—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing leakage current 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers

Landscapes

  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW092105159A 2002-03-21 2003-03-11 Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions TWI265559B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/104,319 US6780686B2 (en) 2002-03-21 2002-03-21 Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions

Publications (2)

Publication Number Publication Date
TW200305938A TW200305938A (en) 2003-11-01
TWI265559B true TWI265559B (en) 2006-11-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW092105159A TWI265559B (en) 2002-03-21 2003-03-11 Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions

Country Status (9)

Country Link
US (2) US6780686B2 (https=)
JP (1) JP4470011B2 (https=)
KR (1) KR100913830B1 (https=)
CN (1) CN100399582C (https=)
AU (1) AU2002361759A1 (https=)
DE (1) DE10297679B4 (https=)
GB (1) GB2409335B (https=)
TW (1) TWI265559B (https=)
WO (1) WO2003081678A1 (https=)

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US7838875B1 (en) * 2003-01-22 2010-11-23 Tsang Dean Z Metal transistor device
US7638841B2 (en) 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
TWI248681B (en) * 2004-03-29 2006-02-01 Imec Inter Uni Micro Electr Method for fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel
JP4664631B2 (ja) * 2004-08-05 2011-04-06 株式会社東芝 半導体装置及びその製造方法
US7230270B2 (en) * 2004-11-24 2007-06-12 Taiwan Semiconductor Manfacturing Company, Ltd. Self-aligned double gate device and method for forming same
US7605042B2 (en) * 2005-04-18 2009-10-20 Toshiba America Electronic Components, Inc. SOI bottom pre-doping merged e-SiGe for poly height reduction
US7314794B2 (en) * 2005-08-08 2008-01-01 International Business Machines Corporation Low-cost high-performance planar back-gate CMOS
US7442586B2 (en) * 2006-03-31 2008-10-28 International Business Machines Corporation SOI substrate and SOI device, and method for forming the same
US7285480B1 (en) * 2006-04-07 2007-10-23 International Business Machines Corporation Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof
US7629649B2 (en) * 2006-05-09 2009-12-08 Atmel Corporation Method and materials to control doping profile in integrated circuit substrate material
JP5057804B2 (ja) 2007-03-12 2012-10-24 株式会社東芝 半導体装置
US8120110B2 (en) * 2008-08-08 2012-02-21 International Business Machines Corporation Semiconductor structure including a high performance FET and a high voltage FET on a SOI substrate
US8012814B2 (en) * 2008-08-08 2011-09-06 International Business Machines Corporation Method of forming a high performance fet and a high voltage fet on a SOI substrate
US8174067B2 (en) 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
DE102009006800B4 (de) * 2009-01-30 2013-01-31 Advanced Micro Devices, Inc. Verfahren zur Herstellung von Transistoren und entsprechendes Halbleiterbauelement
US8471340B2 (en) 2009-11-30 2013-06-25 International Business Machines Corporation Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure
US8698244B2 (en) * 2009-11-30 2014-04-15 International Business Machines Corporation Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method
US8299545B2 (en) * 2010-01-28 2012-10-30 International Business Machines Corporation Method and structure to improve body effect and junction capacitance
US8432000B2 (en) 2010-06-18 2013-04-30 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
US8421156B2 (en) * 2010-06-25 2013-04-16 International Business Machines Corporation FET with self-aligned back gate
US8664067B2 (en) * 2010-11-18 2014-03-04 Monolithic Power Systems, Inc. CMOS devices with reduced short channel effects
US8507989B2 (en) * 2011-05-16 2013-08-13 International Business Machine Corporation Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance
JP5456090B2 (ja) * 2012-03-13 2014-03-26 株式会社東芝 半導体装置およびその製造方法
CN103779212B (zh) * 2012-10-18 2016-11-16 中国科学院微电子研究所 半导体结构及其制造方法
CN103311301B (zh) * 2013-05-09 2016-06-29 北京大学 一种抑制辐射引起背栅泄漏电流的soi器件及其制备方法
US9620617B2 (en) * 2014-09-04 2017-04-11 Newport Fab, Llc Structure and method for reducing substrate parasitics in semiconductor on insulator technology
US10062713B1 (en) 2017-09-08 2018-08-28 Nxp Usa, Inc. Devices and methods for fully depleted silicon-on-insulator back biasing
EP3742476B1 (en) * 2019-05-20 2024-11-06 Infineon Technologies AG Method of implanting an implant species into a substrate at different depths
CN112038405B (zh) * 2020-08-19 2024-06-18 深圳市紫光同创电子有限公司 场效应晶体管及其制备方法、静态随机存储器、集成电路
CN112765922B (zh) * 2020-12-31 2024-04-19 中国科学院上海微系统与信息技术研究所 采用soi衬底的射频晶体管的仿真模型
US11984479B2 (en) * 2021-02-17 2024-05-14 Analog Devices International Unlimited Company Hybrid field-effect transistor

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Also Published As

Publication number Publication date
JP4470011B2 (ja) 2010-06-02
CN1623237A (zh) 2005-06-01
DE10297679T5 (de) 2005-05-19
US6876037B2 (en) 2005-04-05
GB2409335A (en) 2005-06-22
CN100399582C (zh) 2008-07-02
GB0418683D0 (en) 2004-09-22
TW200305938A (en) 2003-11-01
WO2003081678A1 (en) 2003-10-02
US6780686B2 (en) 2004-08-24
US20040169227A1 (en) 2004-09-02
GB2409335B (en) 2005-09-14
KR20040087345A (ko) 2004-10-13
JP2005521265A (ja) 2005-07-14
AU2002361759A1 (en) 2003-10-08
KR100913830B1 (ko) 2009-08-26
US20030178678A1 (en) 2003-09-25
DE10297679B4 (de) 2008-09-25

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