TWI249192B - Coated semiconductor wafer, and process and device for producing the semiconductor wafer - Google Patents

Coated semiconductor wafer, and process and device for producing the semiconductor wafer Download PDF

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TWI249192B
TWI249192B TW093118123A TW93118123A TWI249192B TW I249192 B TWI249192 B TW I249192B TW 093118123 A TW093118123 A TW 093118123A TW 93118123 A TW93118123 A TW 93118123A TW I249192 B TWI249192 B TW I249192B
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semiconductor wafer
susceptor
cvd
chemical vapor
vapor deposition
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TW093118123A
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TW200501243A (en
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Reinhard Schauer
Norbert Werner
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Siltronic Ag
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4581—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber characterised by material of construction or surface finish of the means for supporting the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/12—Substrate holders or susceptors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Chemical Vapour Deposition (AREA)
  • Drying Of Semiconductors (AREA)

Description

1249192 五 發明說明（1) 一、【發明所屬之技術領域】 化學蒸氣沉積⑽）（尤其於兩面 之外延層沉積）包括面對所謂"自動捭 夕片明®上 象。就"自動摻雜"而言，摻質自丰逡擁曰軍圈兩種現 相傳入流經半導體晶圓正面上方之沉積：：背面經由氣體 等摻質混入半導體晶圓正面邊緣 層： 二内傳導度或多或少顯著、非所願心起二致皮外 應了解的是’"暈圈詞係指半導體晶㈣面 射結構所引起之散射光效果且传於用 政 ::圓背面時顯現出來。該等結構在半導體晶圓背面上留= ::轉變痕跡，在該等轉變處，&有天然氧化物層之 與無此類氧化物層之區域相鄰。實際沉積階段未完成之前 ，在所謂"預烤"之預熱階段過程中若移除天然氧化物層， 同樣會發生非所願轉變。 二、【先前技術】 、為避免有關自動摻雜之問題，美國專利us 6, 129, 〇47 中曾，議：於承受半導體晶圓之基座槽底部設置若干切口 j該等切口係配置在該底部之外緣。自半導體晶圓背面擴 政^來之摻質可經由該等切口自反應器移除，無需首先通 過半導體晶圓之正面。依照美國專利⑽2〇〇1/〇〇37761 A1 ’作同樣用途之基座之整個底部内有若干小孔洞。再者， 利用沖洗氣體之掃除有助於自半導體晶圓背面擴散出來摻 質之移除。該兩種措施亦對暈圈之形成具有防止作用，蓋
1249192 程中所生 流動體之 除。 非全然無 之溫度場 ，則對半 形一詞係 1 〇公厘側 上之過程 同沉積速 國專利us 徑及藉調 五、發明說明（2) 因由於天然氧化物溶解過 由底部之孔洞及沖洗氣體 施使天然氧化物層容易移 但’使用所述基座並 半導體晶圓背面及正面上 孔洞之直徑超過某種尺寸 形具有不良影響。奈米構 咼度起伏變化（於一 〇·5至 層沉積在半導體晶圓正面 溫度起伏變化導致局部不 變化。為避免該問題，美 建議：限制該等孔洞之直 度場更加均勻。 但’該等措施僅對半 諸發明人所證實者，若所 晶圓背面奈米構形數值甚 °月半導體晶圓背面之溫度 洗氣體（例如：氫）所引起 面之沉積氣體所引起之局 構形具有不良影響，該不 晶圓正面上製作電子元件 =不均勻亦會引起步進器 二、【發明内容】 本發明之内容係一具 氣態反應生成物同樣經 協助傳遞出去，該等措 問題’盍因該等孔洞對 具有影響。若基座底部 導體晶圓正面之奈米構 用以描述奈米範圍内之 面上所量得）。在外延 中，該等孔洞所引起之 率及最終上述高度起伏 2001/0037761 Α1 中曾 適燈光加熱之功率使溫 導體晶圓之正面有效。如本發明 選基座内孔洞直徑愈小，半導體 ^變得愈差。該等孔洞之出現意 場保持相當不均勻，以致發生沖 ，局部蝕刻及到達半導體晶圓背 部沉積。該兩種現象對背面奈米 良影響不能忍受，蓋因在半導體 過程中，即使半導體晶圓背面上 之聚焦問題。 有一背面 業經化學蒸氣沉考
第6頁 1249192 五、發明說明（3) 法（CVD )塗層正面及一拋光或餘刻背面之半導體晶圓、及 一種用以製造該半導體晶圓之方法。本發明之另一内容係 一用化學蒸氣沉積法（CVD)沉積一薄層在半導體晶圓正面 上之過程中用以置放半導體晶圓之基座。 本發明之内容係一具有一背面、一業經化學蒸氣沉積 法（CVD)塗層正面及一拋光或姓刻背面之半導體晶圓，其 中背面之奈米構形（以高度起伏變化峰谷（PV)表示）低於5 奈米。 本發明之另一内容係一種用以製造半導體晶圓之方法 ’該半導體晶圓具有一藉化學蒸氣沉積法（CVD)沉積一層 之正面及一經拋光或餘刻之背面，沉積該層時，半導體晶 圓係置於一基座上，俾該半導體晶圓之背面面向該基座之 底部，其中氣態物質係自半導體晶圓上方之區域、主要經 過基座内之孔洞、抵達基座背面上方之區域内。 本發明之另一内容係於用化學蒸氣沉積法（CVD )沉積 一層在半導體晶圓正面上之過程中置放半導體晶圓之基座 ，該基座之氣體穿透結構之孔積率（孔洞體積/總體積）至 少為15%，尤以至少為20%更佳，其密度為〇· 5至丨· 5公克/ 立方公分，尤以〇·8至1.4公克/立方公分更佳。該基座之 材質以石墨或具有上述特性之石墨纖維為佳，尤以塗以碳 化矽之石墨或塗以碳化矽具有上述特性之石墨纖維更佳。 四、【實施方式】 本發明之目的在顯示如何可適當避免自動摻雜、暈圈 、及正面與背面之不良奈米構形。
1249192
片J半晶圓最好係一正面上有-外延沉積層之石夕基 片曰n 3半導體晶圓之背面係經拋光及蝕刻者。該義 ^ Γ，'ίη_掺雜者為佳，尤以用硼作摻質之p-摻雜i t情況下，摻雜度可以是” "+及p++。其中Γ 摻：度P'對應於電導度約0.0 05至約。。3歐姆*公分f更中： ，尤Ϊ : 以?摻雜者為佳，#以用硼作為摻質者較佳
。ί = 5Ρ對應於電導度約1至約2°歐姆*公分者更佳 米為Γϊί用途而定，外延層之厚度以u微米至_微 〇 5八厂半導體晶圓正面之奈米構形（以標準表面積 方开广曰里!5公厘、2公厘χ 2公厘或10公厘χ 10公厘之正 為基準)最好低於5奈米。該半導體晶圓背面 準Γ低=米最好以表面積10公厘χ 10公厘之量測窗為基 且右IΓ ί方法與習知方法之特別差異在於藉助於使用一 ;期资栌：構之基座’肖多孔結構之氣體穿透性足以達成 ，期乳體輸送。該基座之效果使早在預熱階段即感受到其 存在，當時該基片晶圓接受預熱且曝露於沖洗氣體（由貴、 重氣體或氮等惰性氣體組成）及/或還原氣體（氫），俾移除 該天然氧化物層。如同由基片晶圓擴散出來之摻質，氧化 物層溶解過程中所形成之氣態反應生成物，經由基座之孔 洞逃逸至基座之背面，用沖洗氣體流動體將該等氣態反應 生成物帶走並自反應器中移除。俟氧化物層移除之後，沖 洗氣體中可添加氣化氫，最好在外延層沉積之前，俾使半 導體晶圓之正面平滑。為沉積外延層，將基片晶圓提昇至
1249192 五、發明說明（6) & 一實驗例為基準，茲將本發明與既有技術作_比較 如下。為達成比較之目的，所用者係一由塗有碳化石夕石墨 所製、附有不同直徑孔洞之標準基座（比較例）。該材料之 密度约為1· 85公克/立方公分。另一同樣形狀之基座係由 塗有碳化矽之石墨氈製成（實驗例）。該基座材料之孔^率 約為25%及密度约為〗·35公克/立方公分。 在單一晶圓反應器内’許多由ρ -摻雜、以,為推質 之矽所製基片晶圓備有一ρ+-摻雜（同樣以硼為摻質）矽外延 層，總是使用上述若干型基座中之一種基座。該外延 沉積作用係依照既有技術實施且包含一傳 =半導想晶圓測試其正面及背面之自動=烤=及 υ ’曾依照比較例利用_基座加以塗 導體曰曰圓’其奈米構形值遠較依照本 者差。以表面積為1〇χ 10公厘之量 導體晶圓 例内半導體晶圓所達成奈米構形值均二’所有比較 第三至第五圖所示，基座内未此低於5奈米。如 高度偏差愈大。在對比下所直禮愈小’可能測定之 其背面上之奈米構形值均低於5奈米驗。例内之半導體晶圓， 1249192 圖式簡單說明 第一圖：本發明具有纖維結構之基座剖面圖。 第二圖：本發明具有微粒結構之基座剖面圖。 第三圖：晶圓背面孔洞直徑0. 5公厘之奈米構形。 第四圖：晶圓背面孔洞直徑1 · 0公厘之奈米構形。 第五圖··晶圓背面孔洞直徑1. 5公厘之奈米構形。 ΙϋΗΗ

Claims (1)

1249192 六、申請專利範圍 1· 一種於用化學蒸氣沉積法（CVD)沉積一層在半導體晶 ，正面上之過程中用以置放半導體晶圓之基座，該基座之 t體穿透結構之孔積率至少為15%，其密度為0 5至15公 克/立方公分。 2.如申請專利範圍第1項之基座，其中該結構實質上含 有石墨纖維。 3 ·如申明專利範圍第1項之基座，其中該結構實質上含 有石墨微粒。 4.如申請專利範圍第1、2或3項之基座，該基座包含一 碳化石夕塗層。 5·如申請專利範圍第4項之基座，其中碳化矽塗層之厚 度自基座表面朝基座内部遞減。 6. 一種具有一背面、一業經化學蒸氣沉積法（CVD)塗層 正面及一拋光或蝕刻背面之半導體晶圓，其中 之卉米 構形（以高度起伏變化峰谷（PV)表示）低於5太米 不^ 7· 一種用以製造半導體晶圓之方法，該半$導體晶圓具有 一藉化學蒸氣沉積法（CVD)沉積一層之正面及一緩拋光或 蝕刻之背面，沉積該層時，半導體晶圓係置於一某上， 俾該半導體晶圓之背面面向該基座之底邮 &心低邵，其中翁離物皙 係自半導體晶圓背面上方之區域、主要錄、甘 亂^ M 土要經過基座内之孔洞 、抵達基座背面上方之區域内。
TW093118123A 2003-06-26 2004-06-23 Coated semiconductor wafer, and process and device for producing the semiconductor wafer TWI249192B (en)

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DE10328842A DE10328842B4 (de) 2003-06-26 2003-06-26 Suszeptor für eine chemische Gasphasenabscheidung, Verfahren zur Bearbeitung einer Halbleiterscheibe durch chemische Gasphasenabscheidung und nach dem Verfahren bearbeitete Halbleiterscheibe

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US (1) US7101794B2 (zh)
JP (2) JP4195417B2 (zh)
KR (1) KR100633757B1 (zh)
CN (1) CN100394550C (zh)
DE (1) DE10328842B4 (zh)
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JP2005020000A (ja) 2005-01-20
TW200501243A (en) 2005-01-01
CN100394550C (zh) 2008-06-11
KR20050001372A (ko) 2005-01-06
JP4773413B2 (ja) 2011-09-14
US20040266181A1 (en) 2004-12-30
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