TWI242275B - Multi-column wire bonding structure and layout method for high-frequency IC - Google Patents

Multi-column wire bonding structure and layout method for high-frequency IC Download PDF

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TWI242275B
TWI242275B TW092113276A TW92113276A TWI242275B TW I242275 B TWI242275 B TW I242275B TW 092113276 A TW092113276 A TW 092113276A TW 92113276 A TW92113276 A TW 92113276A TW I242275 B TWI242275 B TW I242275B
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Taiwan
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row
wire
pads
wire bonding
integrated circuit
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TW092113276A
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English (en)
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TW200427032A (en
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Jimmy Hsu
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Via Tech Inc
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Priority to TW092113276A priority Critical patent/TWI242275B/zh
Priority to US10/778,143 priority patent/US20040227226A1/en
Publication of TW200427032A publication Critical patent/TW200427032A/zh
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Publication of TWI242275B publication Critical patent/TWI242275B/zh

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    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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Description

1242275 五、發明說明（1) 【發明所屬之技術領域】 本發明是有關於一種高頻積體電路多排打線結構及佈 局方法，特別是有關於同時使用正反打線之高頻積體電路 多排打線結構及佈局方法，以使晶片與封裝體間之電性連 接月b具有最佳之電氣特性。 【先前技術】 電子構裝的目的可以歸納為傳遞電能、傳遞電路訊 號、提供散熱途徑與結構保護與支持。如果將IC晶片與各 種電路零件分別比喻成人體頭腦與身體内部的各項器官， 電子構裝有如將這些器官組合而成的肌肉骨架，構裝中的 連線電路一如血管神經提供能量與電路訊號傳遞的路徑， 以使此IC晶片與各種電路構裝後所形成的電子產品功能得 以發揮。由於在電子產品在工作頻率與效能上不斷推陳出 新’因此為使電子產品之電氣特性表現能夠最佳，構裝技 術即是一種可使電子產品效能與層次提升的顯然因素。 請參考圖一，圖一繪示的是習知構裝元件之俯視示意 圖。此構裝元件100主要具有晶片（頭腦）105以及内部含 有連線電路（血管神經）之基板丨丨〇。晶片1〇〇與基板丨1() 間之電性連接則透過將金屬線丨4〇等打線於晶片上之銲塾 130及基板上之銲墊12〇來完成。而晶片（頭腦）ι〇5與佈 有電子零件（器官）之印刷電路板（未繪示）的電性連 接’為訊號經由金屬線丨4 〇等以及基板11 〇内部連線電路 後’由引腳145導出至印刷電路板來完成。
五、發明說明（2) 面干f 圖’第：a圖繪是的是習知構裝元件之剖 二美:2彳 件20°主要包含有基板21。以及晶片 240。基板210上具有承載墊（die 廿站， 環氧樹酯層（eP〇xy，熱嫁膠）22 二輔上曰-層 240 ^ ^ ^ ,1 ^ ^ ^ ί；；Λ 243 ^板21 G引腳（lead )⑽、郎上之鮮_、=截來斷達於 不過，由於射頻電路或高速電路 大因需：:：frrbf知構裝元件會
^排列）’且為了使整個構裝元件2〇〇能具有較佳 J 特性，更將環氧樹酯層225鋪的較窄。 :二考第一Β圖，第二Β圖繪是的是習知構裝元件之 ，J思圖。銲塾245、247旁各增加銲墊m、249，且將以 乳树酯層225鋪的較二Α圖來的窄，、衣 =，225周圍之部分即可作為接地端載(墊因 =二 ^為絕緣體’故可作為接地端）。由於承載塾m 20 =%、乳樹酯層225周圍之部分即可作為接地端，故銲墊 、2 4 7上需接地之信號即不必透過^ ^ ^ ^ ^ ^ ^ ^ ^ =接經由金屬咖、27。’再透過承載丄 :¼能層225周圍之部分（為整圈環繞之線狀）接 ： ’㈡圖接地信號接地之距離較第二B圖來的短 (金屬線260、270比金屬線241、243短的多）， 1242275 五、發明說明（3) — 240的接地點直接藉由金屬線260、27〇以較短的距離來 同時將此連接至印刷電路板之接地，以達到較好 氣特性與良好的散熱的需求。 電 不過γ在射頻電路或高速電路中，構襞元件中晶 的接點雖藉由較短距離之金屬線與承載 提供多點接地處，但是於金屬線在打目接’ 嚴重的失真情形。況且，在射頻電路=時，有著較 ^ ^ ^ f ^QFN . BCC + + ,«SP # ^ 0、，構裝元件一般會鋪上一層膠膜覆 > 、网又（構裝 j板）較低之構裝體，而其金屬線線以及 的困難，而無法以在晶片上以三排並與打線時 仃不同弧高的打線。 式來對金屬線進 有鐘於此’本發明提出一籍古 j ::效降低元件間之介入損耗：及返回損：多排打線： 電戰*特性提升。 相耗，而使整髏 發明内容】 線 本發明的主要目的是提供一古 構，其旦有第一雷+ _从八種同頻積體電路多排 --^ ^電子兀件、第二電子元 f 。其中，第一電子元件更包 夕條金 第一打線面的一側表面，而第一 f子兀件
周圍分佈置’且第-群鲜塾自第-打線面周 H 第7頁 1242275 五、發明說明（4) 向順序而至+ π # π \ 1 電子元件，則為第一排銲墊與第二排銲墊。第二 二承載面用二承載面以及第二群銲墊。又第 載面相互心承元件並使第-承載面與第二承 合。第二群銲墊則：相互疊 載面位於相同一侧表：：佈於第：承載面周圍且與第二承 連接第一與第二雷早_ 。至=廷些金屬線，則用以電性 而至少可被區八A ^:，且廷些金屬線依據打線之方式 與反打線若干反打、線，且各正打線 斷端，其巾，這些正打線；：別具有打線之起始端與截 群銲墊中之某一：且這:匕之：：的起始端是連接於第- 第二群鮮墊中之某—：；這；截：端連接於 是連接於第二群銲墊中之草之某-的起始端卻 截斷端係連接於第一排銲墊中之某反打線中之某-的 本發明的次要目的是提供上述高頻積體電路 結構之佈局方法，&方法為：先將這些金屬線中^線 反打線方式起始第二群銲墊中之某—並截斷於一占、以 中之某一。再將這些金屬線中之某一 '、墊 第一群銲墊中之某一並截斷於第：群銲墊起始於 綜合上述’本發明提出一播古相 /、 構及方法’藉由同時使用正打線；式路2打線結 第二電子元件之連接方式，可實現第一電子元件與 線，且可有效降低元件間之介入損耗以丄J =並列打 整體電氣特性提升。 &回抽耗’而使
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I 1242275 五、發明說明（5) 【實施方式】 為使貴審查委員能對本發明之特徵、目的及功能有 更進一步的認知與瞭解，茲配合圖式詳細說明如後： 一般來說，構裝元件中金屬線打線方式可根據打線之 起始端與截斷端所在之位置來區分正打線或是反打線。舉 例來說’請參考圖三’圖三繪示的是習知構裝元件以正打 線模式佈局之立體示意圖。在構裝時，構裝元件3 〇 〇以金 屬線305先打線於晶片31 0上之銲墊330後，將金屬線3 0 5拉 高形成一個弧度，最後在截斷於基板32〇上之銲墊34〇。或 疋以金屬線315先打線於晶片310上之鲜墊335後，將金屬 線3 05拉高形成一個弧度，最後在截斷於基板32〇上之接地 線350。 ^ 此類將金屬線先打線於晶片上之銲墊，再將金屬線拉 高一個弧度，最後將金屬線截斷於基板上之銲墊或接地線 之方式，通稱為正打線之方式。 反之，請參考圖四，圖四繪示的是習知構裝元件以反 2線模式佈局之立體示意圖。在構裝時，構裝元件4 6 〇以 金屬線490先打線於基板470上之銲墊480後，將金屬線49〇 技高形成一個弧度（此弧度較在正打線方式中所形成之弧 度大，但弧高較低），最後在截斷於晶片4 6 5上之銲塾 475。或是以金屬線497先打線於基板470上之接地線485 後’再將金屬線497拉高形成一個弧度，最後在截斷於晶 片上之接地線450。 日日
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此類將金屬線先打線於 金屬線拉高一個弧度，最後 方式’通稱為反打線之方式 由於在構裝時，正打線 膠體高度限制與所產生打線 以三排並列方式來對金屬線 線的方式有著金屬線弧度較 度較長、電氣特性較差之堪 銲墊之晶片。 基板上之銲墊或接地線，再將 將金屬線截斷於晶片上銲墊之 〇 的方式有著金屬線弧高與QFN 時的困難，而無法以在晶片上 進行不同弧高的打線。而反打 大’以致晶片與基板間打線長 慮’且完全不適用於具有多排
、基於射頻電路或高速電路中，對構裝元件其工作頻率 與效能有著嚴苛的要求，因此本發明基於對正打線以及反 打線之佈局作為考量，提出一種打線佈局裝置及方法。
本發明提出一種同時使用正打線以及反打線方式之高頻積 體電路多排打線結構及方法。請參考圖五，圖五繪示的是 本發明較佳實施例之多排線佈局裝置示意圖。此多排打線 佈局裝置500主要具有電子元件及52〇。此電子元件51〇 及5 2 0可分別例如是晶片或是基板，而在此較佳實施例 中，電子元件5 1 0為晶片，電子元件5 2 〇為基板。其中，晶 片5 1 0具有打線面5 〇 5，晶片5 1 〇相對於打線面5 〇 5之另一側 面則具承載面507。打線面505周圍設置有一群銲墊，且自 打線面5 0 5周圍往打線面5 〇 5中心至少設置有兩排以上之銲 墊，在此較佳實施例中，打線面5〇5上設置有第一排銲墊 530、第二銲墊535以及第三排銲墊54〇。至於基板52〇上， 則具有承載面550，晶片510之承載面5〇7則疊合於此承載
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五、發明說明（7) 面5 5 0之上 在承載面550周圍還亦設置有一群銲墊，可自承载面 5 5 0周圍往承載面5 5 〇中心設置多排之銲墊，而在此較佳實 施例中，承載面5 5 0上設置有兩排銲墊5 5 3、5 5 7，且承载 面550上，還設置有整圈圍繞在晶片51〇周圍之線狀銲塾 5 5 5 (類似圓圈）。 至於金屬線間佈局，為先將金屬線以反打線方式起始 基板520上銲墊群中之其一並截斷於晶片51〇銲墊群中第— 排銲塾中之其一，再將金屬線以正打線方式起始於晶片 510上銲墊群中之其一並截斷於基板52〇銲墊群中之其一。 在此較佳實施例中則是首先將金屬線543先以反打線方式 起始於線狀銲墊555並截斷於第一排銲墊530中之某_，再 將金屬線537以正打線方式起始於第二排銲墊535中之某一 並截斷於第五排銲墊557中之某一，以及最後將金屬線53~3 以正打線方式起始於第三排銲墊54〇中之某一並截 四排銲塾553中之某一。 當金屬線543、53 7、533將晶片510與基板520連接* =，：可進行膠膜590的鋪置，到此’此高頻積體電ς 夕排打線結構5 〇 〇即完成。 在此較佳實施例中，由於以反打線方式進行 上第一排銲墊5 30之打線，因此金屬線543在第一 530上之弧高與第一排銲墊53〇之高度幾乎相同。、 ，片510上第二排銲墊535上之金屬線537可維持正 高’第三排銲墊54Q上之金屬線533亦只需將弧高拉高至較
第11頁 1242275 五、發明說明（8) =屬線5 3 7略问之弧咼即可。故本發明之設計除了可運用 =排並列或父錯之銲塾群’亦可運三排並列或 之銲墊群。 =參考圖六A、六b及七a、七8。圖六A、六B分別缘示 .疋為兩排及三排交錯銲墊群之示意圖，圖七A、七B分別 繪示的是兩排及三排並列銲塾群之示意圖。 ，外，清再參考圖五，在此較佳實施例中，高頻信號 H由金屬線537、533在晶片510與基板52〇間流通，而高 ’ σ唬之接地則可藉由之金屬線543由晶片導引至基板Η5
=之線狀銲墊555(通常作為接地端）。因此，可在高頻 =之金屬、線，旁安排與其平行且藉由反打線方式產生在 =片端較低弧高、較短距離之接地保護線路，來完成整個 冋頻信號的傳輸。 故，本發明多排線佈局裝置之設計除了將整體金屬線 ，兩降低，同時藉由反打線方式可有效降低其介入損耗以 返回損耗，而整體提升元件間之電氣特性。
>、本發明之功效更可藉由在相同架構下之構裝元件分 施以習知打線佈局方式以及本發明正反打線同時運用之 局方式間之比較，來得知。請參考圖八A及第八B，圖八A 及第八B分別繪示的是習知打線佈局方式及本發明較佳徐 施例打線佈局方式之立體示意圖。第八A圖中，構裝元^ 80〇具有晶片810以及基板83 0，晶片810上具有兩排銲墊 第一排銲墊為銲墊817〜823，第二排銲墊為銲墊811〜， 815。基板上830具有一排銲墊831〜835以及線狀銲墊
1242275 五、發明說明（9) 84〇 :其中，銲墊813以及銲墊833分別為晶片81〇及基板 830上之信號端，其他銲塾則均為接地端，且銲塾間金屬 式均為··將金屬線以正打財式起始於晶片 810上之銲墊群並截斷於基板83〇上之銲墊群。其中， =上信號線平行的兩側，以鲜塾81 9、821上線路接 呆Λ線路 '同時請參考圖八β，在相同之架構 θ將八属綠、圖中之保濩線路以反打線之方式接地，也就 ί墊心9、8二反ί、Ϊ之ί式起始於線狀鮮墊840並截斷於 立線路#、® si 〇虽咼頻信號於構裝元件8〇〇中傳遞時，當 損圖之5線模式時，此構裝元件_之介入 相對庫读"τ回貝耗會杈其線路使用圖八A之打線模式時， 以月ΐ 此構裝元件800在高頻信號下，其介入損耗
= 實驗數據可參考圖九A、W及九C。圖九A =二Ϊί構裝元件分別以習知打線佈局及本發明 佈】及：ί :二的•是相同結構構裝元件分別以習知打線 之頻率響應比打二佈的局 耗與=損耗之頻率^比^的疋九Α及九Β圖中介入損 局之局種=運用正反打線方式佈 正打線方式金屬綠ΐ j i ί，其* # *反打 '線*式降低 實現可使用三排並列打線弧：萨=膠膜高度的構裝體中 高頻信號之介入損耗及:由反打線方式可有效降低 粍以及返回彳貝耗，使高頻信號能完整傳 第13頁 1242275
而提升其整 遞且降低在信號連接端處阻抗不匹配 體電氣特性。 反射 唯以上所述者，僅為本 之限制本發明的範圍。即大 之均專變化及修飾，仍將不 離本發明之精神和範圍，故 狀況。 發明之較佳實施例，當不能以 凡依:本發明申請專利範圍所做 失本發明之要義所在，亦不脫 都應視為本發明的進一步實施
£42275 圖式簡單說明 【圖式簡單說明， 圖'一繪不的是習冬 圖二A %示的是羽 凌元件之俯視示意圖· 第二B圖繪示的是卿獨1装元件之剖面示意圖； |貨知構裝元件 ， 示意圖； ，^構裝 ^知構袈 ’ 圖三繪示的是習知二構裝元件之剖面示意圖； 元件以正打線模式佈局之立體 圖四繪示的是習知 示意圖； 〇構装元件以反打線模式佈局之立體 圖五繪示的是較佳振 圖； 汽施例之多排線佈局裝置之示意 一立圖六A、六Β分別 一 不思圖； y、的是為兩排及三排交錯銲墊群之 立圖七A、七B分別給_ 思圖； "V的是兩排及三排並列銲墊群之示 圖八A、八Β分別给一 車又佳實施例打線佈局^不的是習知打線佈局方式及本發明 圖九A繪示的是°相s式之立體示意圖； 局及本發明較佳實施目同結構構裝元件分別以習知打線佈 頻率響應比較圖；·打線佈局下，高頻信號介入損耗之 圖九β繪示的e柏 局及本發明較佳杏疋雜你丨^結構構裝元件分別以習知打線佈 頻率響應比較圖T J打線佈局τ，高頻信號返回損耗之 頻率Ξ 繪不的是九A及九β圖中介入損耗與返回損耗之 貝半響應比較表。 义
1242275 圖式簡單說明 圖號說明： 100、200 > 30 0、460、500、800、850 ：構裝元件 105 、 240 、 410 、 465 、 510 、 810 :晶片 110、210、320、470、520、830 ：基板 120 ^ 130 、 237 、 239 ' 245 ' 247 ' 330 、 335 、 340 、 475 、 480 、495 > 530 、 535 '540 、553 、557 '811 >813 、815 ' 817 >819 >821 ' 823 '831 > 833 > 835 ：銲墊 350、485、555、840 :線狀銲墊
140 > 242 ^ 243 '260 ' 270 ' 305 、 315 、 490 、 497 、 533 、 537、543 ··金屬線 230 、 235 ：引腳 220 :承載墊 225 :環氧樹脂層
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Claims (1)

1242275
六、申請專利範圍 1. ，包含有： 片端； 中南頻信號的打線墊 一種高頻積體電路多排線打線結構 交錯排列之複數個打線墊在晶 複數個打線墊於封裝體端，其 係被兩個接地的打線墊包圍；以及 至少一個接地面； 其中高頻信號的打線墊自晶片端以正打線方式連接 至封裝體端的打線墊，而相鄰兩個接地迴路自接地面以 反打線方式連接至晶片端。 2 ·如申明專利範圍第1項所述之高頻積體電路多排線打線 結構，其中在晶片端上該些銲墊自晶片端周圍往晶片端 中〜方向至少可順序分為第一排打線墊以及第二排打線 塾0 3 ·如申凊專利範圍第1項所述之高頻積體電路多排線打線 結構’其中該封裝體端上銲墊自封裝體端周圍往封裝體 中心中心方向順序至少可被區分為第一排以及第二排。 4 ·如申請專利範圍第3項所述之高頻積體電路多排線打線 結構’其中晶片端上高頻信號的打線墊位於第二排。 5 ·如申請專利範圍第4項所述之高頻積體電路多排線打線 結構，其中高頻信號相鄰兩個接地迴路自接地面以反打 線方式連接至晶片端第一排打線墊。 6 ·如申請專利範圍第2項所述之，其中晶片端上還有第三 排打線墊。 7 · —種高頻積體電路多排線打線結構，包含有： 複數個打線墊在晶片端·，
第17頁 1242275 六、申請專利範圍 複數個打線墊在封裝體端，其中高頻信號的打線墊 係被兩個接地的打線墊包園；以及 至少一接地面； 其中高頻信號的打線弧高高於相鄰接地迴路的打線 弧高。 8.如申請專利範圍第7項所述之高頻積體電路多排線打線 結構，其中在晶片端上該些銲墊自晶片周圍至晶片中心 方向至少可順序分為第一排打線墊以及第二排打線塾。
9·如申請專利範圍第7項所述之高頻積體電路多排線打線 結構，其中該封裝體端上銲墊自封裝體端周圍往封裝體 中心中心方向順序至少玎被區分為第一排以及第二排。 I 0 ·如申請專利範圍第9項所述之高頻積體電路多排線打線 結構’其中晶片端上高頻信號的打線塾位於第二排。 II ·如申請專利範圍第丨〇項所述之高頻積體電路多排線打 線結構，其中高頻信號的打線墊自晶片端以正打線方 式連接至封裝體端的打線墊，而相鄰兩個接地迴路自 接地面以反打線方式連接至晶片端。
1 2 ·如申請專利範圍第丨丨項所述之高頻積體電路多排線打 線結構’其中高頻信號相鄰兩個接地迴路自接地面以 反打線方式連接至晶片端第一排打線墊。 1 3·如申請專利範圍第7項所述之高頻積體電路多排線打線 結構，其中晶片端上還有第三排打線墊。 1 4 · 一種高頻積體電路多排線打線結構，包括有：
一第一電子元件，其更包括有：
第18頁
TW092113276A 2003-05-16 2003-05-16 Multi-column wire bonding structure and layout method for high-frequency IC TWI242275B (en)

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