TWI235434B - Method of forming tunnel oxide film in semiconductor device - Google Patents

Method of forming tunnel oxide film in semiconductor device Download PDF

Info

Publication number
TWI235434B
TWI235434B TW092137146A TW92137146A TWI235434B TW I235434 B TWI235434 B TW I235434B TW 092137146 A TW092137146 A TW 092137146A TW 92137146 A TW92137146 A TW 92137146A TW I235434 B TWI235434 B TW I235434B
Authority
TW
Taiwan
Prior art keywords
oxide film
forming
film
angstroms
remove
Prior art date
Application number
TW092137146A
Other languages
English (en)
Other versions
TW200507109A (en
Inventor
Seung-Cheol Lee
Sang-Wook Park
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200507109A publication Critical patent/TW200507109A/zh
Application granted granted Critical
Publication of TWI235434B publication Critical patent/TWI235434B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

1235434 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一種於半導體裝置中形成穿隧氧化膜之 法，更具體地，係關於一種於半導體 、方 双直γ形成一可 因所吸收之碳成分及半導體基板表面變粗而造成薄膜口耕 下降之穿隧氧化膜之方法。 、口口貝 【先前技術】 訊至圖⑽用於説㈣半導體裝置中形成 膜之傳統方法之截面示意圖。 乳化 參照圖1Α’為形成一高壓電晶體之閉氧化膜，在 預確定m於半導體基板1上形成—厚度為3 第一氧化膜2。 之 參照圖1B，於第_傷外赠ο u r二、 虱化膜2上形成一光阻膜3，並將 膜3圖案化，以使形成記憶體單元及低壓電晶體之部分上所 形成的第一氧化膜2曝露。 參照圖1C，在執行-殘渣清除製程將圖案化光阻膜3清理 後’第-氧化膜2之曝露部分被去除。在此情形中，係使用 300.1 BOE (緩衝氧化物姓刻劑）浸泡2,2_而將第一 氧化膜2去除‘然後再使用一邮〇4溶液將光阻膜3去除，最 後用一 SC-U容液來執行一清洗製程。 、 參照圖1D’於整個頂部表面形成-80埃（人)厚之第二氧化 te4。在此忪形中’係於高壓電晶體區中形成一含有第一氧 化膜2及第二氣化膜〆 、之厗閘氧化膜，而於記憶體單元區及 低壓電晶體區中形忐_人士 & ^ έ有苐二氧化膜4之穿隨氧化膜。
O:\89\89720.DOC 1235434 依照上述之傳統方法，當使用—b〇e將記憶體單元區及 低屢電晶體區中之第一氧化膜2去除時，將產生3〇%之過声 飿刻’從而使半導體基板1之表面變粗，而在使用H2S〇i 液將光阻膜3去除時，亦會使含於光阻膜中之碳成分被半導 體基板1之表面吸收。但在形成穿随氧化膜以前，即使隨後 用-SCM溶液進行清洗、或預先用_5〇:1HF溶液進行清洗 ’均很難將所吸收之碳成分去除。結果，所遺留之碳成分 將導致半導體石夕形成虛懸結合，而這在穿随氧化薄膜係於 存在碳成分之情形下形成時，將使薄膜品質下降，進而導 致所製備之半導體裝置之電性能不良。 圖2及圖3係對依照傳統方法製成之快閃記憶體裝置實施 怪流應力測試（CCST)之結果，結果顯示其分佈均勻性不佳 且缺陷比例亦較高，尤其是大多數初始缺陷分佈於晶圓之 邊緣部分。 【發明内容】 因此，本發明旨在提供一種於半導體裝置中形成穿隧氧 化膜之方法，其中在形成高壓電晶體之閘氧化膜之後，於 去除§己憶體單元區及低壓電晶體區中氧化膜之製程中留下 一預確定厚度之氧化膜，藉此防止在去除氧化臈及光阻臈 過程中所造成之基板表面變粗、以及因所吸收之碳成分而 導致之污染。 本發明之一個方面係提供一種於半導體裝置中形成穿隧 氧化膜之方法，其包括以下步驟··（a)先於半導體基板上形 成一第一氧化膜，然後再形成一使記憶體單元區及低壓電 O:\89\89720.DOC -7- 1235434 μ. -區中之第氧化膜曝露之光阻圖案；（b)再將所曝露之 第氧化膜之預確定厚度以及光阻圖案相繼去除；以及⑷ 取後將遺留之第一氧化膜完全去除並於整個表面上形成一 第二氧化膜。 在别述之依照本發明之另一具體實施例之於半導體芽置 中：成穿瞻膜之方法中，第一氧化膜係於75〇。。至㈣ C μ度下所生長之厚度為35〇埃（A)至埃（a)之純氧化膜。 在前述之依照本發明之另一具體實施例之於半導體裝置 中形成穿隧氧化膜之方法中，步驟⑻另外還包括以下步驟 :先用一则：1 Β〇Ε浸泡L730至1，735秒將第-氧化膜之一 預確疋厚度去除，再使用一 Η2§〇4溶液將光阻圖案去除·最 後使用-SCM溶液進行清潔處理，以將有機成分或顆粒等 污染物去除。 在前述之依照本發明之另一具體實施例之於半導體裝置 中形成穿隧氧化臈之方法中，經過步驟⑻後所遺留之第— 氧化膜之厚度為17埃（A)至23埃（A)，且最好於步驟（c)中使 用一 5〇:1 HF溶液進行清洗以將第一氧化膜完全去除。 【實施方式】 本發明將以較佳具體實施例結合附圖之形式進行詳細説 明，圖中相似之元件符號係指相同或相似之元件。
圖4A至圖4D係依照本發明於半導體裝置中形成穿隨& 化膜之方法之截面示意圖。 I 麥照圖4A’為形成一高壓電晶體之閘氧化膜’在預處理 後之半導體基板11上形成—厚度為35〇埃（人）至6〇〇埃（f)的
O:\89\89720.DOC 1235434 第一氧化膜12 ’該第一氧化膜12係由75〇。(：至85〇。(：：溫度下 所生長之純氧化膜製成。 苓胲圖4B，於第一氧化膜12上形成一光阻圖案13，接著 進行圖案化使待形成的記憶體單元區及低壓電晶體區中之 第一氧化膜12曝露出來。 參照圖4C，於8代至14代溫度下完成一 1〇分鐘或較短時 間之殘渣清除製程，以清理圖案化光阻膜13，然後再將每 一曝露部分之第一氧化膜12之預確定厚度去除。再使用一 300.1 BOE次泡1，730至1，735秒，以將第一氧化膜12之一部 伤去除以及使用一 HJO4溶液將光阻膜13去除；最後使用 一 SC-1溶液進行清潔處理，以將有機成分或顆粒等污染物 完全去除。在此情形中，彳採用如下方法將有貞污染物去 除，即··在8(TC至10(TC高溫下進行H2S〇4/H2〇2反應以形成 Caro酸，然後再進行脫水和氧化處理。上述製程包括相繼 將第一氧化膜12及光阻膜13去除，以及進行清潔處理。 參照圖4D，先使用一 50:1 HF溶液執行一預清潔製程 FN40’，，以將殘留之第一氧化膜12完全去除，再於整個頂部 表面形成厚度為80埃（A)之第二氧化膜14。結果，於高壓電 晶體區中形成一含有第一氧化膜12及第二氧化膜14之厚閘 氧化膜，而於記憶體單元區及低壓電晶體區中則形成一含 有第二氧化膜14之穿隧氧化膜。 上述第二氧化膜14係用hvovN2氣體進行氧化、並使用 A氣進行熱處理而形成，其於高壓電晶體區中之厚度為肋 埃（人），而於記憶體單元區及低壓電晶體區中之厚度則為
O:\89\89720.DOC -9- 1235434 350埃（A)。同時，可於前述之預清潔過程中，將高壓電晶 體區中之第一氧化膜12之一預確定厚度去除。 如圖4C所示，依照本發明，·在去除第_氧化膜η及光阻 膜13之製程中，未將半導體基板u上之第—氧化膜^之一 預確定厚度——譬如17埃（人）至23埃（人）——去除。某於此 ’即能使由職造成之半導體基板u表面變粗及㈣降至 最小，且能防止由包含於光阻膜13中之殘留碳成分所導致 之污染。另外，由於第二氧化膜14係於殘留之第一氧化膜 12被完全去除之後即刻形成，故能提高穿隨氧化膜之載流 子遷移率以及擊穿性能。 ▲圖5係對依照本發明之快閃記憶體裝置實妹流應力測 捕性之結果曲線圖，從卞可看出恆流應力測試特性之均 勻性整體上得以改良，並顯示出優異特性，同時初始缺陷 比例亦得以降低。另外，如圖6所示，從中可看 緣部分僅有三個缺陷晶粒（die)。 如上所述，依照本發明，在形成高壓電晶體之閘氧化膜 之後’於去除記憶體單元區及低塵電晶體區中氧化膜、 程中’留下-預確定厚度之氧化膜，藉此防止在去除氧^ 臈及光阻膜之製程中所造成之基板表面變粗、以及因所吸 ”而導致之污染’進而可形成-具有優異薄膜品 質之穿隧氧化膜’藉此改良裝置成品之電特性。 、 儘管前面已參照較佳具體實施例對本發明進行 =明瞭’只要不背離本發明及後附申請專利範圍^精神 契乾圍’在此領域中擁有一般技藝者亦可對本發明進行各
O:\89\89720.DOC 1235434 種改動及修改。
【圖式簡單說明J 將結合附圖對本發明之前述方面及其他特性進行説明， 其中： 圖1A至圖1D係於半導體裝晉中带# 丁宁般衣置T形成穿隧氧化膜之傳統 方法之截面示意圖； 圖2及圖3係對依照傳統方法之快閃記憶體裝置實施十至流 應力測試之結果曲線圖； 圖4A至圖4D係依照本發明於半導體震置中形成穿隧氧 化膜之方法之截面示意圖； 圖5係對依照本發明之快閃記憶體裝置實施恆流應力測 試之結果曲線圖；以及 圖6係B曰圓之晶粒分佈及悝流應力測試結果之平面示 意圖。 【圖式代表符號說明】 1 半導體基板 2 第一氧化膜 3 光阻膜 4 第二氧化膜 11 半導體基板 12 第一氧化膜 13 光阻圖案 14 第二氧化膜
O:\89\89720.DOC -11 -

Claims (1)

1235434 拾、申請專利範圍： 1· 一種於半導體裝置中形成—穿随氧化膜之方法，其包括 以下步驟： . ⑷首先於半導體基板上形成―第—氧化膜，然後再形成 一使記憶體單元區及低壓電晶體區中之第一氧化膜 曝露之光阻圖案； (b)再將所曝露之第一氧化膜之預確定厚度及光阻圖案 相繼去除，以及 (0最後將遺留之第一氧化膜完全去除並於整個表面上 形成一第二氧化膜。 2.如申明專利圍第i項之方法，其中該第一氧化膜係於 750°C至850°C溫度下所生長之厚度為35〇埃（人）至6〇〇埃 (人）之純氧化膜。 3·如申a月專利耗圍第丄項之方法，其中步驟⑻另外還包括以 下步驟： 使用一则：1 B〇E浸泡U30至1，735秒，以將該第一氧 化膜之一預確定厚度去除； 再用H2SO心液將該光阻圖案去除；以及 」後再使用-SCM溶液進行清潔處理，以將有機成分 或顆粒等污染物去除。 4·如申請專利之方法，其中經過步驟⑻之後所遺 留之該第一氧化膜之厚度為17埃（人）至23埃（人）。 5·如申請專利範圍第1項之方法，其中在步驟⑷中係使用-50:1 HF溶液進行清洗以將該第一氧化膜去除。 O:\89\89720.DOC
TW092137146A 2003-06-27 2003-12-26 Method of forming tunnel oxide film in semiconductor device TWI235434B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2003-0042430A KR100470942B1 (ko) 2003-06-27 2003-06-27 반도체 소자의 터널산화막 형성 방법

Publications (2)

Publication Number Publication Date
TW200507109A TW200507109A (en) 2005-02-16
TWI235434B true TWI235434B (en) 2005-07-01

Family

ID=36637670

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092137146A TWI235434B (en) 2003-06-27 2003-12-26 Method of forming tunnel oxide film in semiconductor device

Country Status (4)

Country Link
US (1) US6858543B2 (zh)
JP (1) JP2005019944A (zh)
KR (1) KR100470942B1 (zh)
TW (1) TWI235434B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100520628B1 (ko) * 2003-12-26 2005-10-13 주식회사 하이닉스반도체 반도체 소자의 제조 방법
KR100567530B1 (ko) 2003-12-30 2006-04-03 주식회사 하이닉스반도체 반도체 소자의 산화막 형성 방법
CN103165437B (zh) * 2011-12-12 2016-06-29 无锡华润上华科技有限公司 一种栅氧刻蚀方法和多栅极制作方法
CN104658899B (zh) * 2013-11-22 2017-11-10 中芯国际集成电路制造(上海)有限公司 一种蚀刻栅极介电层的方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5316981A (en) * 1992-10-09 1994-05-31 Advanced Micro Devices, Inc. Method for achieving a high quality thin oxide using a sacrificial oxide anneal
US6146948A (en) * 1997-06-03 2000-11-14 Motorola Inc. Method for manufacturing a thin oxide for use in semiconductor integrated circuits
KR100273281B1 (ko) * 1998-02-27 2000-12-15 김영환 반도체 소자의 절연막 형성 방법
JPH11345884A (ja) * 1998-06-02 1999-12-14 Mitsubishi Electric Corp 半導体装置の製造方法およびその構造
US6573141B1 (en) * 1999-03-12 2003-06-03 Zilog, Inc. In-situ etch and pre-clean for high quality thin oxides
JP2001044292A (ja) * 1999-07-27 2001-02-16 Hitachi Ltd 半導体装置の製造方法および半導体装置
US6147008A (en) * 1999-11-19 2000-11-14 Chartered Semiconductor Manufacturing Ltd. Creation of multiple gate oxide with high thickness ratio in flash memory process
JP2002124578A (ja) * 2000-10-12 2002-04-26 Sony Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
KR20050003535A (ko) 2005-01-12
US6858543B2 (en) 2005-02-22
JP2005019944A (ja) 2005-01-20
US20040266110A1 (en) 2004-12-30
KR100470942B1 (ko) 2005-03-14
TW200507109A (en) 2005-02-16

Similar Documents

Publication Publication Date Title
JP2581268B2 (ja) 半導体基板の処理方法
TW391034B (en) Method of cleaning substrate
Águila Rodríguez et al. FTIR and photoluminescence studies of porous silicon layers oxidized in controlled water vapor conditions
KR950004449A (ko) 반도체 실리콘 웨이퍼 및 그 제조방법
JP2006191029A5 (zh)
TW200539330A (en) Ozone vapor clean method
JP2003531490A (ja) 窒化ケイ素フィルムを形成するための超薄オキシニトリドのｕｖ前処理法
JPH05198549A (ja) 半導体基板の製造方法
TWI235434B (en) Method of forming tunnel oxide film in semiconductor device
TW478062B (en) A method of surface treatment on the improvement of electrical properties for doped SiO2 films
JP2005539367A (ja) 半導体基盤の紫外線増強性酸窒化
JP2007534149A5 (zh)
KR20070093177A (ko) 하드 마스크 및 실리콘을 포함하는 포토레지스트 제거방법, 이를 이용한 패턴 형성 방법
TWI301639B (en) Method for suppressing oxide growth while performing wet cleaning sequence on semiconductor device on semiconductor substrate
JPH03116727A (ja) 半導体装置の製造方法
JP3611142B2 (ja) 張り合わせウェーハおよびその製造方法
JP2004031394A5 (zh)
JPH0719764B2 (ja) 表面洗浄方法
KR100935397B1 (ko) 접합 웨이퍼의 제조 방법
JP2996025B2 (ja) 絶縁膜の製造方法及びこれを用いた薄膜トランジスター素子
KR20030068354A (ko) 반도체 웨이퍼의 재생방법
JP2000068512A (ja) 半導体装置の製造方法
JPH04103173A (ja) 半導体装置の製造方法
JP4178227B2 (ja) 基板処理方法及び半導体装置の製造方法
JPH0218932A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees