TWI234231B - Reliable low-k interconnect structure with hybrid dielectric - Google Patents

Reliable low-k interconnect structure with hybrid dielectric Download PDF

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Publication number
TWI234231B
TWI234231B TW092130322A TW92130322A TWI234231B TW I234231 B TWI234231 B TW I234231B TW 092130322 A TW092130322 A TW 092130322A TW 92130322 A TW92130322 A TW 92130322A TW I234231 B TWI234231 B TW I234231B
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TW
Taiwan
Prior art keywords
layer
dielectric
dielectric layer
hard mask
hard
Prior art date
Application number
TW092130322A
Other languages
English (en)
Chinese (zh)
Other versions
TW200419714A (en
Inventor
John A Fitzsimmons
Stephen E Greco
Jia Lee
Stephen M Gates
Terry Spooner
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Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200419714A publication Critical patent/TW200419714A/zh
Application granted granted Critical
Publication of TWI234231B publication Critical patent/TWI234231B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
TW092130322A 2002-11-14 2003-10-30 Reliable low-k interconnect structure with hybrid dielectric TWI234231B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/294,139 US6917108B2 (en) 2002-11-14 2002-11-14 Reliable low-k interconnect structure with hybrid dielectric

Publications (2)

Publication Number Publication Date
TW200419714A TW200419714A (en) 2004-10-01
TWI234231B true TWI234231B (en) 2005-06-11

Family

ID=32296906

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092130322A TWI234231B (en) 2002-11-14 2003-10-30 Reliable low-k interconnect structure with hybrid dielectric

Country Status (8)

Country Link
US (2) US6917108B2 (https=)
EP (1) EP1561241A1 (https=)
JP (2) JP2006506806A (https=)
KR (1) KR100773003B1 (https=)
CN (1) CN1314101C (https=)
AU (1) AU2003279460A1 (https=)
TW (1) TWI234231B (https=)
WO (1) WO2004044978A1 (https=)

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Also Published As

Publication number Publication date
US7135398B2 (en) 2006-11-14
EP1561241A1 (en) 2005-08-10
US20050023693A1 (en) 2005-02-03
JP2006506806A (ja) 2006-02-23
JP2011061228A (ja) 2011-03-24
WO2004044978A1 (en) 2004-05-27
US6917108B2 (en) 2005-07-12
AU2003279460A1 (en) 2004-06-03
CN1314101C (zh) 2007-05-02
TW200419714A (en) 2004-10-01
KR20050074996A (ko) 2005-07-19
CN1711635A (zh) 2005-12-21
KR100773003B1 (ko) 2007-11-05
US20040094839A1 (en) 2004-05-20

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