CN1314101C - 具有混合电介质的可靠低k互连结构 - Google Patents

具有混合电介质的可靠低k互连结构 Download PDF

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Publication number
CN1314101C
CN1314101C CNB2003801033040A CN200380103304A CN1314101C CN 1314101 C CN1314101 C CN 1314101C CN B2003801033040 A CNB2003801033040 A CN B2003801033040A CN 200380103304 A CN200380103304 A CN 200380103304A CN 1314101 C CN1314101 C CN 1314101C
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CN
China
Prior art keywords
dielectric layer
layer
hard mask
mask layer
dielectric
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Expired - Lifetime
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CNB2003801033040A
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English (en)
Chinese (zh)
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CN1711635A (zh
Inventor
约翰·菲茨西蒙斯
斯蒂芬·格雷科
李加
斯蒂芬·盖茨
特里·斯普纳
马修·安格耶尔
哈彼·希克里
西奥尔多卢斯·斯坦戴尔特
格伦·比厄里
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Core Usa Second LLC
GlobalFoundries Inc
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International Business Machines Corp
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Publication of CN1711635A publication Critical patent/CN1711635A/zh
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Anticipated expiration legal-status Critical
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/074Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/081Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
CNB2003801033040A 2002-11-14 2003-11-07 具有混合电介质的可靠低k互连结构 Expired - Lifetime CN1314101C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/294,139 US6917108B2 (en) 2002-11-14 2002-11-14 Reliable low-k interconnect structure with hybrid dielectric
US10/294,139 2002-11-14

Publications (2)

Publication Number Publication Date
CN1711635A CN1711635A (zh) 2005-12-21
CN1314101C true CN1314101C (zh) 2007-05-02

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Family Applications (1)

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CNB2003801033040A Expired - Lifetime CN1314101C (zh) 2002-11-14 2003-11-07 具有混合电介质的可靠低k互连结构

Country Status (8)

Country Link
US (2) US6917108B2 (https=)
EP (1) EP1561241A1 (https=)
JP (2) JP2006506806A (https=)
KR (1) KR100773003B1 (https=)
CN (1) CN1314101C (https=)
AU (1) AU2003279460A1 (https=)
TW (1) TWI234231B (https=)
WO (1) WO2004044978A1 (https=)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7425346B2 (en) * 2001-02-26 2008-09-16 Dielectric Systems, Inc. Method for making hybrid dielectric film
JP2004146798A (ja) * 2002-09-30 2004-05-20 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP3898133B2 (ja) * 2003-01-14 2007-03-28 Necエレクトロニクス株式会社 SiCHN膜の成膜方法。
JP3715626B2 (ja) * 2003-01-17 2005-11-09 株式会社東芝 半導体装置の製造方法および半導体装置
JP4086673B2 (ja) * 2003-02-04 2008-05-14 Necエレクトロニクス株式会社 半導体装置及びその製造方法
US7081673B2 (en) 2003-04-17 2006-07-25 International Business Machines Corporation Multilayered cap barrier in microelectronic interconnect structures
US6919636B1 (en) * 2003-07-31 2005-07-19 Advanced Micro Devices, Inc. Interconnects with a dielectric sealant layer
US7199046B2 (en) * 2003-11-14 2007-04-03 Tokyo Electron Ltd. Structure comprising tunable anti-reflective coating and method of forming thereof
US20050130407A1 (en) * 2003-12-12 2005-06-16 Jui-Neng Tu Dual damascene process for forming a multi-layer low-k dielectric interconnect
US7224068B2 (en) * 2004-04-06 2007-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Stable metal structure with tungsten plug
US20060012014A1 (en) * 2004-07-15 2006-01-19 International Business Machines Corporation Reliability of low-k dielectric devices with energy dissipative layer
US20060027924A1 (en) * 2004-08-03 2006-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Metallization layers for crack prevention and reduced capacitance
US6974772B1 (en) * 2004-08-19 2005-12-13 Intel Corporation Integrated low-k hard mask
US7348672B2 (en) * 2005-07-07 2008-03-25 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnects with improved reliability
US7341941B2 (en) * 2005-08-19 2008-03-11 Texas Instruments Incorporated Methods to facilitate etch uniformity and selectivity
US7394154B2 (en) * 2005-09-13 2008-07-01 International Business Machines Corporation Embedded barrier for dielectric encapsulation
US20070059922A1 (en) * 2005-09-13 2007-03-15 International Business Machines Corporation Post-etch removal of fluorocarbon-based residues from a hybrid dielectric structure
KR20080072644A (ko) * 2005-11-03 2008-08-06 레드포인트 바이오 코포레이션 Trpm5 이온 채널용 고속 처리 스크리닝 검정
US20070155186A1 (en) * 2005-11-22 2007-07-05 International Business Machines Corporation OPTIMIZED SiCN CAPPING LAYER
US7338893B2 (en) * 2005-11-23 2008-03-04 Texas Instruments Incorporated Integration of pore sealing liner into dual-damascene methods and devices
US7358182B2 (en) * 2005-12-22 2008-04-15 International Business Machines Corporation Method of forming an interconnect structure
US20070152332A1 (en) * 2006-01-04 2007-07-05 International Business Machines Corporation Single or dual damascene via level wirings and/or devices, and methods of fabricating same
US7473636B2 (en) * 2006-01-12 2009-01-06 International Business Machines Corporation Method to improve time dependent dielectric breakdown
US20070278682A1 (en) * 2006-05-31 2007-12-06 Chung-Chi Ko Self-assembled mono-layer liner for cu/porous low-k interconnections
US7727885B2 (en) * 2006-08-29 2010-06-01 Texas Instruments Incorporated Reduction of punch-thru defects in damascene processing
US7466027B2 (en) * 2006-09-13 2008-12-16 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structures with surfaces roughness improving liner and methods for fabricating the same
US7749894B2 (en) * 2006-11-09 2010-07-06 Chartered Semiconductor Manufacturing Ltd. Integrated circuit processing system
US7723226B2 (en) * 2007-01-17 2010-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio
US7947565B2 (en) 2007-02-07 2011-05-24 United Microelectronics Corp. Forming method of porous low-k layer and interconnect process
US7485949B2 (en) * 2007-05-02 2009-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device
US7718525B2 (en) * 2007-06-29 2010-05-18 International Business Machines Corporation Metal interconnect forming methods and IC chip including metal interconnect
US20090032491A1 (en) * 2007-08-03 2009-02-05 International Business Machines Corporation Conductive element forming using sacrificial layer patterned to form dielectric layer
US20090176367A1 (en) * 2008-01-08 2009-07-09 Heidi Baks OPTIMIZED SiCN CAPPING LAYER
US8212337B2 (en) * 2008-01-10 2012-07-03 International Business Machines Corporation Advanced low k cap film formation process for nano electronic devices
US20090269507A1 (en) 2008-04-29 2009-10-29 Sang-Ho Yu Selective cobalt deposition on copper surfaces
US7863176B2 (en) * 2008-05-13 2011-01-04 Micron Technology, Inc. Low-resistance interconnects and methods of making same
JP2010003894A (ja) * 2008-06-20 2010-01-07 Nec Electronics Corp 半導体装置の製造方法及び半導体装置
US8189292B2 (en) * 2008-12-24 2012-05-29 Hitachi Global Storage Technologies Netherlands B.V. Method for manufacturing a magnetic write head having a write pole with a trailing edge taper using a Rieable hard mask
US8889235B2 (en) * 2009-05-13 2014-11-18 Air Products And Chemicals, Inc. Dielectric barrier deposition using nitrogen containing precursor
US8836127B2 (en) * 2009-11-19 2014-09-16 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect with flexible dielectric layer
JP2012190900A (ja) * 2011-03-09 2012-10-04 Sony Corp 半導体装置及びその製造方法
US8461683B2 (en) * 2011-04-01 2013-06-11 Intel Corporation Self-forming, self-aligned barriers for back-end interconnects and methods of making same
US8980740B2 (en) 2013-03-06 2015-03-17 Globalfoundries Inc. Barrier layer conformality in copper interconnects
US9385086B2 (en) * 2013-12-10 2016-07-05 Taiwan Semiconductor Manufacturing Co., Ltd. Bi-layer hard mask for robust metallization profile
US20170092753A1 (en) 2015-09-29 2017-03-30 Infineon Technologies Austria Ag Water and Ion Barrier for III-V Semiconductor Devices
US9905456B1 (en) * 2016-09-26 2018-02-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10256191B2 (en) 2017-01-23 2019-04-09 International Business Machines Corporation Hybrid dielectric scheme for varying liner thickness and manganese concentration
US11217481B2 (en) * 2019-11-08 2022-01-04 International Business Machines Corporation Fully aligned top vias
US11244854B2 (en) 2020-03-24 2022-02-08 International Business Machines Corporation Dual damascene fully aligned via in interconnects
KR102881251B1 (ko) 2021-01-11 2025-11-04 삼성전자주식회사 반도체 장치 및 이의 제조 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1120822A1 (en) * 1998-09-02 2001-08-01 Tokyo Electron Limited Method of manufacturing semiconductor device
US6380091B1 (en) * 1999-01-27 2002-04-30 Advanced Micro Devices, Inc. Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer
WO2002083327A1 (en) * 2001-04-16 2002-10-24 Honeywell International Inc. Layered stacks and methods of production thereof
US20020164889A1 (en) * 2001-05-02 2002-11-07 Cheng-Yuan Tsai Method for improving adhesion of low k materials with adjacent layer

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6265780B1 (en) 1998-12-01 2001-07-24 United Microelectronics Corp. Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit
US6245662B1 (en) 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
US6265779B1 (en) * 1998-08-11 2001-07-24 International Business Machines Corporation Method and material for integration of fuorine-containing low-k dielectrics
US6159842A (en) 1999-01-11 2000-12-12 Taiwan Semiconductor Manufacturing Company Method for fabricating a hybrid low-dielectric-constant intermetal dielectric (IMD) layer with improved reliability for multilevel interconnections
US6187663B1 (en) 1999-01-19 2001-02-13 Taiwan Semiconductor Manufacturing Company Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials
US6312793B1 (en) * 1999-05-26 2001-11-06 International Business Machines Corporation Multiphase low dielectric constant material
US6770975B2 (en) 1999-06-09 2004-08-03 Alliedsignal Inc. Integrated circuits with multiple low dielectric-constant inter-metal dielectrics
WO2000079586A1 (en) * 1999-06-24 2000-12-28 Hitachi, Ltd. Production method for semiconductor integrated circuit device and semiconductor integrated circuit device
US6319814B1 (en) * 1999-10-12 2001-11-20 United Microelectronics Corp. Method of fabricating dual damascene
US6406994B1 (en) * 1999-12-03 2002-06-18 Chartered Semiconductor Manufacturing Ltd. Triple-layered low dielectric constant dielectric dual damascene approach
FR2802336B1 (fr) * 1999-12-13 2002-03-01 St Microelectronics Sa Structure d'interconnexions de type damascene et son procede de realisation
US6486557B1 (en) 2000-02-29 2002-11-26 International Business Machines Corporation Hybrid dielectric structure for improving the stiffness of back end of the line structures
US6362091B1 (en) 2000-03-14 2002-03-26 Intel Corporation Method for making a semiconductor device having a low-k dielectric layer
US6440878B1 (en) * 2000-04-03 2002-08-27 Sharp Laboratories Of America, Inc. Method to enhance the adhesion of silicon nitride to low-k fluorinated amorphous carbon using a silicon carbide adhesion promoter layer
JP2001338978A (ja) 2000-05-25 2001-12-07 Hitachi Ltd 半導体装置及びその製造方法
US6358842B1 (en) 2000-08-07 2002-03-19 Chartered Semiconductor Manufacturing Ltd. Method to form damascene interconnects with sidewall passivation to protect organic dielectrics
US7115531B2 (en) 2000-08-21 2006-10-03 Dow Global Technologies Inc. Organosilicate resins as hardmasks for organic polymer dielectrics in fabrication of microelectronic devices
US6451683B1 (en) 2000-08-28 2002-09-17 Micron Technology, Inc. Damascene structure and method of making
US6395632B1 (en) 2000-08-31 2002-05-28 Micron Technology, Inc. Etch stop in damascene interconnect structure and method of making
US6472306B1 (en) * 2000-09-05 2002-10-29 Industrial Technology Research Institute Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer
US6380084B1 (en) * 2000-10-02 2002-04-30 Chartered Semiconductor Manufacturing Inc. Method to form high performance copper damascene interconnects by de-coupling via and metal line filling
WO2002043119A2 (en) * 2000-10-25 2002-05-30 International Business Machines Corporation An ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device, a method for fabricating the same, and an electronic device containing the same
TW468241B (en) * 2000-11-14 2001-12-11 United Microelectronics Corp Method to improve adhesion of dielectric material of semiconductor
JP2002164428A (ja) * 2000-11-29 2002-06-07 Hitachi Ltd 半導体装置およびその製造方法
US6451712B1 (en) * 2000-12-18 2002-09-17 International Business Machines Corporation Method for forming a porous dielectric material layer in a semiconductor device and device formed
US20020137323A1 (en) * 2001-01-03 2002-09-26 Loboda Mark Jon Metal ion diffusion barrier layers
US6383920B1 (en) 2001-01-10 2002-05-07 International Business Machines Corporation Process of enclosing via for improved reliability in dual damascene interconnects
US6677680B2 (en) * 2001-02-28 2004-01-13 International Business Machines Corporation Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials
US6603204B2 (en) * 2001-02-28 2003-08-05 International Business Machines Corporation Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics
US6710450B2 (en) * 2001-02-28 2004-03-23 International Business Machines Corporation Interconnect structure with precise conductor resistance and method to form same
KR100416596B1 (ko) * 2001-05-10 2004-02-05 삼성전자주식회사 반도체 소자의 연결 배선 형성 방법
US6391757B1 (en) 2001-06-06 2002-05-21 United Microelectronics Corp. Dual damascene process
US6798043B2 (en) 2001-06-28 2004-09-28 Agere Systems, Inc. Structure and method for isolating porous low-k dielectric films
US6879046B2 (en) * 2001-06-28 2005-04-12 Agere Systems Inc. Split barrier layer including nitrogen-containing portion and oxygen-containing portion
JP4152619B2 (ja) * 2001-11-14 2008-09-17 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US20030134499A1 (en) * 2002-01-15 2003-07-17 International Business Machines Corporation Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof
US6806203B2 (en) * 2002-03-18 2004-10-19 Applied Materials Inc. Method of forming a dual damascene structure using an amorphous silicon hard mask
JP4340040B2 (ja) * 2002-03-28 2009-10-07 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP3657921B2 (ja) * 2002-04-26 2005-06-08 株式会社東芝 半導体装置とその製造方法
US6764774B2 (en) * 2002-06-19 2004-07-20 International Business Machines Corporation Structures with improved adhesion to Si and C containing dielectrics and method for preparing the same
US6867125B2 (en) * 2002-09-26 2005-03-15 Intel Corporation Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material
US7023093B2 (en) * 2002-10-24 2006-04-04 International Business Machines Corporation Very low effective dielectric constant interconnect Structures and methods for fabricating the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1120822A1 (en) * 1998-09-02 2001-08-01 Tokyo Electron Limited Method of manufacturing semiconductor device
US6380091B1 (en) * 1999-01-27 2002-04-30 Advanced Micro Devices, Inc. Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer
WO2002083327A1 (en) * 2001-04-16 2002-10-24 Honeywell International Inc. Layered stacks and methods of production thereof
US20020164889A1 (en) * 2001-05-02 2002-11-07 Cheng-Yuan Tsai Method for improving adhesion of low k materials with adjacent layer

Also Published As

Publication number Publication date
US7135398B2 (en) 2006-11-14
EP1561241A1 (en) 2005-08-10
TWI234231B (en) 2005-06-11
US20050023693A1 (en) 2005-02-03
JP2006506806A (ja) 2006-02-23
JP2011061228A (ja) 2011-03-24
WO2004044978A1 (en) 2004-05-27
US6917108B2 (en) 2005-07-12
AU2003279460A1 (en) 2004-06-03
TW200419714A (en) 2004-10-01
KR20050074996A (ko) 2005-07-19
CN1711635A (zh) 2005-12-21
KR100773003B1 (ko) 2007-11-05
US20040094839A1 (en) 2004-05-20

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