TWI230433B - Isolation structures for imposing stress patterns - Google Patents

Isolation structures for imposing stress patterns Download PDF

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TWI230433B
TWI230433B TW092129908A TW92129908A TWI230433B TW I230433 B TWI230433 B TW I230433B TW 092129908 A TW092129908 A TW 092129908A TW 92129908 A TW92129908 A TW 92129908A TW I230433 B TWI230433 B TW I230433B
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elements
isolation
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effect transistor
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TW200415746A (en
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Dureseti Chidambarrao
Omer H Dokumaci
Bruce B Doris
Jack A Mandelman
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Ibm
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

1230433 五、發明說明（1) " ---- 申請相關參考 美國專利申請第^__號名稱為” Stress
Inducing Spacers”，係讓渡給相同之受讓人，於某方面其 包含與本申請相關的内容。上述專利申請於此係做為參… 考。 多 【發明所屬之技術領域】 本發明係關於半導體元件創新的製造方法，用以增進 元件的性能，以及關於所形成之獨特而具有高性能的=件 構造。特別是，本發明在元件製程中，藉由改變元件基板_ 結構之拉張力與壓縮力，以增進場效電晶體（FET)元件之電 荷遷移速率。 在半導體元件設計的領域之中，習知調控元件基板内 的機械應力，可改變元件的性能。各別的應力張量分量 (stress tensor component )會對P 型場效電晶體（pfet)以 及N型場效電晶體（NFET)的元件行為造成不同的影響。習知 利用應力以提升性能的技術，傾向著眼於一種或其他種與 貫際性能表現環境無關的元件，例如一 I C晶片。為了使在· I C晶片中的P型場效電晶體以及N型場效電晶體之性能最大 化，應力分量需要被不相同地但同時地設計與應用。本發 明展現了製程方法以及所產生之結構，其利用了適當的應 力場，可增進單一元件以及位於同一基板上之至少二元件 的性能。
1230433 五、發明說明（2) 【先前技術】
Hameda 等人，在 IEEE Transactions on Electron Devices, ν〇1·38 No. 4(1991，四月），標題為「A New Aspect of Mechanical Stress Effects in Scaled MOS Devices」的文獻中，發表了關於重力引起橫方向與縱方向 之壓縮應力與拉伸應力，並具有跨導偏差 (Transconductance deviation)的數據資料。在一 P 型場效 電晶體（PFET)中，縱向應用單軸壓縮應力將與在一N型場& 電晶體（NFET)中所得到效果相反。如此的實驗數據可被如響 此解釋：假若應用平面雙轴拉伸應力（in-plane biaxial tensile stress)，N型場效電晶體（NFET)之性能將會是應 用單軸拉伸應力的兩倍，而P型場效電晶體（PFET)之性能則 會因為橫向與縱向的拉伸應力相互抵消而沒有改變。 在2001 年VLSI Technology Digest of Technical
Papers研討會上，iiiin等人顯示了利用具有平面雙軸拉伸應 力的應變矽（strained Si)，可使N型場效電晶體（NFET)的 電子遷移率提升百分之七十。習知技術中，應用機械應力_ 以增進元件性能的方法尚無法同時使p型場效電晶體（PFET) 以及N型場效電晶體（NFET)之性能提升。再者，習知技術中 從未提及任何具體可行的元件結構或製程方法。 【發明内容】
4IBM0383TW.ptd 第8頁 1230433
(二維的、月揭示了數種方法與結構，係關於應用平面雙軸 面一壓縮縱應力於n型場效電晶體（nfet)，並同時應用平 卜卜、 σ μ力及拉伸橫向應力於P型場效電晶體（P F E T )。 本發明關於各別元件製造之方法與結構也是獨特 丘，^發明之方法與結構的優點在於該等方法與結構提 供愛目=於單軸應力兩倍之元件性能改善。本發明之另一 二j係提供了同時在同一基板上之p型場效電晶體以及N型 電晶體的製造方法，其中每一元件係經由設計，以利 Z產生應力的隔離材料來增加性能表現。其他優點為經 μ力產生之溝渠隔離結構，可提供具強化性能的個別元_ 件之結構及製造方法。 本發明之一目的在於提供Ν型場效電晶體、ρ型場效電 晶體，以及Ν型場效電晶體及Ρ型場效電晶體兩者同時之元 件性肖b的提升。本發明之另一目的在於使本發明可經濟地 輕易整合於現行之製程，僅藉由增加一單一光罩程序，而 顯著的提升元件性能。本發明之另一目的在於在整體矽 (bulk silicon)、絕緣層覆矽（s〇I)以及應變矽（straine(i silicon)等結構，可製作應用本發明。 · 本發明包含有P型場效電晶體以及N型場效電晶體的溝 渠隔離結構（trench isolation structure) 型場效電晶 體的一隔離區中具有一第一型隔離材料，其係對於N型場效 電晶體之縱向以及橫向皆施予一第一機械應力。ρ型場效電
4IBM0383TW.ptd 第9頁 1230433 五、發明說明（4) 曰曰體的 弟 隔離區則在P型場效電晶體的橫向施以機械應 2。P型場效電晶體的一第二隔離區，其係對於p型場效電 晶體之縱向施予另一型機械應力。該等隔離區根據所需之 機械應力’可包含相似或不同的隔離材料。一般而言，該 等機械應力為拉伸應力或壓縮應力。 以另 一 型場效電晶 體元件之側 一隔離區則 溝渠隔離區 场效電晶體 件橫向施予 於該等隔離 縮型機械應 區之中。於 中，其係氧 到膨脹，而 力。因此， component) 方面而言，本發明包含有p型場效電晶體以及N 體元件的製作方法。此觀點涉及在N型場效電晶 邊（sides)以及末端（ends)的隔離區之形成 形成於P型場效電晶體元件之側邊。另一（第一 形成於P型場效電晶體元件之末端。可對於N型 凡件橫向與縱向兩方向，以及p型場效電晶體元 一第一型機械應力的隔離材料，將被選來使用 區之中。可對於P型場效電晶體之縱向施予一壓 力的隔離材料，將被選來使用於第三溝渠隔離 另種產生應力向$(stress vector)的方法 化第二溝渠隔離區的至少部分隔離材料，以達 對於P型場效電晶體之縱向施予一壓縮機械應 視，否藉由氧化以產生應力分量（stress ’每一元件可選擇相同或不同之隔離材料。 以另一方面而言，本發明 極區以及源極區。基板在每一 通道區。一閘極區鄰接於通道 包含在一基板上所形成之汲 沒極區與源極區之間具有一 區以控制通道區之導電性。
4IBM0383TW.ptd
1230433
用以產生應力之隔離材料鄰接於汲極區與源極區所選擇之 侧邊，以將應力至少分派予在基板的汲極區以及源極區 伸應力或壓縮應力）外之通道區。 關於本發明之優點與精神可以藉由以下的發明詳、求 所附圖式得到進一步的瞭解。 【實施方式】 本發明最佳具體實施例 本發明係關於使用本質上應力產生材料以填塞隔離修 區，特別是淺溝渠隔離（shaii〇w trench is〇iati()n， ST I ):以將所選擇的橫向以及縱向應力分量分配至基板之 主動元件區。舉例而言，使用一本質為拉伸的應力產生材 料即可在基板中產生一拉伸狀態之應力，而使用一本質為 壓細的應力產生材料即可在基板中產生壓縮。為了將不同 的應力分配至各元件上，本發明採用可提供不同本質應力 的沈積薄膜。舉例而言，四乙基正石夕酸鹽（T E Q S， tetraethy lorthosi 1 icate)習知為拉伸性，因其在退火過 程之中會密實化因而產生收縮，藉此施予鄰接之基板一拉_ 伸應力。尚密度電漿氧化物（HDP oxide)習知為本質壓縮。 本發明在此處的重點係為將兩種不同本質的應力產生結構 整合鄰接於P型場效電晶體（PFET)以及N型場效電晶體 (NFET)的結構，或者個別地，使一或兩種應力產生結構鄰 接於該些元件的其中之一。關於具有拉伸本質應力的TE〇s
4IBM0383TW.ptd 第11頁 1230433
以及具有 驟’係繪示於圖三至圖七且萄 度電漿（HDP)的整合製程 述於後續之詳細說明。
本 程，可 量的襯 程在淺 (0 2 )滲 作用。 用會造 制性地 質拉伸 及縱向 該等方 發明之方法包令τ ^ 使氮切(SiN)作為—Ν :::的淺溝渠隔離(STI)製作流 層，而僅作為P型^丈^效電晶體橫向以及縱向分 溝渠隔離填塞物中/入电晶體橫向分量的概層。此製 入，而氛化石夕j 了丽，因為麵可使氧 因此，僅P型場效曰電曰防止在矽/TE0S邊界產生氧化 成Si/TE0S邊界^^阳體的縱向分量會被氧化，此% 增加P型場效電曰、二：化的量以及時間可被用來, 之薄膜，而氮化曰曰石夕襯/的壓縮應力。由於丽係本 分量及P型場效電晶體曰之用於效電象 向上會提供-拉伸應力k向…所以丽在上述 結構
標準的淺溝渠隔離製程 (氮化概層為選擇性使用）以 之用。在本發明之中，不同 圍場效電晶體元件的基板區 控制分派至鄰接之場效電晶 通常利用單一種類的氧化薄膜 及一隔離填充材料以作為隔離 種類的氧化薄膜被選用置於包 域中。藉著控制製程條件，可 體元件的應力型式。 P型％效電晶體以及N4 θ 量或圖宰，以；^ Λ i琢效電日日體萵要不同的應力向 里4 131木 Λ曰加電荷遷移率〇 P雜奸+3L日I +人 秒午離材枓則適合用來微調
4IBM0383TW.ptd 第12頁 1230433
以產生元件所需之應力圖案 波功率（RF power)，某些材 -周。TE0S不易藉由製程控制 於鬆散，然而當退火密實時 種型式的本質應力——拉伸 好調控，其不需密實程序（$ 力0 。藉由製程控制，例如無線電 料則可用來進一步地進行微 進行微調，因為其材料結構過 會產生收縮，因此可用來提供 應力。南密度電漿則較TE〇s較 ^處理）且一般提供本質壓縮應 % 向 力 圖一係為本發明較佳實施例示意圖。自N型場效電晶 外延伸之箭號表示在元件縱向以及橫向產生之拉伸應 。如以下將進一步描述，TE0S可用於本發明方法，以提 供N型場效電晶體之該些應力。TE0S亦可應用於鄰接或相鄰 的P型場效電晶體的橫向側邊，以對p型場效電晶體產生橫 向拉伸向量。高密度電漿則鄰接於P型場效電晶體縱向側/ 邊’以對P型场效電晶體產生縱向壓縮向量。 在另一實施例中，最終結構包含於縱向及橫向兩方向 部分均具有氮化石夕（S i N )襯層之N型場效電晶體、以及於橫 向部分具有氮化矽襯層且於縱向部分具有氧化的矽但無氮_ 化矽襯層之P型場效電晶體。數個製作流程可產生此最終結 構0 與元件區域相關之高密度電漿以及TE0S應力產生區域 的位置亦繪示於圖六。如圖六所示，TE0S包圍著N型場效電
4IBM0383TW.ptd 第13頁 1230433
五、發明說明（9) 高密度電漿與TE0S 兩種較佳之溝渠隔離材料—高密度電 =斤:同。高密度電聚與丽的沈積過程：了 ^ 之雷將it沈積係使用化學氣相沈積法（CM)。高密度電漿 電漿ϋ =為—方向性製程’其中因為在電漿中高密度 产電將、六：Ϊ粒子所組成’因此材料係由電場加速。高密 ϋ = Γ具有本f壓縮應力’且密實（densify)視為 但;份，在沈積後則需要密實退火程序，· 予，：Ξ i ί應力可藉由應力產生材料的收縮/膨脹而施 =應力產生材料生長於鄰接基板時可本質地施 電/具有内建的本f應力（buiit—in —ic =:::二熱時產生收縮。以下產生應力的基本機制 論上的細節。 因此’不再進一步描述這些機構的理 製程 讀 離，包圍場效電晶體元件的隔 罩係用以在基板内形成的利；；二； 方法，將_與高密度電漿丄合
4IBM0383TW.ptd 第15頁

Claims (1)

1230433 六、申請專利範圍 1 · 一種作為形成於一基板之複數個元件的隔離結構，該複 數個元件中之每一個具有一縱向及一橫向，該結構包含·· 一第一隔離區，用於該複數個元件之一第一元件，該 第一隔離區於其中具有一第一隔離材料，其應用一第一型 機械應力於該複數個元件之該第一元件之該縱向且及該橫 向0 2 ·如申請專利範圍第1項所述之隔離結構，進一步包含： 一第二隔離區，用於該複數個元件之一第二元件，該 第二隔離區於其中具有該第一隔離材料，其應用該第一型
機械應力於該複數個元件之該第二元件之該橫向；以及 一第三隔離區，用於該複數個元件之該第二元件，該 第三隔離區於其中具有一第二隔離材料，其應用一第二型 機械應力於該複數個元件之該第二元件之該縱向。 3 ·如申請專利範圍第2項所述之隔離結構，其中該複數個元 件之該第一元件係為一N型場效電晶體（NFET)，且該複數個 元件之該第二元件係為一p型場效電晶體（pFET)。 4·如申請專利範圍第3項所述之隔離結構，其中該第一隔^ 材料係為四乙基正矽酸鹽（TE〇s)，且該第二隔離材 高密度電漿（HDP)。 句 5 · —種於一基板形成複數個元件的方法，該複數個元件之
1230433 縱向，以及末端（ends)延 ~、申請專利範圍 每一個具有側邊（s i d e S )延， 伸於一橫向，該方法包含： 在該複數個元件之一第一元件之該側邊，形成一第一 隔離區； 在該禝數個兀件之該第一元件之該末端，形成一第二 隔離區；以及 提供一第一隔離材料於該第一隔離區中，以應用一第 二型機械應力於該複數個元件之該第一元件之該橫向；以 及 提供一第二隔離材料於該第二隔離中， I 二型機械應力於該複數個元件之該第一元：之該縱向。 6·如申請專利範圍第5項所述之方法， 在該複數個元件之一楚—-从 ^ 形成一第三隔離區；以及…件之該側邊以及該末端， 之該縱向且及 一型‘二二^於3離材料於該第三隔離區中，以應用該第 該ί: 該複數個元件之該第二元 7該圍Λ:項所述之方法，其中該複數個元件之· 之該第二元件係為—晶體(PFET)，且該複數個元件 N型~效電晶體（NFET)。 項所述之方法，其中該第一隔離材 8 ·如申請專利範圍第7 料 _ 4IBM0383TW.ptd 第26頁 1230433
係為四乙基正矽酸鹽（TE〇s)， 度電漿（HDP)。 此該第二隔離材料係為高密
9 · 一種於一基板形成複數個元 每一個具有側邊延伸於一縱向 該方法包含： 在該複數個元件之一第 形成一第一隔離區； 提供一第一隔離材料於該 一型機械應力於該複數個元件 及 件的方法，該複數個元件之 ’以及末端延伸於一橫向， 711件之該側邊以及該末端 第—隔離區中，以應用一第 之該第一元件之該橫向；以 氧化在該複數個元件之該第一元件之該末端之該第一 隔離材料的至少一部份，以致使該第一隔離材料應用一第 二型機械應力於該複數個元件之該第一元件之該縱向。 1 0 ·如申請專利範圍第9項所述之方法，進一步包含： 在該複數個元件之一第二元件之該侧邊以及該末端’ 形成一第二隔離區；以及 提供該第一隔離材料於該第二隔離區中，以應用該第 一型機械應力於該複數個元件之該第二元件之該縱向區且 及該横向。 11 l ^ ^ ^ 1之方法，其中該形成第一隔 1 1 ·如申清專利範圍第1 0項所述之刀 離區之步驟包含：
4IBM0383TW.ptd
1230433 六、申請專利範圍 沈積一氧化阻擋層（〇xidati〇n blocking layer)於該 複數個元件之該第一元件以及該第二元件之上；以及 僅（ο η 1 y)移除超出該複數個元件之該第一元件之該末 端之該氧化阻擋層。 1 2 ·如申請專利範圍第1 0項所述之方法，其中該氧化該第一 隔離材料的至少一部份的步驟包含： 同時氧化該複數個元件之該第一元件之該末端的至少 一部份。 • 1 3 ·如申請專利範圍第丨〇項所述之方法，其中該複數個元件 之該第一元件係為一P型場效電晶體（PFET)，且該複數個元 件之該第二元件係為一N型場效電晶體（NFET)。 1 4 · 一種作為形成於一基板之複數個元件的隔離結構，該複 數個元件之每一個具有側邊延伸於一縱向及末端延伸於一 橫向，該結構包含： 一第一隔離區，鄰接該複數個元件之一第一元件之至 少一側邊以及至少一末端，該第一隔離區於其中具有一第鲁 一隔離材料，該第一隔離材料鄰接該複數個元件之該第一 元件之該至少側邊，以應用一第一型機械應力於該複數個 元件之該第一元件之該橫向；以及 该第一隔離材料的一氧化部分（oxidized portion)鄰 接該複數個元件之該第一元件之該至少一末端，以應用一
第28頁 1230433 六、申請專利範圍 第二型機械應力於該複數個元件之該弟一元件之該縱向。 1 5 ·如申請專利範圍第1 4項所述之隔離結構，進一步包含： 一第二隔離區，用於該複數個元件之一第二元件，該 第二隔離區於其中具有該第〆隔離材料，其應用該第一型 機械應力於該複數個元件之該第二元件之該縱向且及該橫 向。 1 6 ·如申請專利範圍第1 5項所述之隔離結構，其中該複數1 元件之該第一元件係為一p梨場效電晶體（PFET)，且該複 個元件之該第二元件係為〆N蜇場效電晶體（NFET)。
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US20040113174A1 (en) 2004-06-17
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