TWI228813B - Method for manufacturing circuit device - Google Patents

Method for manufacturing circuit device Download PDF

Info

Publication number
TWI228813B
TWI228813B TW092122219A TW92122219A TWI228813B TW I228813 B TWI228813 B TW I228813B TW 092122219 A TW092122219 A TW 092122219A TW 92122219 A TW92122219 A TW 92122219A TW I228813 B TWI228813 B TW I228813B
Authority
TW
Taiwan
Prior art keywords
conductive film
conductive
circuit device
layer
item
Prior art date
Application number
TW092122219A
Other languages
English (en)
Other versions
TW200408097A (en
Inventor
Yusuke Igarashi
Noriaki Sakamoto
Original Assignee
Sanyo Electric Co
Kanto Sanyo Semiconductors Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co, Kanto Sanyo Semiconductors Co filed Critical Sanyo Electric Co
Publication of TW200408097A publication Critical patent/TW200408097A/zh
Application granted granted Critical
Publication of TWI228813B publication Critical patent/TWI228813B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48233—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a potential ring of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48639—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01011—Sodium [Na]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01059—Praseodymium [Pr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H05K1/187—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0376—Etching temporary metallic carrier substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Electroplating Methods And Accessories (AREA)
  • ing And Chemical Polishing (AREA)

Description

1228813 玖、發明說明 [發明所屬之技術領域] 本發明乃關於電路裝置之製造方法，尤其是關於在蝕 刻製程當中，採用了介以第3導電膜為阻障層來層疊之2 枚的導電膜之薄型的電路裝置之製造方法。 [先前技術] 近年來，於1C封裝當中，用於攜帶型機器或小型· 咼密度封裝機器之進展迅速，而使以往的I c封裝及其封裝 概念產生極大變化。關於以往的半導體裝置之技術，例如 有採用可撓式薄板之聚亞醯胺（Polyimide)樹脂薄板，來做 為絕緣樹脂薄板之一例之半導體裝置（例如可參照專利文 獻1) 〇 第16圖至第18圖為採用可撓式薄板5〇來做為内插 板（Interposer)基板之圖式。而於各個圖式的上方所顯示的 圖面為平面圖，於各個圖式的下方所顯示的圖面為A_ A線 的剖面圖。 首先於第16圖所示之可撓式薄板5()上，備有介以黏 著劑來貼合的銅箔佈線圖案（pattern)5 1。於此銅箔佈線圖 案5 1备中，雖然裝设的半導體元件乃因電晶體、，而使 佈線圖案有所不同，但是一般而言，均形成了銲墊（B〇nding Pad)51A及轉接島（Island)51B。此外，符號52為用於從可 撓式溥板5 0的内側取出電極的開口部，而上述銅箔佈線圖 案5 1從此開口部露出。 接下來，如第17圖所示般，此可撓式薄板5〇被運送 314953 5 1228813 至銲片機（Die Bonder)，並裝設半導體元件53。之後，此 了撓式薄板50被運送至銲線機（wire Bonder)，並以金屬細 線54,與銲墊51A及半導體元件53的襯墊進行電性連接。 隶後’如第1 8圖（A)所示般，於可撓式薄板50的表面 上设置密封樹脂5 5來加以密封。在此，進行轉注模壓成形 (Transfer Mold)來包覆住銲墊51八及轉接島51B、及半導 體元件53、及金屬細線54。 之後，如第18圖（B)所示般，設置銲錫或是錫球等連 接裝置56，藉由通過回銲爐，介以開口部52來形成與銲 塾51A融合之球狀銲錫56。並且於可撓式薄板5()上形成 矩陣狀的半導體元件53，因此如第丨7圖所示般，進行切 割而個別分離。 此外’第18圖（C)所示之剖面圖，於可撓式薄板5〇的 兩面上，形成51A及51D來做為電極。一般而言，此可撓 式薄板50乃在兩面上進行佈線圖案化之後再由製造商處 來供應。 【專利文獻1】 曰本特開200(M33 678號公報（第5頁，第2圖）。 [發明内容] 採用上述了撓式薄板50的半導體裝置，因為未採用 眾所皆知之金屬弓丨線架，因此具有可實現極小型且為薄型 的封裒構這之優點，然而實際上僅以設置於可撓式薄板$ 〇 勺表面之1層的鋼箔佈線圖案5 1來進行配線。這是因為可 撓式薄板較為柔軟，於導電膜的佈線圖案形成前後會產生 314953 6 1228813 扭曲，於層疊的層間的位置偏移較大因而於夕 造當中會具有不適用之問題點。 、夕層配線構 ^為了實現多層配線構造’有必要增強用 正斜之支禮強度，因此，有必要使可撓式薄板 戸反的 到約200 " m之厚度，而無法達到薄型化的目的。、予度大 再者，於製造方法當中，於上述製造裝 片機、薛線機、轉注模壓成形裝置、回鲜爐等^如於銲 可撓式薄板5〇,並裝設於验炎亚么 田 運送 之部分上。 又於稱為千台⑽㈣或是承載台⑽le: =;做為可撓式薄板5"基礎之絕緣樹 右…"〇心左右的話’則形成於表面之 ： ::的厚度亦薄到9至35 一情況下，則存在如第= 所不般之鍾曲，其運送困難度增高，此外對平 圖 =裝設性亦惡化。這可視為絕緣樹脂本身非常薄：造： 』曲，以及銅落佈線圖案51與絕緣樹 的差所導致之翹曲。 ]旳熱恥脹係數 ==可能是因為開口部52的部分於模 =，上方來因此產生將㈣5ϊα的周圍往上龜曲 的力置，而使銲墊51Α的黏著性惡化。 =卜=成可挽式薄板5〇的樹脂材料本身不具備可 ^::戈疋為了提高熱傳導性而加入添加材料 =式薄板變硬。於此狀態下，一旦於輝線機内進行谭接 的活’則有可能於焊接的部分上產生裂開。此外，於轉、主 竭形之際’與模具抵接的部分上有可能產生裂開。此 3]4953 7 1228813 情形若是在如第丨Q同^ — 回斤不身又之翹曲的情況下，則更為顯 著0 :目前為止所說明的可撓式薄板5。，乃未於内側形成 …卜旦疋亦可如第18圖(C)所示般，於可撓式薄板50 =:形成電極51D。此時，因為電極51D與上述製造 r:t，或是與此製造裝置之間的運送機構之運送面抵 =因此有可能於電極51D的内側產生刮 ;在此到傷的狀態下形成電極，因此之後-旦加埶的話， 有可能使電極51D本身產生裂開之問題點，以及在、二 板進行銲錫連拯 u械 场運接之際，產生銲錫浸入性降低的問題。 每，此外…旦於可撓式薄板50的内側設置電極51D的 疒面i:轉注模壓成形之際’亦有可能產生無法與平台進 成可 於此清况下，如上述般以堅硬材料來構 極5 I/的用反5〇的活則因為電極51D成為支點而使電 產生往下方加壓，所以可能於可撓式薄板50 生I開的問題點。 2解決上述課題，本發明者乃提出，採用將較薄的 導電膜及較厚的第2導電膜介以第3導 層豎板之提案。 曰且< 做為本發明之用以解決課題之手段，第i，本發明之 電路裝置之;皮古、土 、 ^ 、运方法的特徵為，具備用於準備將第i導電 導電膜介以第3導電膜來層疊之層疊板之製程； 電L二所希望的圖案來蝕刻上述第1導電膜，來形成導 泉層之製程；及採用上述導電配線層做為光罩，來去 314953 8 Ϊ228813 除上述第 導電膜之製程 '〜取你，从从、、、〇略/日+巴復，因去除上 述第3導電膜而露出之第2導電膜表面部、及上述導電配 線層、及第3導電膜的端面之製程；及藉由去除上述絕緣 層的一部分，來局部露出上述導電配線層之製程；及於上 述絕緣層上固定半導體元件，並電性連接上述半導體元件 及上述導電配線層之製程；及以密封樹脂層包覆上述半 體元件之製程；及去除上述第2導電膜，並使上述第 電膜在内側露出之製程；及於上述第3導電膜的所希 區域上，形成外部電極之製程。 _:上2述ir:之電路裝置之製造方法的特徵為，藉由 層：以*電膜為止，來精密地形成上述導電配線 第3，本發明之電路裝置之製造方法 僅蝕刻上述第丨導電膜之溶液。 支為知用 第4，本發明之電路裝置之 包含氯化銅或是氯化鐵之容 、、徵為，使用 述溶液。 戴之…來做為進行上述钱刻之上 M 3 ^本4明之電路裝置之製μ㈣± # 第3導電膜藉由電解剝離來去除。 文為上述 第6,本發明之電路裝置之 採用僅蝕刻上述第3導電膜的，—/ ’徵為，藉由 3導電膜。 …的;谷液之敍刻，來去除上述第 第7,本發明之電路裝置之製造 溶液為碘系之溶液。 7符城為，上述 3)4953 9 1228813 、第8，本發明之電路裝置之製造方法的特徵為， 述第2導電膜進行全面蝕刻。 卜第9，本發明之電路裝置之製造方法的特徵為，上、 第2導電膜係以較上述第丨導電膜為厚之方式形成。述 第10,本發明之電路裝置之製造方法的特徵為，上 絕緣層/㈣指樹脂、熱硬化性樹脂、或是感光性樹脂: 々第11，本發明之電路裝置之製造方法的特徵為，上曰、求 第1 ‘電膜及上述第2導電膜為以銅為主材料之金 \ 述第3導電膜為以銀為主材料之金屬。 玉#上 第12,本發明之電路|置之製造方法的特徵為，以上 第2導電膜為基礎，#由電鍍來層疊上述第 上述第1導電膜，以製造上述層疊板。 —、 第⑴本發明之電路裝置之製造方法的 層登板乃藉由壓延接合來形成。 $ 弟14，本發明之電路裝置 連接上述露出並經錢敷的第1 件以外的電子元件。 之製造方法的特徵為，電性 導電膜的部分，及半導體元 弟15’本發明之電路裝置之製造方法的特徵 絕緣層乃藉由直办、、Φ段 馬上1 形成。 真工冲麼（PreSS)或是真空壓合（laminate)4 第 雷射加 16，本發明之電路裝置之製造方法的特徵為 工來局部去除上述絕緣層。 ’' 錯由 ，藉由 微影 314953 10 1228813 第18，本發明之電路裳置之製造方法的特徵為，藉由 採用上述帛2導電層來做為電極之電解錄敷，於上述導電 配線層的露出部分上形成鍍敷層。 ^ .如上所述，藉由利用形成較薄第丨導電膜，且以第3 ^電膜做為阻障層，來部分的去除第 士增+ ^ β 于乐1 ¥ ^膜可精密的形 成V電配線層。例如，採用銅做為 Α ^ ^ ^ „ 勹乐丄ν电膑，採用銀做 為第3 ‘電膜的情況下，當使用 、广十 田便用0有虱化銅或氯化鐵的溶 液來姑刻帛1導《膜，則銀具有不合被Γ 能。 β个曰被蝕刻的阻障層功 此外在本發明中，係藉由局部的去 ★ 成的導電配線層11Α來#作 〃 ⑨膜所形 胺 L 作光罩’以局部的去除第3導雷 、種局部的去除第3導電膜可利用 於利用餘刻局部的去除第…J用餘刻或電解剝離， 丨w玄除弟3導電膜的情 # 丄 1導電膜之際所使用的蝕 下’係與去除第 [實施方式] w刻液為不相同的材料。 關於本發明的電路裝置之 ^ 15圖加以說明。 / ，參知弟1圖至第 本發明的電路裝置之製造 電獏！3層疊3第 ’疋由，準備介以第3導 , 〒电膜Π及坌，、苦 10之製程;及藉由以所希 ¥電膜12的層疊板 來形成導電配線層11A 餘刻第1導電膜11， 為光罩，來去除 t 採用導電配線層]1A傲 ^ ^ 示罘3導電膜丨3之 1後’藉由去除第 x王，及以絕緣層j 5釆 表面部、及導電配後Λ 而露出之第2導電心的 曰】Α、及第3導電膜J3的端面之製
JI ^14953 1228813 程；及藉由去除絕緣層15的一部分，來局部露出導電 曰 &表柱；及於上述絕緣層上固定半導體元 並免性連接上述半導體元件及上述導電配線層之製程， 以密封樹脂層22包覆半導體元件19之製程；及：二 導電膜12 ,並传黛,1示弟2 …使弟3導電膜13在内側露出之製程；及於 ¥甩膜13的所希望的區域上，形成外部電極 程所構成。以下說明上述各製程。 之衣 第圖所示般’本發明的第1製程為，準備2介以 弟3導電膜13層疊了較 I 乂 導電膜12之層疊板1G之製程。 及^厚的第2 導電m η實質上係形成於層疊板1〇的全表面 上，並；丨以第3導電膜13，第2 於層疊板10的令内側上。第彳道士 、12只貝上亦形成 π 7内側上。第i導電膜i i及 f好是以銅(叫為主要材料者，或者是由眾所皆 木的材料來構成。第1導電膜1 1、第2導 、 導雷膜】‘電膜12及第3 著由麼延、、法、蒸鏟法或是減鍍法來形成，亦可貼 者由£^去或鍍敷法所形成的金屬箱。 及第2導電膜12亦可由A】、Fe、FeNi V^M 11 的引線架的材料等來構成。 或疋由眾所皆知 第3導電膜13的材料係採用 ^及第2導電们2之際所使__^除第】導電膜 此外，因為於第3導電膜13的内側，形成由::刻y才料。 的外部電極24，因此亦需考慮 寸錫寻所組成 具體而言，第3導電膜】3的材料=極24的附著性。 材科可刼用由金、銀、鈀 314953 12 1228813 (Palladium)所組成之導電材料。 為了形成精密的佈線圖幸，楚 較薄，其厚度大約在5至35“…電膜的厚度形成的 ^ ^ 7 ^m而為了機械性的支撐全 體，弟佈線圖案的厚度形成的較厚， 7〇至·…第3導電膜】 第、子度大，力在 及第2導電膜12之際作為 敍刻第1導電膜η 層的功能，其厚度約形成在 本發明的特徵在於，第2導電膜係以較第】導電膜為 厚之方式形成。第1導電膜的 一…* 形成大約在5至35”， 廷疋因為儘可能的形成的較薄，以 宏。楚9 it + 2 更幵/成更精密的佈線圖 案弟2導電膜的厚度大約在7〇至2〇〇… 視支撐強度之故。 k疋□為重 因此’藉由形成較厚的第2導雷膣 10的平㈣* ]弟2導電膜12，可維持層疊板 、千-性，並可提升之後的製程的運作性。 此外，在經過許多製程之後， ,^ 曰便弟2導電膜12產 生Η劳。然而’因為較厚的第 加以去除，因此可防止在^口膜2在之後的製程會 防止在元成扣的電路裝置上留下刮傷。 此外，因為可一方面維持一 ^ ^ ^ ^ ^ ^ ^ 卞一旺方面硬化密封樹脂，因 此也可使封裝的内側平坦化，亦可 板1 〇内側的外部電極。-y於層豐 电柽因此，將封裝基板上的電極與層疊 板10的内側的電極抵接，可防止銲錫的不良。 、接下來，針對上述的層疊板1〇的具體性製造方法加 以敘返。層璧板1G可藉由依據電鍵之層疊或是壓延接合 製造。於藉由電鍍來製造層疊板10的情況下，首先先準備 314953 13 1228813 第2導電膜12。然後於第2導電膜12的内側設置電極， 並藉由電解鍍敷法來層疊第3導電膜13。之後，同樣的藉 由電解鍍敷法，於第3導電膜13上層疊第1導電膜11。 於藉由壓延來製造層疊板的情況下，將預先準備好的板狀 第1導電膜11、第2導電膜12、及第3導電膜13,藉由 軋輥等來施加壓力以進行接合。 如第2圖及第3圖所示般，本發明的第2製程為，以 所希望的圖案來蝕刻第1導電膜11，以形成導電配線層 11A之製程。 於第1導電膜11上，以所希望的圖案之光阻Pr來包 覆’並藉由化學蝕刻來形成構成銲墊及配線的導電配線層 UA。因為第丨導電膜n是以cu為主要材料來構成，因 此蝕刻液可採用氣化銅或是氯化鐵。雖然在蝕刻第1導電 ' 1之際’第3導電膜13亦會與姓刻液接觸，但是因為 第3 V電膜1 3的材料不會被氣化銅及氯化鐵蝕刻，因此， 蝕刻會於第3導電膜13的表面上停止。由此，因為第j V電膜11的厚度形成約5至35//m左右，因此第！導電 配線層1 1 A可形成為5〇 " m以下的精密圖案。此外，如第 3圖所^般’在形成導電配線層11A之後再去除光阻PR。 曾本發明的特徵係，於蝕刻第1導電膜11之製程，以第 ' 3來阻止飿刻。於本製程當中，被姓刻的 ^ 電膜11主要杲^ 开疋以CU來構成，因此，可使用氯化銅或是 苟邛刀去除Cu之蝕刻液。相對的，因為楚 導電膜]3是由又么^ 疋田不會破氯化銅及氯化鐵蝕刻的導電性 1228813 所組成，因此，^ w … 餘刻會於第3導電膜M &生 弟3導電膜！ 3 電膜1 3的表面停止。關於 如第4圖所/可採用金、銀及免° 線層本發明的第3製程為，採用導電配 採用由先二來去除第3導電膜13之製程。 配線層11A，做A斤形成的第1導電膜11所組成的導電 於選擇性的去除第tr選擇性的去除第3導電膜⑴關 …方法為，=去電二13的方法，可採用2種方法。 刻的方法。第2種:弟3導電膜13的液體來進行蚀 導電膜13的方法。 藉由電場剝離來僅僅去除第3 在此’說明為第1藉t + 種方法之糟由蝕刻來部分去除第3 ¥電膜13的方法。於 於此方法所使用之蝕刻液，係採用可蝕 刻第3導電腺η w „ 、 、 、並且不會蝕刻導電配線層11 a及第2 ，電膜12者。例如，於導電配線層11A及第2導電膜12 疋由CU為主租的材料來形成，而第3導電膜13為Ag膜 的情況下’可藉由採用蛾系之㈣液，來僅僅去除第3導 電膜13。藉由蝕刻第3導電膜13，雖然第2導電膜12會 接觸碘系之蝕刻液，但是例如由Cu所構成之帛2導電膜 1 2並不會被碘系之蝕刻液蝕刻。因此，在此的蝕刻會於第 2導電膜12的表面停止。而在此之後，第2圖所示之光阻 PR可以於本製程之後再加以去除。 在此’說明為第2種方法之藉由電解剝離來僅僅去除 第3導電膜1 3的方法。首先，將包含金屬離子的溶液與第 3導電膜1 3接觸。然後於溶液側設置正電極，於層疊板j 〇 15 31495 1228813 攻置負電極，並進行直流電流之通電。藉此，藉由與依據 包解法形成鍍敷膜的相反原理，來僅僅去除第3導電膜 、，。在此所使用的溶液，可採用對構成第3導電膜13的材 料進行锻敷處理之際所使用者。因此，於此方法中，僅僅 剝離第3導電膜13。 如第5圖至第7圖所示般，本發明的第4製程為，以 、、、巴緣層1 5來包覆導電配線層丨丨a及第3導電膜1 3之製 程。 t 如第5圖所示，以絕緣層15來包覆第3導電膜13、 及導電配線層11A、及局部露出之第2導電膜12的表面。 具體而言，是以絕緣層15來包覆被局部去除的第3導電膜 13、及導電配線層丨1A的上面及側面（端面）。此外，亦以 、、、巴緣層1 5來包覆局部露出之第2導電膜】2的表面。關於 系巴緣層1 5的包覆，可藉由真空沖壓或是壓合之方法來進 行真二冲壓疋指，將由熱硬化性樹脂所形成之預浸潰薄 板（Preimpregnati〇n)加以疊合並於真空狀態下進行沖壓之 方法，可一次處理多數牧的層疊板1 0。而壓合之方法為採 用軋幸比’每次以1片塗佈熱硬化性樹脂或是感光性樹脂薄 板於層$板1G。於此方法中，後處理⑽⑽）製程乃藉 由批认處理而方;其他製程當中進行，而具有可精密控制厚 度之優點。 接下來參照第6圖 於絕緣層1 5上進行電性$ & 而設置孔16 °從孔16的底部 為了使預定承載之半導體元件]9 ，因而部分的去除絕緣層 露出的導電配線層1 1 A， 1 5 即 16 314953 1228813 成為銲墊的部分。而於絕緣層 況下，可揼用四 甶成先丨生材料所組成的情 而設置孔:6皆知之微影製程，來局部去除絕緣層15 法中，去 A外，孔16亦可藉由雷射來形成。於此方 "A。心：：層15 ’並於孔16的底部露出導電配線層 奇於运射，較為理想者為碳酸氣體 以雷射來蒸發絕緣層15之後，於開殘二卜， 愔況下，可y 1日7履#殘留殘渣的 下了採用過錳酸蘇打或是過硫酸 來去除殘渣。 丁 /”、、式蝕刻， 接下來參照第7圖，在從孔16露 電配線層11 A的主I 成為杯墊的導 成，乃可夢由=，形成鍍敷層21。鍍敷層21的形 :乃：…解鑛敷法來附著金或是銀來進行於此情 ' 知用弟2導電膜12來做為鍍敷電 敷不附著於第2導電膜12及鑛敷電二電：。此時，以鑛 的方式，以光阻來保護。此先: = 的内側上 敷部之部分治具錢敷則不需要。 。纟表面鍍 如第8圖所示般’本發明的第 件19固定於絕緣層15上，並電性 二二：… 電配線層UA之製程。 連接丰*肢兀件19及導 半導體元件19 乂： a μ上，著^Ρ)的狀態下，於絕緣層 半導體元件19*Th “ 叫）°因為 而被電氣性的絕缘〇广配線層11Α乃藉由絕緣層15 7、，巴緣，因此即使在半導俨 電配線物亦可自由的配線，兀件19的下方’導 此外，.導體元件19的各個電極襯墊乃藉由銲線2。， 1228813 連接於設置在周邊之導電配線層丨丨A的一部分之銲墊上。 而半導體元件19亦可藉由朝下（Face D〇wn)的方式來裝 設。於此情況下，於半導體元件19的各個電極襯墊表面: 設置銲球或是凸塊，並於層疊板1〇的表面上，在對應銲球 的位置之部分上設置由導電配線層11A所組成的銲墊相同 的電極。 接下來敘述關於採用銲線之際的層疊板1〇之優點。 一般於進行烊接Au線之際，乃加熱至2 〇〇。〇至3 〇〇它。此 時，一旦第2導電膜12較薄的話，則層疊板1〇會產生翹 曲，而一旦於此狀態下介以銲墊來加壓於層疊板1〇的話， 則有可肥使層$板1 0產生損害。然而，若是可使第2導電 膜12本身形成的較厚的話，則可解決這些問題。 如第9圖所示般，本發明的第6製程為，以密封樹脂 層22包覆半導體元件1 9及銲線2〇之製程。 層疊板10被設置於模壓成形裝置上，來進行樹脂模 壓成形。關於模壓成形方法，可採用轉注模壓成形、射出 成形、塗佈、浸入等。然而，就量產性來考慮的話，則轉 注模壓成形及射出成形較為適合。 於本製程當中，有必要使層疊板1〇平坦的抵接於模 穴（mold cavity)的下方模具上，而較厚的第2導電膜12則 具有此功能。並且在從模穴當中取出之後，在密封樹脂層 22的收縮完全結束為止之前，亦可藉由第2導電膜i 2來 維持封裝的平坦性。亦即，於本製程為止之層疊板1〇的機 械性支撐的功能，是由第2導電膜1 2來擔當。 314953 1228813 如弟1 〇圖所示般，本私日日 ^ ^ 尽么月的弟7製程為，去除第2 ¥電膜12，並使第3莫雷替 電膜1 3在内側露出之製程。 於本製程當中，以益先置办 认七4十、 …九罩耒全面去除第2導電膜12 的方式來進行蝕刻。此蝕刻 yL m ^ , T為抓用氣化銅或是氣化鐵之 化子姓刻，來全面去除第2導電 ^ 尾膜12。糟由上述全面去除 弟2導電膜12,可使第3暮雷胳 、1 3從絕緣層1 5當中露出。 G = ’所？導電膜13的材料是由，_餘刻第2 :膜所使用的敍刻溶液所姓刻之材料所組成， 本衣程當中，第3導電膜13不會被姓刻。 本發明的特徵在於，於與由 |y ^ 、精由蝕刻來去除第2導電膜的 衣矛王4中，利用第3導電膜 ώΑ…、 丨早嘴之功旎，而可平；t曰 的形成由絕緣層15及第3導 坌1、* 命电膜1 3所組成的内面。因為 弟2導電膜乃藉由蝕 口為 階段當中，第3導雷㈣Γ 因此於钱刻的最終 3導電膜二二 _刻液。如上所述，第 今電膜1 3的材料是出 i 導電膜】2 π: 刻由CU所構成的第2 V電膜12之際所使用的 所組成。因此，於第"千 鐵所钱刻之材料 成因此於第3導電膜13的下側的面上 進仃’所以第3導電膜具有 曰τ 製程之後，乃藉由密封樹脂…:::=於本 撐。 ^仃王肢的機械性支 如第11圖至箆ΐΐκϊα 一上 圖所不般，本發明的第s制 备 於第3導電膜1 3的所 衣私為， 製程。 心成外部電極24之 此才在Ag的遷移（Migration)形成問$ 风問嘀的環境中來 314953 19 1228813 使用的情況下’再以外敷層樹脂來包覆導電膜i 3之前，最 好選擇性的_第3導電膜13來加以去除。首先參昭第 '圖，針對第3導電膜13’將形成外部電極則部分予 以露出’並將以溶劑來溶化後之環氧樹脂等來進行網版印 刷(keen Printing)，並以外敷層樹脂23纟覆蓋住大部分 :第3導電膜13。接下來，如第12圖所示般，藉由銲錫 T的網版印刷及錄端旧、卜日 極24。 、錫…於此露出的部分上形成外部電 ^ 多…、第13圖，因為於層疊板10上形成多數之 矩陣狀的電路裝置，因此切割密封樹脂層22及外敷層樹脂 23，亚將它們分離為各個電路裝置。 於本製程當中，因為可藉由切割密封樹脂層22及外 曰才t爿曰23 ’來分離各個電路裝置，因此可降低於切割之 際所產生的切割器的損耗。 、接:來苓照第14圖，來說明具體化的本發明的製造 方法之電路裝置。以虛線所顯示的佈線圖案為導電配線層 "A。以包圍住半導體元件19的方式，來設置由導電配線 層iiA所組成的銲墊，並於對應半導體元件19的下方之 區或上’形成由導電配線層i iA所組成的銲墊。由此可得 方、半‘肢兀件1 9的下方之區域上，亦可形成由導電配 線層11A所組成的佈線圖案。此外，於導電配線| “A上， 可形成知也佈線圖案，並形成多數的外部電極。 要疋上述構4，即使是具有2⑽個以上的焊墊之半 導體元件19,均可利用導電配線層UA的精密佈線圖案， 31495. 20 1228813 來形成1 士^ & X吳有所希望的精密佈線圖案化之導電佈線圖案，因 可進行從外部電極2 4往外部電路之連接。 才妾下來參照第1 5圖，說明具體化的其他型態之電路 裝置】 導^ 。在此’於電路裝置1A上，形成了以虛線所示之 件電配線層丨丨A ’並於導電配線層11A上裝設了半導體元 2s 晶片兀件25、及裸裝之電晶體26。關於晶片元件 主可抓用所有的電阻、電容、二極體、線圈等被動元件、 =兀件。此外，内藏的元件之間，乃介以導電配線層11A 或是銲線20來電性連接。 [發明之效果] 艮據本發明’_形成較薄之第ι導電膜u，來形成 配線層11A的製程中’藉由設置做為阻障層之第3導 罙度來停止㈣。因此，藉由形成較 優點。 而具有形成精密的導電配線層ΗΑ的 此外，藉由從_開始之㈣來 12的製程中，第3導電膜η且士 陈弟2¥電月 且女 具有阻障層之功能，藉由此 八有可以平坦的形成絕緣層Μ， 第3導電膜13所槿乂及從絕緣層15露出^ 守包朕i J所構成之内側 的電路裝置内側之平坦性，故可提升：此由於可提升心 [圖式簡單說明] Μ升其品質。 第1圖係說明本發明的電 圖。 置的W造方法之剖面 第2圖係說明本發明 电路衣置的製造方法之剖面 314953 21 1228813 圖。 第3圖係說明本發明的電路裝置的製造方法之剖面 圖。 第4圖係說明本發明的電路·裝置的製造方法之剖面 圖。 第5圖係說明本發明的電路裝置的製造方法之剖面 圖。 第6圖係說明本發明的電路裝置的製造方法之剖面 圖。 第7圖係說明本發明的電路裝置的製造方法之剖面 圖。 第8圖係說明本發明的電路裝置的製造方法之剖面 圖。 第9圖係說明本發明的電路裝置的製造方法之剖面 圖。 第1 0圖係說明本發明的電路裝置的製造方法之剖面 圖。 第11圖係說明本發明的電路裝置的製造方法之剖面 圖。 第1 2圖係說明本發明的電路裝置的製造方法之剖面 圖。 第1 3圖係說明本發明的電路裝置的製造方法之剖面 圖。 第1 4圖係說明由本發明所製造之電路裝置的平面 314953 1228813 第1 5圖係說明由本發明所製造之電路 衣置的平； 圖。 十面 第16圖係說明習知半導體裝置的製造 乃，去之示咅 圖。 μ 第17圖係說明習知半導體裝置的製造方法立 不思圖。 第18圖（Α)至（C)係說明習知半導體裝置的製造方法 之示意圖。 第19圖係說明習知可撓式薄板之示意圖。 1 A 電路裝置 10 層疊板 11 第1導電膜 11A 導電配線層 12 第2導電膜 13 第3導電膜 15 絕緣層 16 子L 19 半導體元件 20 銲線 21 鍍敷層 22 密封樹脂層 23 外敷層樹脂 24 外部電極 25 晶片元件 26 電晶體 50 可撓式薄板 51 銅箔佈線圖案 5 1 A 銲墊 51B 轉接島 5 ID 電極 52 開D部 53 半導體元件 54 金屬細線 5 5 PR 密封樹脂 光阻 56 球狀銲錫 314953

Claims (1)

1228813 拾、申請專利範圍： 1 · 一種電路裝置之製造方法，係具備： 3導電 *用於準備將第1導電膜及帛2導電膜介以第 膜來層疊之層疊板之製程； ^藉由以所希望的佈線圖案來蝕刻上述第丨導電 膜’來形成導電配線層之製程； 採用上述導電配線層做為光罩，來去除上述第3 電膜之製程； ★以絕緣層來包覆利用去除上述第3導電膜而露出 之第2導電膜&面部、上述導電配線層卩帛〗導電膜 端面之製程； 、 藉由去除上述絕緣層的-部分，來局部露出上述導 電配線層之製程； 一；上述、、邑緣層上固定半導體元件，並電性連接上述 半導體70件及上述導電配線層之製程，· 以密封樹脂層包覆上述半導體元件之製程； 去除上述第2導電膜，並使上述第3導電膜在内側 露出之製程；以及 於上述第3導電膜的所希望的區域上，形成外部電 極之製程。 1項之電路裝置之製造方法，其中， 3導電膜為止，來精密地形成上述導 2 ·如申請專利範圍第 藉由姓刻至上述第 電配線層。 3·如申請專利範圍帛2項之電路裝置之製造方法，其中 314953 24 1228813 才木用僅可姓刻上述第1導電膜之溶液。 4·如申請專利範圍第2項或第3項之電路裝置之製造方 ’使用包含氯化銅或是氣化鐵之溶液，來做為 進仃上述姓刻之上述溶液。 ”、、 5· ^申請專利範圍第1項之電路裝置之製造方法，盆中， 上述第3導電膜藉由電場剝離來去除。 6^^專利❹第1項之電路裝置之製造方法，立中， 僅可…述第3導電膜的溶液厂二 除上述第3導電膜。 J木去 其中 7 範圍第6項之電路裝置之製造方法 上述洛液為碘系之溶液。 其中 8. 如申請專利範圍第丨項之電路裝 對上述第2導電膜進行全面姓刻。“方法 9. :::專利範圍第】項之電路裝置之製造方法 上述苐2導電膜择以^ ，、中 成。電一較上迷第1導電膜為厚之方式形 】〇.如申請專利範圍第〗項之電路裝置之製 上述、%緣層為熱可塑性樹 Ί 樹脂。 ·、、、更化性樹脂或是感光蚀 如申請專利範㈣】項之電路 上述第1導電膜及上述第之^方法，其令， 屬，上述第3導電膜為以銀為III::主材料之金 A"請專利範圍第】項之電路裘置之IT 以上述第2導電膜為 衣&方法，其中， 猎由電錢來層疊上述第3導 •314953 25 1228813 導電膜，來製造上述層疊板。 申明專利乾圍第1項之電路裝置之製送方 上述層疊板乃藉由麼延接合來形成。^法，其中， 14·如申請專利範圍第丨項之電路裝 電性連接上述^錢料難的^ 其中， 分，及半導體元件以外的電子元件。¥电膜的部 •如申凊專利範圍第1項之電路裝置之製造方去 =絕緣層乃藉由真空沖壓或是真空麼合來形成、中’ .如申請專利範圍第！項之電路裝置之製成。 藉由雷射加工來局部去除上述絕緣層。…其中’ 17.如申請專利範圍第i項之電路裝 藉由微影製程來局部去除上述絕緣層。方去，其中， 申凊專利範圍帛i項之電路裝置之製造方法，其 精由採用上述第2導電層來做為 ：、’ 述導電配線層的露出部分上形成鏟敷=“敷’於上 314953 26
TW092122219A 2002-09-26 2003-08-13 Method for manufacturing circuit device TWI228813B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002281889A JP4086607B2 (ja) 2002-09-26 2002-09-26 回路装置の製造方法

Publications (2)

Publication Number Publication Date
TW200408097A TW200408097A (en) 2004-05-16
TWI228813B true TWI228813B (en) 2005-03-01

Family

ID=32276219

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092122219A TWI228813B (en) 2002-09-26 2003-08-13 Method for manufacturing circuit device

Country Status (5)

Country Link
US (1) US7045393B2 (zh)
JP (1) JP4086607B2 (zh)
KR (1) KR100639737B1 (zh)
CN (1) CN1254860C (zh)
TW (1) TWI228813B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3704304B2 (ja) * 2001-10-26 2005-10-12 新光電気工業株式会社 リードフレーム及びその製造方法並びに該リードフレームを用いた半導体装置の製造方法
JP2004119729A (ja) * 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP2004119726A (ja) * 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP4052915B2 (ja) * 2002-09-26 2008-02-27 三洋電機株式会社 回路装置の製造方法
JP2004119727A (ja) * 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP4115228B2 (ja) * 2002-09-27 2008-07-09 三洋電機株式会社 回路装置の製造方法
JP5629969B2 (ja) * 2008-09-29 2014-11-26 凸版印刷株式会社 リードフレーム型基板の製造方法と半導体装置の製造方法
US7830024B2 (en) * 2008-10-02 2010-11-09 Advanced Semiconductor Engineering, Inc. Package and fabricating method thereof
WO2010112983A1 (en) * 2009-03-31 2010-10-07 Stmicroelectronics (Grenoble 2) Sas Wire-bonded semiconductor package with a coated wire
KR20180089607A (ko) * 2017-01-31 2018-08-09 삼성디스플레이 주식회사 증착용 마스크의 제조 방법
TWI848733B (zh) * 2023-06-02 2024-07-11 前源科技股份有限公司 電子元件的接合方法與巨量轉移電子元件的方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3357848B2 (ja) 1998-10-28 2002-12-16 三洋電機株式会社 半導体装置およびその製造方法
JP4509437B2 (ja) * 2000-09-11 2010-07-21 Ｈｏｙａ株式会社 多層配線基板の製造方法
JP2003007916A (ja) * 2001-06-19 2003-01-10 Sanyo Electric Co Ltd 回路装置の製造方法
JP2003007918A (ja) * 2001-06-19 2003-01-10 Sanyo Electric Co Ltd 回路装置の製造方法
JP2004119729A (ja) 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP2004119726A (ja) 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP4052915B2 (ja) 2002-09-26 2008-02-27 三洋電機株式会社 回路装置の製造方法
JP2004119727A (ja) 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP4115228B2 (ja) 2002-09-27 2008-07-09 三洋電機株式会社 回路装置の製造方法

Also Published As

Publication number Publication date
CN1497691A (zh) 2004-05-19
KR20040030301A (ko) 2004-04-09
JP2004119730A (ja) 2004-04-15
US20040106235A1 (en) 2004-06-03
US7045393B2 (en) 2006-05-16
TW200408097A (en) 2004-05-16
JP4086607B2 (ja) 2008-05-14
KR100639737B1 (ko) 2006-10-30
CN1254860C (zh) 2006-05-03

Similar Documents

Publication Publication Date Title
TW201010552A (en) Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board
JP5289832B2 (ja) 半導体装置および半導体装置の製造方法
TWI228813B (en) Method for manufacturing circuit device
JP2011014728A (ja) 半導体装置及び半導体装置の製造方法
TW548812B (en) Manufacturing method for circuit device
TW200406900A (en) Electric circuit device and method for making the same
US6951811B2 (en) Method of producing vias and other conductor parts on an electrode terminal forming surface of a semiconductor wafer
CN104134643A (zh) 具有超细间距倒装芯片凸点的基板
TWI248183B (en) Method of manufacturing circuit device
JP2004119726A (ja) 回路装置の製造方法
TWI234259B (en) Method for making an electric circuit device
TW201546912A (zh) 電子封裝件、封裝載板及兩者的製造方法
TWI360213B (en) Chip package carrier, chip package and method for
TW552691B (en) Method for making an electric circuit device
TW486799B (en) Semiconductor device and its manufacturing method
TW200538000A (en) Method for forming printed circuit board
KR101039774B1 (ko) 인쇄회로기판 제조를 위한 범프 형성 방법
JP2001068856A (ja) 絶縁樹脂シート及びその製造方法
US11393761B2 (en) Circuit board and its manufacturing method
TWI715261B (zh) 晶片尺寸封裝結構及其製作方法
KR101441466B1 (ko) 초박형 패키지기판 및 제조방법
KR101302380B1 (ko) 박형 인쇄회로기판 및 이의 제조 방법
TW201225758A (en) Multi-layer PCB modules with lateral conductive pads and fabrication methods thereof
JP2022172509A (ja) プリント配線板の製造方法
CN113871304A (zh) 一种无芯基板的制作方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees