TW578278B - Semiconductor laminated module - Google Patents

Semiconductor laminated module Download PDF

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Publication number
TW578278B
TW578278B TW091111837A TW91111837A TW578278B TW 578278 B TW578278 B TW 578278B TW 091111837 A TW091111837 A TW 091111837A TW 91111837 A TW91111837 A TW 91111837A TW 578278 B TW578278 B TW 578278B
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semiconductor
adhesive material
item
patent application
module according
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Hiroshi Shimoe
Naohisa Okumura
Takashi Imoto
Ryuji Hosokawa
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

請案之交互n 本案王張2001年6月19日申請之日本專利申請案N〇 = :-1 84783之優先權權益，其所有内容已併入其中以供 背景 1 ·發明之技術領域 本發明係關於例如將薄膜狀半導體晶片以倒$晶片接人 法連接而搭載於基座基板上之單體封裝體，積層複數個: 構成之半導體積層模組。 2 ·先前技藝 、兹將先前技術之半導體積層模組之結構一例子參閱圖4 說明=下。圖4為剖面圖，其半導體積層模組41係例如將 ^個單體封裝體42a、42b、42e依序積層而構成。例如， 取下層 < 早體封裝體42a係在玻璃一環氧樹脂製之基座基 板43a之上面，以倒裝法連接厚度為例如1〇〇 左右2 半導體晶片44a ’同時以例如由環氧系樹脂構成之薄膜狀 熱硬化性樹脂黏接材料等之晶片黏接材料45a予以接合而 構成者。半導體晶片44a則以基板黏接材料46a 一體黏接 於基座基板43a上，以構成單體封裝體42a。基座基板43& 足下面設有複數個焊錫球47，以構成與外部裝置間之連接 部。 在該單體封裝體42a之上方積層有第二層之單體封裝體 42b，並再積層有第三層之單體封裝體42c。該第三層單 體封裝體42c之上面則為單體之基座基板43d所覆 班一個單體封裝體42 a、42b、42 c之積層，係使用例如由 環氧系樹脂等熱硬化性樹脂黏接材料構成之半固化片 (preprag)等基板黏接材料46a、46b、，而藉由加 热、加壓，依序朝上下.方向加以黏接以構成三層積層體。 作為覆蓋用而設在最上部單體封裝體42c上之基座基板 43d係以與基座基板43a、川、仏相同之玻璃—環氧樹 月曰製成’且為基板黏接材料46c所黏接者。 經使三個單體封裝體42a、42b、42c疊成三次元積層 後’在半導體晶片44a、44b、“c之兩側形成以上下方向 貝通一層積層體之通孔48&、48b，並在該通孔Ua、48b 内形成鍍銅層49a、49b。 在圖4所示上述先前技術中，將單體封裝體42&、42b、 42c積層而形成為半導體積層模組41後，常會在該半導體 積層模組41發生彎度（301<〇，或因該彎度之故而使各基座 基板43a、43b、43c與半導體晶片44a、44b ' 44c間之 倒裝接合部分發生剝離，使得對於積層部分之密著性的可 靠性因此而下降。加上半導體晶片44a、44b、4打若形成 為薄膜狀，則在進行熱循環試驗時，亦有因反復發生於半 導體積層模組41之彎度而使各半導體晶片44a〜44c發生 裂痕之情況。 對這些問題之發生，經研究結果得知··由於經以倒裝法 使半導體晶片44a〜44c各自連接於基座基板43a〜43。 後，用以封閉半導體晶片44a〜44c之下面側的密封樹脂 之晶片黏接材料45a〜45c，與在進行單體封裝體42a〜 578278 五、發明説明（ 42c之積層時用以封閉半導體晶片44a〜44c之上面側的密 封树脂之基板黏接材料4 6 a〜4 6 c間之熱膨脹量差異所產 生足應力，就是造成彎度之發生原因。另外亦得知彎度亦 會因隨著溫度而變化的兩者之彈性率差所引起之應力而產 生。 發明之概述 依照本發明一實施形態之半導體積層模組，係具有：將 半導體晶片以第一黏接材料黏接於基座基板上而形成之複 數個單體封裝體；將該複數個單體封裝體以第二黏接材料 互相黏接而形成之積層體；以覆蓋上述半導體晶片上面之 方式所形成且具有與上述第一黏接材料大致相同的熱膨脹 係數之第三黏接材料層；以及以上述第二黏接材料黏接於 最上部之上述單體封裝體上之最上部基板。 、 圖式之簡要說明 圖1係顯示本發明半導體積層模組之一實施形態結構叫 面圖。 圖2係顯示圖1所示一實施形態之半導體積層模組結構要 素之單體模組結構剖面圖。 ^ 圖3係顯示在圖1所示一實施形態之半導體積層模組製造 工序中使圖2所示結構之單體模組予以積層三個而成、 態剖面圖。 圖4係顯示先前之半導體積層模組結構之一 圖。 發明之詳細說明 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） -6- 578278 五、發明説明（ 半導體晶片14a之上面，係如 — 、 你如圖1所不為具有與第一晶片 黏接材料15相同組成、相同屋厣 发 、、 又々承氧系树脂構成之薄膜 狀熱硬化性樹脂黏接材料之第-3 ^ ^ < 罘一晶片黏接材料17a所覆 最後予以堆積以環氧系樹脂等熱硬化性樹脂黏接材 料構成之半固化片等之基板黏接材料^，以覆蓋整個半 導把日日片14a及第一、第二晶片黏接材料15&、，且使 第二晶片黏接材料17a之上面露出於基板黏接材料—，即 可製得單體封裝體⑸。另外該晶片黏接材料15a、17a, 除應使用相同材料外，只要為屬具有相同程度之熱膨脹係 數者則可使用任一黏接材料。 其他之單體封裝體12b、12c也與單體封裝體12a同樣方 式構成。再者，圖1中雖不加圖示，但若在基座基板l3b、 13c也與圖2之基座基板13a同樣地在其上面及下面形成有 與配線23a-l、23a-2、23a-3、23a-4及配線24&-1、24&- 2、24a-3、24a-4、24a-5相同之配線，則可作為基座基板 13a-13c而量產相同規格者，這對於降低製造成本有益。 最後’以由例如環氧系樹脂等熱硬化性樹脂黏接材料構 成之半固化片等基板黏接材料18(：，將厚度為6〇 “爪之玻 璃一環氧樹脂製之最上部基板13d黏接於單體封裝體丨2c之 上面。於此狀態下之積層體結構係顯示於圖3。 再者，在圖3所示經施予三次元積層之單體封裝體12a〜 12c之積層體中，各半導體晶片14a〜14c係經整合而積層 於單體封裝體12a〜12c内互為大致相同之位置。在接近於 積層有這些各半導體晶片14a〜14c的位置之特定位置，如 -8- 本纸張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 578278 A7
578278
24a-2 、 24a-3 、 24a-4 、 24a-5 〇 然後對於如上述所構成半導體積層模組n，經加熱、加 壓後測武其臂度，結果己見有大幅度地減少，且並未曾有 在基座基板13a〜13c與半導體晶片14a〜14c之倒裝接合 部分發生剝離，或使積層部分之密著性惡化等狀況。另外 即使犯予熱循裱試驗，由於其係形同以具有相同組成且相 等厚度 '或熱膨脹係數相等或大致相等、厚度同樣地相等 或大致相等之第一及第二晶片黏接材料15a〜15c、17a〜 17c夾住半導體晶片14a〜14c而成之結構，因而能緩和產 生於半導體晶片14a〜14c内之應力，使半導體晶片14a〜 14c本身不致於發生裂痕，且能使發生裂痕之機率減少， 並且即使將半導體晶片1 4 a〜1 4 c形成為薄，亦能製得具 高可靠性之半導體積層模組u。另外第一、第二晶片黏接 材料15a〜15c、17a〜17c各自雖以使用相同材料為最 佳但，、要熱膨脹係數為屬相同程度則亦可使用任一黏接 材料。此外，除熱膨脹係數需為相同程度外，若使用彈性 率炙依存於溫度變化的變化率亦為大致相同之黏接材料， 則由於彈性率亦不會相對於溫度變化引起之應力變化而造 成差異，因而不致於造成相對於應力變化的彎度等之原 因。 再者，在上述實施形態中半導體晶片l4a〜l4c係使用 厚度為100 /zm者，但對於易於發生裂痕之厚度為2〇〇 以下者，也能獲得與上述相同之效果。 由上述之說明即得知，若依照本發明，即能製得能大幅 - -11_ 本紙張尺度適用巾s @家標準(CNS) A4—X297公釐1----- ^78278
度地減少將單體封裝體疊成三次元積層時所發生之彎度， 減y以倒裝法連接於基板的半導體晶片之剝離，且可提高 積層部分之密著性者’因而能提供_種即使為屬薄的半導 體晶片亦能消除會發生裂痕之虞而提高可#性之半導體積 層模組。 本發明之其他有利條件及變形，對於熟悉技藝之人士當 可容易達成，因而本發明在其廣泛的可供應用之局面中， 上述詳細說明及代表性實施例並非用以限制本發明，在不 脫離本發明之精神或附加的申請專利範圍所定義之獨創性 構想範圍内，當可作各種變形。 ____-12- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐）

Claims (1)

  1. 六、申請專利範圍 1· 一種半導體積層模組，其特徵為具有： 、手半導m日日片以第一黏接材料黏接於基座基板上而形 成之複數個單體封裝體； / 將該複數個單體封裝體以第二黏接材料互相黏接而形 成之積層體； 以覆蓋著上述半導體晶片上面而形成且具有與上述第 一黏接材料大致相同的熱膨脹係數之第三黏接材料層； 以及 9 以上述第一黏接材料黏接於最上部之上述單體封裝體 上之取上部基板。 2.如申請專利範圍第丨項之半導體積層模組，其中上述第 一黏接材料與第三黏接材料為相同材料。 3·如申請專利範圍第丨項之半導體積層模組，其中上述第 黏接材料與第三黏接材料具有大致相同的厚度。 4·如申請專利範圍第〗項之半導體積層模組，其$上述半 導體晶片係厚度為200 // m以下者。 5·如申請專利範圍第丨項之半導體積層模組，其中上述基 座基板係在其兩面具有特定的配線圖案。 6·如申請專利範圍第5項之半導體積層模組，其中上述複 數個基座基板係各自在其兩面具有相同的配線圖案。 7·如申請專利範圍第6項之半導體積層模組，其中上述積 層體含有接近於上述半導體晶片而形成之至少一個通 孔，及形成於該通孔的内壁之導電體膜，且上述複數個 早體封裝體係介以分別形成在基座基板上之配線圖案而 本紙張尺度it；?! t @ ®家標準(CNS) A4規格(210X297公复) 2 8 7 5
    8 8 8 8 A B c D 六、申請專利範圍 選擇性地連接於上述導電體膜。 8. 如申請專利範圍第1項之半導體積層模組，其中上述半 導體晶片係以倒裝晶片接合法連接於上述基座基板上。 9. 如申請專利範圍第1項之半導體積層模組，其中上述第 一黏接材料為熱硬化性樹脂。 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）
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Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3786103B2 (ja) * 2003-05-02 2006-06-14 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器および半導体装置の製造方法
JP4272968B2 (ja) * 2003-10-16 2009-06-03 エルピーダメモリ株式会社 半導体装置および半導体チップ制御方法
US7067910B2 (en) * 2004-04-13 2006-06-27 Sun Microsystems, Inc. Method and apparatus for using capacitively coupled communication within stacks of laminated chips
JP2005317861A (ja) * 2004-04-30 2005-11-10 Toshiba Corp 半導体装置およびその製造方法
JP2006165320A (ja) * 2004-12-08 2006-06-22 Matsushita Electric Ind Co Ltd 半導体積層モジュールとその製造方法
KR100663265B1 (ko) * 2005-05-10 2007-01-02 삼성전기주식회사 다층 기판 및 그 제조 방법
JP4689375B2 (ja) 2005-07-07 2011-05-25 富士通株式会社 積層基板および該積層基板を有する電子機器
US20070069396A1 (en) * 2005-09-29 2007-03-29 Samsung Electronics Co., Ltd. Semiconductor package, method of manufacturing the same, stacked semiconductor package including the same and method of manufacturing the stacked semiconductor package
US7312519B2 (en) * 2006-01-12 2007-12-25 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
KR100833589B1 (ko) * 2006-03-29 2008-05-30 주식회사 하이닉스반도체 스택 패키지
US20080179721A1 (en) * 2007-01-31 2008-07-31 Cheng-Lien Chiang Stacking of transfer carriers with aperture arrays as interconnection joints
US20090206481A1 (en) * 2007-01-31 2009-08-20 Nichepac Technology Inc. Stacking of transfer carriers with aperture arrays as interconnection joints
US20090051046A1 (en) * 2007-08-24 2009-02-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method for the same
WO2009035849A2 (en) 2007-09-10 2009-03-19 Vertical Circuits, Inc. Semiconductor die mount by conformal die coating
KR20090034081A (ko) * 2007-10-02 2009-04-07 삼성전자주식회사 적층형 반도체 패키지 장치 및 이의 제작 방법
KR101006518B1 (ko) * 2007-10-31 2011-01-07 주식회사 하이닉스반도체 스택 패키지
CN101999167B (zh) 2008-03-12 2013-07-17 伊文萨思公司 支撑安装的电互连管芯组件
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
JP5359165B2 (ja) * 2008-10-07 2013-12-04 日本電気株式会社 単結晶基板の非破壊反り測定方法及び測定装置
JP5321815B2 (ja) * 2009-03-19 2013-10-23 日本電気株式会社 非破壊単結晶基板反り測定法及び測定装置
JP2010238821A (ja) * 2009-03-30 2010-10-21 Sony Corp 多層配線基板、スタック構造センサパッケージおよびその製造方法
WO2011056668A2 (en) 2009-10-27 2011-05-12 Vertical Circuits, Inc. Selective die electrical insulation additive process
KR101740483B1 (ko) * 2011-05-02 2017-06-08 삼성전자 주식회사 고정 부재 및 할로겐-프리 패키지간 연결부를 포함하는 적층 패키지
CN104299964A (zh) * 2014-09-23 2015-01-21 武汉新芯集成电路制造有限公司 一种层叠封装结构及其制备方法
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
US10797005B2 (en) * 2017-11-27 2020-10-06 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and method for manufacturing the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3400877B2 (ja) * 1994-12-14 2003-04-28 三菱電機株式会社 半導体装置及びその製造方法
KR100206893B1 (ko) 1996-03-11 1999-07-01 구본준 반도체 패키지 및 그 제조방법
TW383435B (en) * 1996-11-01 2000-03-01 Hitachi Chemical Co Ltd Electronic device
US6448665B1 (en) * 1997-10-15 2002-09-10 Kabushiki Kaisha Toshiba Semiconductor package and manufacturing method thereof
JP2000124363A (ja) 1998-10-12 2000-04-28 Citizen Electronics Co Ltd 半導体パッケージ
JP2000252392A (ja) 1999-02-26 2000-09-14 Kyocera Corp 半導体素子搭載配線基板およびその実装構造
US6455924B1 (en) * 2001-03-22 2002-09-24 International Business Machines Corporation Stress-relieving heatsink structure and method of attachment to an electronic package

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