TWI452635B - 具有線入膜隔離障壁的積體電路封裝系統 - Google Patents

具有線入膜隔離障壁的積體電路封裝系統 Download PDF

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TWI452635B
TWI452635B TW097126021A TW97126021A TWI452635B TW I452635 B TWI452635 B TW I452635B TW 097126021 A TW097126021 A TW 097126021A TW 97126021 A TW97126021 A TW 97126021A TW I452635 B TWI452635 B TW I452635B
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Taiwan
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wire
die
film adhesive
line
wire bond
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TW097126021A
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TW200913087A (en
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Jonathan Abela
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Stats Chippac Ltd
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Description

具有線入膜隔離障壁的積體電路封裝系統 相關申請案之交互參照
本申請案主張美國臨時專利申請案第60/948,831(申請日2007年7月10日)的優先權，且其專利標的在此併入本文作為參考資料。
本發明大體係關於積體電路封裝系統，且詳言之，係關於具有線入膜的積體電路系統。
正快速成長的可攜式電子裝置市場(例如，蜂巢式行動電話、膝上電腦、及PDA)為現代生活的整合方面。眾多可攜式裝置為下一代封裝的最大潛力市場機會之一。該等裝置具有會大幅影響製造整合性的獨特屬性，因為一般而言，彼等必須具備尺寸小、重量輕以及機能豐富的性質而且必須以相對低的成本來大量生產。
為半導體工業之延伸部份的電子封裝工業歷經持續增加的商業競爭壓力，一直在成長的消費者預期，以及有意義產品差異在市場位置上的機會在遞減。
在開發下一代產品的地圖(road map)中，封裝及材料的工程與開發為這些下一代電子裝置插入策略(insertion strategy)的核心。未來的電子系統會更有智慧、密度更高、耗電更省、操作速度更快、而且可包含成本比現今低的混合技術裝置與組裝結構。
當前的封裝供應商都盡其所能地適應預計在未來幾年會超過一兆赫(TeraHertz，簡稱THz)的高速電腦裝置。當前的技術、材料、設備及結構提供這些新型裝置的基本組裝的挑戰，然而仍無法適當地應付與冷卻及可靠性有關的問題。
封包下一代積體電路封裝組裝的技術能力尚未得知，而且清楚的成本效益技術也尚待鑑定。除要求下一代裝置的效能以外，該工業此時要求成本為主要的產品差異因子以企圖滿足利潤目標。
結果，驅策電子封裝至精確超微小形式因子的地圖需要自動化以便達成可接受的良率(yield)。這些挑戰不僅要求製造自動化，也要求給生產經理及消費者的資料流與資訊自動化。
已有許多方法用連續數代的半導體來應付微處理器及可攜式電子裝置的先進封裝要求。許多工業地圖已發現在當前半導體性能與可利用支援性電子封裝技術之間的重大間隙。當前技術的限制與問題包含：增加時脈速率、電磁干擾輻射(EMI radiation)、熱負載、第二層次組裝可靠性應力及成本。
當這些封裝系統演化成用更多組件來結合不同的環境需求時，推動技術封包的壓力變為更具挑戰性。更重要的是，隨著一直在增加的複雜度，在製造期間錯誤的潛在風險會大幅增加。
鑑於持續在增加的商業競爭壓力、一直在成長的消費者預期、以及有意義產品差異在市場位置上的機會在遞減，以致於找出這些問題的答案愈來愈緊要。另外，要求節省成本、減少生產時間、改善效率及效能、以及滿足競爭壓力都會使找出這些問題的答案的必要性有愈來愈高的緊迫性。
因此，仍然需要更精巧以及更強健的封裝件與製造方法。人們長期以來一直在找這些問題的解決方案，但是先前技術並沒有教導或建議任何解決方案，因此這些問題的解決方案長期以來困惑了熟諳此藝者。
本發明提供一種積體電路封裝件之封裝方法，係包含：提供基板，係具有數個附著於其下的外接互連與有主動側裝在其上的第一線接合晶粒(wire-bonded die)；用接合線連接該第一線接合晶粒之該主動側與該基板；在該第一線接合晶粒上，安裝具有隔離障壁的線入膜黏著劑；以及，用囊封材料囊封該第一線接合晶粒、該等接合線、以及該線入膜黏著劑。
除了以上提及的以外，本發明還有一些實施例具有其他態樣或替代態樣。熟諳此藝者閱讀以下結合伴隨圖式的詳細說明將明白該等態樣。
下文會充分詳細地描述數個實施例讓熟諳此藝者得以製作及利用本發明。應瞭解，基於本揭示內容，顯然還有其他的實施例，而且在不脫離本發明的範疇下可更改系統、製程或機械。
在以下的描述中，給出許多特定細節供徹底瞭解本發明。不過，在沒有這些特定細節下，顯然仍可實施本發明。為了避免混淆本發明，有些習知電路、系統組構及製程步驟的細節將不予以詳述。
同樣，顯示系統實施例的圖式均為部份示意圖而且未按比例繪製，特別是有些尺寸是為了清楚呈現而在圖式中予以誇大。此外，為了闡明和便於圖解說明、描述及理解，在揭示及描述有一些共同特徵的多個實施例的地方，彼此相同及相似的特徵通常會用相似的元件符號描述。
此外，為了便於說明而將實施例編號為第一實施例、第二實施例等而不具有任何其他的意義或是想對本發明有所限制。
為了解釋的目的，本文所用之術語“水平”定義為與第一線接合晶粒之平面或表面平行的平面，而不管它的方向。術語“垂直”係指與剛才定義之水平垂直的方向。諸如“上方”、“下方”、“底面”、“頂面”、“側面”(如“側壁”)、“高於”、“低於”、“較上面”、“上面”、以及“下面”之類的術語都是以水平面來定義。術語“在…上”是意指元件之間的直接接觸。
本文所用之術語“加工”包含材料或光阻劑的沉積、圖案化、曝光、顯影、蝕刻、清洗、及/或材料或光阻劑的移除，如在形成描述之結構時要做的。
本文所用之術語“系統”係根據使用該術語的上下文，指稱及定義為本發明的方法與裝置。
現在參見第1圖，係顯示本發明第一實施例之積體電路封裝系統100的上視圖。圖中顯示之積體電路封裝系統100具有結構，例如第二線接合晶粒102。
該結構也可為中介層(interposer)或由積體電路與中介層構成的內部堆疊模組。在第二線接合晶粒102之下的是複合密度隔離障壁(compound density isolation barrier)，例如絕緣柵(insulating grid)104。圖中顯示之囊封材料106係囊封絕緣柵104與第二線接合晶粒102。
現在參見第2圖，係顯示沿著第1圖中之直線2-2繪出的積體電路封裝系統100之橫截面圖。圖中顯示之積體電路封裝系統100有基板202，例如塑膠或陶瓷基板。基板202具有數個黏在其下的外接互連204，例如錫球。
在基板202上安裝有主動側(active side)208的第一線接合晶粒206。第一線接合晶粒206用晶粒黏著劑(die attach adhesive)210附著於基板202上。第一線接合晶粒206的主動側208是用接合線212連接至基板202。
在第一線接合晶粒206上的是有主動側214的第二線接合晶粒102。第二線接合晶粒102的主動側214是用接合線212連接至基板202。
第二線接合晶粒102用線入膜黏著劑218附著於第一線接合晶粒206。線入膜黏著劑218有低黏度，而且隨著溫度增加，黏度會變低。
因此，可輕易地使線入膜黏著劑218覆蓋接合線212以及在第一線接合晶粒206上及周圍，然後加以固化以使線入膜黏著劑218硬化。
已發現，線入膜黏著劑218應為導熱介電材料。線入膜黏著劑218可由在固化後可硬化以及可保持預定厚度的B階段(B-stage)材料製成。
線入膜黏著劑218有單一密度而且包含絕緣柵104。有第二密度的絕緣柵104係嵌入線入膜黏著劑218以及防止接合線212進一步穿透而與第二線接合晶粒102接觸。
由於較薄晶片的需求增加，工程師也跟著把線入膜黏著劑218的尺寸減少到線入膜黏著劑218的厚度或接合線212的高度若有微小的變化就會危及製程的地步。
對微小差異有極度敏感性會導致接合線212短路或斷線。本發明人發現，添加複合密度隔離障壁104使得製程更好控制而且減少對於小高度差異的敏感性。這有助於增加線良率。
複合密度隔離障壁104可為不導電的陶瓷、塑膠或合成材料。複合密度隔離障壁104可由線入膜黏著劑218囊封。
圖中顯示之囊封材料106係囊封第一線接合晶粒206、接合線212、及線入膜黏著劑218。
現在參見第3圖，係顯示本發明第二實施例之積體電路封裝系統300的橫截面圖。圖中顯示之積體電路封裝系統300具有基板302，例如塑膠或陶瓷基板。基板302有數個附著於其下的外接互連304，例如錫球。
在基板302上安裝有主動側308的第一線接合晶粒306。第一線接合晶粒306用晶粒黏著劑310附著於基板302。第一線接合晶粒306的主動側308用接合線312連接至基板302。
在第一線接合晶粒306上有結構，例如有主動側316的第二線接合晶粒314。第二線接合晶粒314的主動側316用接合線312連接至基板302。
第二線接合晶粒314用線入膜黏著劑318附著於第一線接合晶粒306。線入膜黏著劑318具有低黏度，而且隨著溫度增加，黏度會變低。
因此，可輕易地使線入膜黏著劑318覆蓋接合線312以及在第一線接合晶粒306上及周圍，然後加以固化以使線入膜黏著劑318硬化。
已發現，線入膜黏著劑318應為導熱介電材料。線入膜黏著劑318可由在固化後可硬化以及可保持預定厚度的B階段材料製成。
線入膜黏著劑318具有單一密度而且包含複合密度隔離障壁，例如絕緣間隔件320。線入膜黏著劑318可嵌入絕緣間隔件320至任何一點讓接合線312有充分的空間可附著於第一線接合晶粒306的主動側308。絕緣間隔件320可為玻璃、陶瓷或其他絕緣材料。有第二密度的絕緣間隔件320係嵌入線入膜黏著劑318以及防止接合線312進一步穿透而與第二線接合晶粒314接觸。
由於較薄晶片的需求增加，工程師也跟著把線入膜黏著劑318的尺寸減少到線入膜黏著劑318的厚度或接合線312的高度若有微小的變化就會危及製程的地步。
對微小差異有極度敏感性會導致接合線312短路或斷線。本發明人發現，添加複合密度隔離障壁320使得製程更好控制而且減少對於小高度差異的敏感性。這有助於增加線良率。
圖中顯示之囊封材料322係囊封第一線接合晶粒306、接合線312及線入膜黏著劑318。
現在參見第4圖，係顯示本發明第三實施例之積體電路封裝系統400的橫截面圖。圖中顯示之積體電路封裝系統400有基板402，例如塑膠或陶瓷基板。基板402有數個附著於其下的外接互連404，例如錫球。
在基板402上安裝有主動側408的第一線接合晶粒406。第一線接合晶粒406用晶粒黏著劑410附著於基板402。第一線接合晶粒406的主動側408用接合線412連接至基板402。
在第一線接合晶粒406上有結構，例如具有主動側416的第二線接合晶粒414。第二線接合晶粒414的主動側416用接合線412連接至基板402。
第二線接合晶粒414用線入膜黏著劑418附著於第一線接合晶粒406。線入膜黏著劑418具有低黏度，而且隨著溫度增加，黏度會變低。
因此，可輕易地使線入膜黏著劑418覆蓋接合線412以及在第一線接合晶粒406上及周圍，然後加以固化以使線入膜黏著劑418硬化。
已發現，線入膜黏著劑418應為導熱介電材料。線入膜黏著劑418可由在固化後可硬化以及可保持預定厚度的B階段材料製成。
線入膜黏著劑418有單一密度而且包含複合密度隔離障壁，例如數個絕緣球體420。該等絕緣球體420的直徑可為5微米(μm)至10微米。絕緣球體420可為玻璃或其他絕緣材料。有第二密度的絕緣球體420均嵌入線入膜黏著劑418以及防止接合線412進一步穿透而與第二線接合晶粒414接觸。
由於較薄晶片的需求增加，工程師也跟著把線入膜黏著劑418的尺寸減少到線入膜黏著劑418的厚度或接合線412的高度若有微小的變化就會危及製程的地步。
對微小差異有極度敏感性會導致接合線412短路或斷線。本發明人發現，添加複合密度隔離障壁420使得製程更好控制而且減少對於小高度差異的敏感性。這有助於增加線良率。
圖中顯示之囊封材料422係囊封第一線接合晶粒406、接合線412及線入膜黏著劑418。
現在參見第5圖，係顯示本發明第四實施例之積體電路封裝系統500的橫截面圖。圖中顯示之積體電路封裝系統500具有基板502，例如塑膠或陶瓷基板。基板502具有數個附著於其下的外接互連504，例如錫球。
在基板502上安裝有主動側508的第一線接合晶粒506。第一線接合晶粒506用晶粒黏著劑510附著於基板502。第一線接合晶粒506的主動側508用接合線512連接至基板502。
在第一線接合晶粒506上的是有主動側516的第二線接合晶粒514。第二線接合晶粒514的主動側516用接合線512連接至基板502。
在第二線接合晶粒514上的是有主動側520的第三線接合晶粒518。第三線接合晶粒518的主動側520用接合線512連接至基板502。
第二線接合晶粒514用多層線入膜黏著劑522附著於第一線接合晶粒506與第三線接合晶粒518。多層線入膜黏著劑522具有低黏度，而且隨著溫度增加，黏度會變低。
因此，可輕易地使多層線入膜黏著劑522覆蓋接合線512以及在第一線接合晶粒506及第二線接合晶粒514上及周圍，然後加以固化以使多層線入膜黏著劑522硬化。
已發現，多層線入膜黏著劑522應為導熱介電材料。多層線入膜黏著劑522可由在固化後可硬化以及可保持預定厚度的B階段材料製成。
多層線入膜黏著劑522具有單一密度而且包含複合密度隔離障壁，例如絕緣片體524。絕緣片體524可為相同但已予固化之B階段材料的膜狀黏著劑或者是預先層壓於線入膜黏著劑522之另一密度膜的膜狀黏著劑。有第二密度的絕緣片體524係嵌入多層線入膜黏著劑522以及防止接合線512進一步穿透而與第二線接合晶粒514及第三線接合晶粒518接觸。
由於較薄晶片的需求增加，工程師也跟著把多層線入膜黏著劑522的尺寸減少到多層線入膜黏著劑518的厚度或接合線512的高度若有微小的變化就會危及製程的地步。
對微小差異有極度敏感性會導致接合線512短路或斷線。本發明人發現，添加複合密度隔離障壁524使得製程更好控制而且減少對於小高度差異的敏感性。這有助於增加線良率。
圖中顯示之囊封材料526係囊封第一線接合晶粒506、接合線512及多層線入膜黏著劑522。
現在參見第6圖，係顯示本發明第五實施例之積體電路封裝系統600的橫截面圖。圖中顯示之積體電路封裝系統600有基板602，例如塑膠或陶瓷基板。基板602具有數個附著於其下的外接互連604，例如錫球。
在基板602上安裝有主動側608的第一線接合晶粒606。第一線接合晶粒606用晶粒黏著劑610附著於基板602。第一線接合晶粒606的主動側608用接合線612連接至基板602。
在第一線接合晶粒上可安裝結構，例如有主動側616的第二線接合晶粒614。第二線接合晶粒614的主動側616用接合線612連接至基板602。
第二線接合晶粒614用線入膜黏著劑618附著於第一線接合晶粒606。線入膜黏著劑618有往第二線接合晶粒614增加的梯度密度(gradient density)。
黏度與密度在第一線接合晶粒606的主動側608附近都低而在第二線接合晶粒614附近增加。因此，可輕易地使線入膜黏著劑618覆蓋接合線612以及在第一線接合晶粒606上及周圍。線入膜黏著劑618可具有由第一線接合晶粒606線性增加至第二線接合晶粒614的實質線性密度級數(density progression)622。
在線入膜黏著劑618的密度不允許接合線612進一步穿透從而可防止接合線612與第二線接合晶粒614接觸的地方，線入膜黏著劑618建立隔離障壁，例如梯度密度障壁(gradient density barrier)620。
由於較薄晶片的需求增加，工程師也跟著把線入膜黏著劑618的尺寸減少到線入膜黏著劑618的厚度或接合線612的高度若有微小的變化就會危及製程的地步。
對微小差異有極度敏感性會導致接合線612與結構614短路或斷線。本發明人發現，添加隔離障壁620使得製程更好控制而且減少對於小高度差異的敏感性。這有助於增加線良率。
藉由預先固化線入膜黏著劑618的梯度密度障壁620可建立梯度密度障壁620。預先固化可精確地產生實質線性密度級數622要求的想要密度數量及類型。
使用厚度減薄或電位吸引法也可建立梯度密度障壁620。電位吸引法可使用隨著時間增加而減少的電位以建立實質線性的密度級數622。圖中顯示之囊封材料624係囊封第一線接合晶粒606、接合線612及線入膜黏著劑618。
現在參見第7圖，係顯示本發明第六實施例之積體電路封裝系統700的橫截面圖。圖中顯示之積體電路封裝系統700具有基板702，例如塑膠或陶瓷基板。基板702具有數個附著於其下的外接互連704，例如錫球。
在基板702上安裝有主動側708的第一線接合晶粒706。第一線接合晶粒706用晶粒黏著劑710附著於基板702。第一線接合晶粒706的主動側708用接合線712連接至基板702。
在第一線接合晶粒上可安裝結構，例如有主動側716的第二線接合晶粒714。第二線接合晶粒714的主動側716用接合線712連接至基板702。
第二線接合晶粒714用線入膜黏著劑718附著於第一線接合晶粒706。線入膜黏著劑718有往第二線接合晶粒714增加的梯度密度。
黏度與密度在第一線接合晶粒706的主動側708附近都低而在第二線接合晶粒714附近增加。因此，可輕易地使線入膜黏著劑718覆蓋接合線712以及在第一線接合晶粒706上及周圍。線入膜黏著劑718也可具有由第一線接合晶粒706指數增加至第二線接合晶粒714的實質指數密度級數722。
在線入膜黏著劑718的密度不允許接合線712進一步穿透從而可防止接合線712與第二線接合晶粒714接觸的地方，線入膜黏著劑718建立隔離障壁，例如梯度密度障壁720。
由於較薄晶片的需求增加，工程師也跟著把線入膜黏著劑718的尺寸減少到線入膜黏著劑718的厚度或接合線712的高度若有微小的變化就會危及製程的地步。
對微小差異有極度敏感性會導致接合線712與結構714短路或斷線。本發明人發現，添加隔離障壁720使得製程更好控制而且減少對於小高度差異的敏感性。這有助於增加線良率。
藉由預先固化線入膜黏著劑718的梯度密度障壁720可建立梯度密度障壁720。預先固化可精確地產生實質指數密度級數722要求的想要密度數量及類型。
使用厚度減薄或電位吸引法也可建立梯度密度障壁720。電位吸引法可使用隨著時間增加而減少的電位以建立實質指數密度級數722。圖中顯示之囊封材料724係囊封第一線接合晶粒706、接合線712及線入膜黏著劑718。
現在參見第8圖，係顯示用於製造積體電路封裝系統100的方法800之流程圖。方法800包含：在方塊802，提供基板，其係具有數個附在其下的外接互連與有主動側裝在上面的第一線接合晶粒；在方塊804，用接合線連接該第一線接合晶粒之該主動側與該基板；在方塊806，在該第一線接合晶粒上，安裝有隔離障壁的線入膜黏著劑；以及，在方塊808，用囊封材料囊封該第一線接合晶粒、該等接合線、以及該線入膜黏著劑。
因此，已發現，用以使接合線不會與裝在其上之結構接觸的本發明隔離障壁提供先前技術未知、不曾採用而且有重要性的解決方案、性能及功能態樣。所得到的製程及組構都有明確性、成本效益、簡單不複雜、高度通用性、準確性、敏感性、及有效性，而且藉由修改習知組件即可實作成立即可用、有高效率又經濟的製造方式、應用及利用。
儘管已結合特定的最佳模式來描述本發明，應瞭解，熟諳此藝者在參閱前述描述後會明白仍有許多替代、修改及變體。因此，希望本發明能涵蓋所有這類落入隨附之申請專利範圍之範疇內的替代、修改及變體。所有迄今為止在本文及伴隨圖式中提及或顯示的內容都應被解釋成只是用來做圖解說明而沒有限定本發明的意思。
100、300、400、500、600、700．．．積體電路封裝系統
102、314、414、514、614、714．．．第二線接合晶粒
104．．．絕緣柵
106、322、422、526、624、724．．．囊封材料
202、302、402、502、602、702．．．基板
204、304、404、504、604、704．．．外接互連
206、306、406、506、606、706．．．第一線接合晶粒
208、214、308、316、408、416、508、516、520、608、616、708、716．．．主動側
210、310、410、510、610、710．．．晶粒黏著劑
212、312、412、512、612、712．．．接合線
218、318、418、522、618、718．．．線入膜黏著劑
320．．．絕緣間隔件
420．．．絕緣球體
518．．．第三線接合晶粒
524．．．絕緣片體
620、720．．．梯度密度障壁
622、722．．．實質線性密度級數
800．．．方法
802至808．．．方塊
第1圖係本發明第一實施例之積體電路封裝系統的上視圖；
第2圖係沿著第1圖中之直線2-2繪出的積體電路封裝系統的橫截面圖；
第3圖係本發明第二實施例之積體電路封裝系統的橫截面圖；
第4圖係本發明第三實施例之積體電路封裝系統的橫截面圖；
第5圖係本發明第四實施例之積體電路封裝系統的橫截面圖；
第6圖係本發明第五實施例之積體電路封裝系統的橫截面圖；
第7圖係本發明第六實施例之積體電路封裝系統的橫截面圖；以及
第8圖係根據本發明之實施例圖示用於製造第1圖之積體電路封裝系統之方法的流程圖。
100．．．積體電路封裝系統
102．．．第二線接合晶粒
104．．．絕緣柵
106．．．囊封材料
202．．．基板
204．．．外接互連
206．．．第一線接合晶粒
208、214．．．主動側
210．．．晶粒黏著劑
212．．．接合線
218．．．線入膜黏著劑

Claims (8)

  1. 一種積體電路封裝件之封裝方法，係包括：提供基板，該基板具有以主動側裝在其上的第一線接合晶粒；用接合線連接該第一線接合晶粒之該主動側與該基板；在該第一線接合晶粒上，安裝具有梯度密度障壁的線入膜黏著劑；以及用囊封材料囊封該第一線接合晶粒、該等接合線以及該線入膜黏著劑。
  2. 如申請專利範圍第1項所述之方法，其中：安裝線入膜黏著劑係包含：安裝多層線入膜黏著劑。
  3. 如申請專利範圍第1項所述之方法，其中：安裝具有梯度密度障壁的線入膜黏著劑係包含：安裝具有實質線性密度級數的線入膜黏著劑。
  4. 如申請專利範圍第1項所述之方法，其中：安裝具有梯度密度障壁的線入膜黏著劑係包含：安裝具有實質指數密度級數的線入膜黏著劑。
  5. 一種積體電路封裝件之封裝系統，係包括：基板，係具有以主動側裝在其上的第一線接合晶粒；連接該第一線接合晶粒之該主動側與該基板的接合線； 具有梯度密度障壁的線入膜黏著劑，係裝在該第一線接合晶粒上；以及囊封材料，係囊封該第一線接合晶粒、該等接合線以及該線入膜黏著劑。
  6. 如申請專利範圍第5項所述之系統，其中：該線入膜黏著劑為多層線入膜黏著劑。
  7. 如申請專利範圍第5項所述之系統，其中：該梯度密度障壁包括實質線性密度級數。
  8. 如申請專利範圍第5項所述之系統，其中：該梯度密度障壁包括實質指數密度級數。
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