TWI627720B - 指紋感測晶片封裝結構 - Google Patents

指紋感測晶片封裝結構 Download PDF

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TWI627720B
TWI627720B TW106129026A TW106129026A TWI627720B TW I627720 B TWI627720 B TW I627720B TW 106129026 A TW106129026 A TW 106129026A TW 106129026 A TW106129026 A TW 106129026A TW I627720 B TWI627720 B TW I627720B
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fingerprint sensing
sensing chip
package structure
chip package
metal contact
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TW106129026A
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TW201913932A (zh
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盧崇義
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致伸科技股份有限公司
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Priority to TW106129026A priority Critical patent/TWI627720B/zh
Priority to US15/830,796 priority patent/US10445554B2/en
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Publication of TW201913932A publication Critical patent/TW201913932A/zh

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06VIMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12Fingerprints or palmprints
    • G06V40/1365Matching; Classification
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06VIMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12Fingerprints or palmprints
    • G06V40/13Sensors therefor
    • G06V40/1329Protecting the fingerprint sensor against damage caused by the finger
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Abstract

本發明提供一種指紋感測晶片封裝結構,包括:基板,具有第一表面、第二表面及貫穿開口,第二表面包括自貫穿開口延伸出的凹槽及第二金屬接點,凹槽則用以容置第一金屬接點;具有上表面及下表面的指紋感測晶片,係設置於貫穿開口之中且下表面具有焊墊;蓋板,固設於基板的第一表面並覆蓋指紋感測晶片的上表面;以及軟性電路板,設置於基板的第二表面,且軟性電路板之表面具有第三金屬接點,第三金屬接點對應於第二金屬接點,並與第二金屬接點電性連接;其中,焊墊藉由導線與第一金屬接點電性連接。

Description

指紋感測晶片封裝結構
本發明係有關於一種晶片封裝的應用領域,尤指一種用於指紋感測晶片的封裝結構。
隨著科技的進步,具指紋辨識功能的指紋辨識模組也已被廣泛地設置於電子裝置中,而成為電子裝置的標準配備之一。而使用者可藉由指紋辨識模組進行身分的識別,以進一步解除電子裝置的鎖定或進行軟體介面的操作。
習知的技術中,如圖1所示,圖1係為習知指紋感測晶片封裝結構的剖面圖。於圖1中,指紋感測模組20係由平面網格陣列封裝(Land Grid Array,LGA)技術封裝製成,包括有:指紋感測晶片21、基板22、覆蓋於指紋感測晶片21及基板22之上的環氧模壓樹脂(Epoxy Molding Compound,EMC)層23、蓋板24、軟性電路板25及補強板26。其中,指紋感測晶片21的上表面具有焊墊211,基板25上具有金屬接點221,焊墊211則藉由導線W與金屬接點221電性連接。
而於習知的技術中,指紋感測模組20之蓋板24的厚度介於120μm~250μm之間。基板22的厚度介於130μm~310μm之間。指紋感測晶片21的厚度介於150μm~400μ m之間。而為保護導線W及維持其機械強度,環氧模壓樹脂層23的厚度通常為選用指紋感測晶片21之厚度再加上50μm。而軟性電路板25及補強板26的厚度均為120μm。此外,在封裝完成後,需再加上約20μm的灌封膠厚度及約60μm的錫焊厚度。在現今電子裝置不斷追求輕薄化的趨勢中,雖以習知的封裝技術封裝製成的指紋感測模組20其厚度最薄可達770μm,然而,由於封裝材料收縮的特性,可能會導致指紋感測模組20產生翹曲的現象,且讓指紋感測模組20失去應有的機械強度。
有鑑於此,如何提供一種指紋感測晶片封裝結構,使其於在薄型化的過程中,可同時維持其良好的機械強度,並避免翹曲情況的產生,為本發明欲解決的技術課題。
本發明之主要目的,在於提供一種薄型化且同時維持良好機械強度的指紋感測晶片封裝結構。
為達前述之目的,本發明提供一種指紋感測晶片封裝結構,包括:基板,具有第一表面、第二表面及貫穿第一表面及第二表面的貫穿開口,第二表面包括自貫穿開口延伸出的凹槽及第二金屬接點,且凹槽用以容置第一金屬接點;指紋感測晶片,設置於貫穿開口之中,且具有上表面及下表面,下表面具有焊墊;蓋板,固設於基板的第一表面並覆蓋指紋感測晶片的上表面;以及軟性電路板,設置於基板的第二表面,且軟性電路板之表面具有第三金屬接點,第三金屬接點對應於第二金屬接點,並與第二金屬接點電性連接;其中,焊墊藉由導線與第一金屬接點電性連接。
於上述較佳實施方式中,其進一步包括補強板,補強板設置於軟性電路板相對於第三金屬接點之表面的另一表面上。
於上述較佳實施方式中,其中膠體塗佈於焊墊、導線及第一金屬接點,膠體為底部填充膠。
於上述較佳實施方式中,其中第一膠片層形成於蓋板與基板之第一表面之間,用以黏合蓋板及基板。
於上述較佳實施方式中,其中蓋板包括膠水層,形成於對應貫穿開口的位置,並用以黏合指紋感測晶片的上表面。
於上述較佳實施方式中,其中第二膠片層形成於軟性電路與補強板之間,並用以黏合軟性電路及補強板。
於上述較佳實施方式中,其中基板為:電木板、玻璃纖維板、塑膠板或陶瓷板。
於上述較佳實施方式中,其中蓋板的材質為:陶瓷或玻璃。
於上述較佳實施方式中,其中補強板的材質為:不銹鋼、鎢鋼、鋁或馬口鐵。
於上述較佳實施方式中,其中基板的厚度介於295μm~305μm之間。
於上述較佳實施方式中,其中基板的厚度為300μm。
於上述較佳實施方式中,其中蓋板的厚度介於90μm~110μm之間。
於上述較佳實施方式中,其中蓋板的厚度為100μm。
於上述較佳實施方式中,其中補強板的厚度介於145μm~155μm之間。
於上述較佳實施方式中,其中補強板的厚度為150μm。
C‧‧‧第一金屬接點
G‧‧‧膠體
W‧‧‧導線
10‧‧‧指紋感測晶片封裝結構
11、21‧‧‧指紋感測晶片
111、141、151‧‧‧上表面
112、142、152‧‧‧下表面
1121、211‧‧‧焊墊
12‧‧‧基板
121‧‧‧第一表面
122‧‧‧第二表面
1221‧‧‧第二金屬接點
123‧‧‧貫穿開口
1231‧‧‧凹槽
13、24‧‧‧蓋板
131‧‧‧第一膠片層
132‧‧‧膠水層
14、25‧‧‧軟性電路板
1411‧‧‧第三金屬接點
15、26‧‧‧補強板
1511‧‧‧第二膠片層
20‧‧‧指紋感測模組
22‧‧‧基板
221‧‧‧金屬接點
23‧‧‧環氧模壓樹脂層
圖1:係為習知指紋感測晶片封裝結構的剖面圖;圖2:係為本發明所提供之指紋感測晶片封裝結構的立體分解圖;以及圖3:係為本發明所提供之指紋感測晶片封裝結構的剖面圖。
本發明的優點及特徵以及達到其方法將參照例示性實施例及附圖進行更詳細的描述而更容易理解。然而,本發明可以不同形式來實現且不應被理解僅限於此處所陳述的實施例。相反地,對所屬技術領域具有通常知識者而言,所提供的此些實施例將使本揭露更加透徹與全面且完整地傳達本發明的範疇。
首先,請參閱圖2所示,圖2係為本發明所提供之指紋感測晶片封裝結構的立體分解圖。於圖2中,所述的指紋感測晶片封裝結構10包括:指紋感測晶片11、基板12、蓋板13、軟性電路板(Flexible Print Circuit,FPC)14以及補強板15。
請繼續參閱圖2,所述的指紋感測晶片11具有上表面111及下表面112,於本發明的設計中,係利用矽導通孔(Through Silicon Via,TSV)製程技術將指紋感測晶片11之焊墊1121佈置於指紋感測晶片11之下表面112相對的二側邊。雖本發明雖僅提出利用矽導通孔製程技術將指紋感測晶片11之焊墊1121佈置於下表面112相對的二側邊的實施方式,但於實際應用時,亦可利用矽導通孔製程技術及線路重佈技術(Redistribution Layer,RDL)製程技術將焊墊1121集中佈置於指紋感測晶片11之下表面112的任一側邊,而不以本發明所提出的實施方式為限。
所述的基板12具有第一表面121、第二表面122以及貫穿第一表面121與第二表面122的貫穿開口123。其中,第二表面122上具有二個第二金屬接點1221及自貫穿開口123相對的兩側邊延伸出的二個凹槽1231,而凹槽1231則用以容置第一金屬接點C,貫穿開口123則用以容置指紋感測晶片11。本發明所述的基板12的材質可為:電木板、玻璃纖維板、塑膠板或陶瓷板等。
所述的蓋板13之表面包括:第一膠片層131及膠水層132。第一膠片層131用以將蓋板13與基板12之第一表面121進行黏合;膠水層132則佈置於對應於貫穿開口123的位置,並用以黏合指紋感測晶片11的上表面111。其中,第一膠片層131為一種熱壓型雙面膠;膠水層132則為一種熱固型水膠。而蓋板13的材質則可為:陶瓷或玻璃,於一較佳的實施方式中,蓋板13係由藍寶石玻璃所製成。本發明雖僅提出將第一膠片層131及膠水層132佈置於蓋板13之表面的實施方式,但於實際應用時亦可將第一膠片層131佈置於基板12之第一表面121,或將膠水層132佈置於指紋感測晶片11的上表面111,而不以本發明所提出的實施方式為限。
所述的軟性電路板14具有上表面141及相對於上表面141的下表面142。其中,軟性電路板14之上表面141佈置有二個第三金屬接點1411,而第三金屬接點1411佈置的位置係對應於基板12之第二表面122上第二金屬接點1221佈置的位置,且第三金屬接點1411用以與第二金屬接點1221電性連接。本發明雖僅提出二個第三金屬接點1411對應於二個第二金屬接點1221的實施方式,但於實際應用時,亦可依據第二金屬接點1221的個數及佈置位置調整相對應第三金屬接點1411的個數及位置,而不以本發明所提出的實施方式為限。
所述的補強板15則具有上表面151及下表面152。其中,上表面151佈置有第二膠片層1511,用以將補強板15與軟性電路板14之下表面142進行黏合,以藉此提升軟性電路板14 的機械強度。其中,補強板15係由金屬材質所製成,於一較佳實施方式中,補強板15的材質可為:不銹鋼、鎢鋼、鋁或馬口鐵;而第二膠片層1511則為一種熱固型導電雙面膠。
接著,請參閱圖3,圖3係為本發明所提供之指紋感測晶片封裝結構的剖面圖。於圖3中,蓋板13藉由第一膠片層131與基板12之第一表面121相互黏合,使蓋板13可固設於基板12之第一表面121。另一方面,蓋板13亦同時覆蓋於指紋感測晶片11的上表面111,並利用膠水層132與指紋感測晶片11之上表面111相互黏合以固定指紋感測晶片11,而藉由圍繞設置於指紋感測晶片11周緣的基板12提升指紋感測晶片11的機械強度,使指紋感測晶片11可穩固地設置於基板12的貫穿開口123之中。
軟性電路板14則設置於基板12之第二表面122上,並可於軟性電路板14的上表面141或基板12之第二表面122佈置一異方性導電膠膜(Anisotropic Conductive Film,ACF)(未示於圖中),而軟性電路板14則藉由異方性導電膠膜與基板12之第二表面122相互黏合。此外,由於第三金屬接點1411佈置於與第二金屬接點1221相對應的位置,如此第三金屬接點1411便可與第二金屬接點1221相接合並產生電性連接。
接著,佈置於指紋感測晶片11之下表面112的焊墊1121則藉由導線W與基板12凹槽1231內的第一金屬接點C電性連接。隨後,可將膠體G塗佈於焊墊1121、導線W及第一金屬接點C的位置,以保護焊墊1121、導線W及第一金屬接點C,避免焊墊1121、導線W及第一金屬接點C的氧化或受到外界環境的水氣影響而腐蝕,亦可藉此提升導線W的機械強度及抗衝擊能力。其中,膠體W為一種底部填充膠(underfill)。而於本發明另一較佳的實施方式中,亦可於指紋感測晶片11與軟性電路板14之間填充一具有彈性的固化膠(未示於圖中),以藉此提升整體指紋感測晶片封裝結構10的抗衝擊能力。本發明雖僅提出自貫穿開口123相對的兩側邊延伸出二個凹槽1231,並以凹槽1231容置第一金屬接 點C的實施方式,但於實際應用時,亦可依據指紋感測晶片11下表面112之焊墊1121的個數及佈置位置調整凹槽1231形成的位置及個數,而不以本發明所提出的實施方式為限,舉例而言,若焊墊1121以矽導通孔製程技術及線路重佈技術製程技術集中佈置於指紋感測晶片11之下表面112的一側邊時,可自貫穿開口123對應的同一側延伸出凹槽1231以容置第一金屬接點C即可,而毋須再額外設置另一個容置第一金屬接點C的凹槽1231。
請繼續參閱圖3,於圖3中,蓋板13的厚度介於90μm~110μm之間;第一膠片層131的厚度約為20μm;基板12的厚度介於295μm~305μm之間;異方性導電膠膜(未示於圖中)的厚度介於10μm~25μm之間;軟性電路板14的厚度為120μm;第二膠片層151的厚度約為20μm;補強板15的厚度則介於145μm~155μm之間;如此指紋感測晶片封裝結構10整體的厚度可介於700μm~755μm之間。於一較佳的實施方式中,蓋板13的厚度為100μm;第一膠片層131的厚度約為20μm;基板12的厚度為300μm;異方性導電膠膜(未示於圖中)的厚度為10μm;軟性電路板14的厚度為120μm;第二膠片層151的厚度約為20μm;補強板15的厚度為150μm。而指紋感測晶片封裝結構10整體的厚度為720μm。
相較於習知技術,本發明提供一種薄型化的指紋感測晶片封裝結構,以減少電子裝置配置指紋感測晶片時所需的容置空間,如此便可有效提升了電子裝置內部電子線路配置的靈活性及自由度。另一方面,以基板封裝取代現有環氧模壓樹脂的晶片封裝,因基板圍繞設置於指紋感測晶片的周緣,進而達到環狀補強的效果,使指紋感測晶片封裝結構在薄型化的同時仍能維持的良好的機械強度,且以基板封裝不會有材料脹縮比不同的問題,因此可避免指紋感測晶片封裝結構外觀翹曲的現象;故,本發明實為一極具產業價值之創作。
本發明得由熟悉本技藝之人士任施匠思而為諸般修 飾,然皆不脫如附申請專利範圍所欲保護。

Claims (15)

  1. 一種指紋感測晶片封裝結構,包括:一基板,具有一第一表面、一第二表面及貫穿該第一表面及該第二表面的一貫穿開口,該第二表面包括自該貫穿開口延伸出的至少一凹槽及至少一第二金屬接點,且該至少一凹槽用以容置一第一金屬接點;一指紋感測晶片,設置於該貫穿開口之中,且具有一上表面及一下表面,該下表面具有至少一焊墊;一蓋板,固設於該基板的該第一表面並覆蓋該指紋感測晶片的該上表面;以及一軟性電路板,設置於該基板的該第二表面,且該軟性電路板之表面具有至少一第三金屬接點,該至少一第三金屬接點對應於該至少一第二金屬接點,並與該至少一第二金屬接點電性連接;其中,該至少一焊墊藉由一導線與該第一金屬接點電性連接。
  2. 如申請專利範圍第1項所述之指紋感測晶片封裝結構,其進一步包括一補強板,該補強板設置於該軟性電路板相對於該至少一第三金屬接點之表面的另一表面上。
  3. 如申請專利範圍第1項所述之指紋感測晶片封裝結構,其中一膠體塗佈於該至少一焊墊、該導線及該第一金屬接點,該膠體為一底部填充膠。
  4. 如申請專利範圍第1項所述之指紋感測晶片封裝結構,其中一第一膠片層形成於該蓋板與該基板之該第一表面之間,用以黏合該基板及該蓋板。
  5. 如申請專利範圍第1項所述之指紋感測晶片封裝結構,其中該蓋板包括一膠水層,形成於對應該貫穿開口的位置,並用以黏合該指紋感測晶片的該上表面。
  6. 如申請專利範圍第2項所述之指紋感測晶片封裝結構,其中一第二膠片層形成於該軟性電路與該補強板之間,並用以黏合該軟性電路及該補強板。
  7. 如申請專利範圍第1項所述之指紋感測晶片封裝結構,其中該基板為:電木板、玻璃纖維板、塑膠板或陶瓷板。
  8. 如申請專利範圍第1項所述之指紋感測晶片封裝結構,其中該蓋板的材質為:陶瓷或玻璃。
  9. 如申請專利範圍第2項所述之指紋感測晶片封裝結構,其中該補強板的材質為:不銹鋼、鎢鋼、鋁或馬口鐵。
  10. 如申請專利範圍第1項所述之指紋感測晶片封裝結構,其中該基板的厚度介於295μm~305μm之間。
  11. 如申請專利範圍第10項所述之指紋感測晶片封裝結構,其中該基板的厚度為300μm。
  12. 如申請專利範圍第1項所述之指紋感測晶片封裝結構,其中該蓋板的厚度介於90μm~110μm之間。
  13. 如申請專利範圍第12項所述之指紋感測晶片封裝結構,其中該蓋板的厚度為100μm。
  14. 如申請專利範圍第2項所述之指紋感測晶片封裝結構,其中該補強板的厚度介於145μm~155μm之間。
  15. 如申請專利範圍第14項所述之指紋感測晶片封裝結構,其中該補強板的厚度為150μm。
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CN110942997B (zh) * 2019-11-15 2021-08-24 亿芯微半导体科技(深圳)有限公司 一种指纹识别芯片封装体及其制备方法
CN115312549A (zh) * 2021-05-05 2022-11-08 胜丽国际股份有限公司 传感器封装结构
CN118075978A (zh) * 2022-11-24 2024-05-24 庆鼎精密电子(淮安)有限公司 封装结构及封装结构的制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201416991A (zh) * 2012-10-16 2014-05-01 Wei-Ting Lin 電容式指紋感測器及其製造方法
TWM522419U (zh) * 2016-01-21 2016-05-21 Metrics Technology Co Ltd J 指紋辨識感測器
TW201626289A (zh) * 2015-01-05 2016-07-16 致伸科技股份有限公司 感測裝置
TW201627915A (zh) * 2015-01-19 2016-08-01 致伸科技股份有限公司 感測裝置之製造方法
TW201705039A (zh) * 2015-07-31 2017-02-01 致伸科技股份有限公司 指紋感測模組之封裝方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN204808363U (zh) * 2012-11-20 2015-11-25 韩国科泰高科株式会社 指纹传感器模块、具有此的便携式电子设备
CN104201116B (zh) * 2014-09-12 2018-04-20 苏州晶方半导体科技股份有限公司 指纹识别芯片封装方法和封装结构
TWI604388B (zh) * 2016-02-19 2017-11-01 致伸科技股份有限公司 指紋辨識模組及其製造方法
TWI596716B (zh) * 2016-06-27 2017-08-21 速博思股份有限公司 指紋辨識裝置
EP3288072A4 (en) * 2016-07-15 2018-05-23 Shenzhen Goodix Technology Co., Ltd. Fingerprint recognition module and preparation method therefor
ES2705159T3 (es) * 2016-08-16 2019-03-22 Guangdong Oppo Mobile Telecommunications Corp Ltd Ensamblaje de entrada y terminal
CN106653616A (zh) * 2016-11-22 2017-05-10 苏州晶方半导体科技股份有限公司 指纹传感芯片的封装方法以及封装结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201416991A (zh) * 2012-10-16 2014-05-01 Wei-Ting Lin 電容式指紋感測器及其製造方法
TW201626289A (zh) * 2015-01-05 2016-07-16 致伸科技股份有限公司 感測裝置
TW201627915A (zh) * 2015-01-19 2016-08-01 致伸科技股份有限公司 感測裝置之製造方法
TW201705039A (zh) * 2015-07-31 2017-02-01 致伸科技股份有限公司 指紋感測模組之封裝方法
TWM522419U (zh) * 2016-01-21 2016-05-21 Metrics Technology Co Ltd J 指紋辨識感測器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI785838B (zh) * 2021-05-18 2022-12-01 友達光電股份有限公司 指紋感測裝置

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