TW561599B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW561599B
TW561599B TW91123400A TW91123400A TW561599B TW 561599 B TW561599 B TW 561599B TW 91123400 A TW91123400 A TW 91123400A TW 91123400 A TW91123400 A TW 91123400A TW 561599 B TW561599 B TW 561599B
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TW
Taiwan
Prior art keywords
electrode pads
conductive pattern
connection
electrode
aforementioned
Prior art date
Application number
TW91123400A
Other languages
English (en)
Inventor
Tetsuro Asano
Mikito Sakakibara
Hideyuki Inotsume
Haruhiko Sakai
Shigeo Kimura
Original Assignee
Sanyo Electric Co
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Filing date
Publication date
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Publication of TW561599B publication Critical patent/TW561599B/zh

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Description

561599
五、發明說明（1) 【發明所屬之技術領域] 本發明係關於一種半導體裝置，特別是關於可 線接合之固定位置，以同一圖案之晶片與導電圖案，x㈢^ 輕易變更開關電路裝置之控制端子之引線端子配w p可 體裝置。 夏之半導 【先前技術】 在行動電話等用於移動體之通訊機器中，多使用斗 之微波，在天線的切換電路或收送訊的切換電路等方面广 則多使用可切換此等高頻訊號的開關元件（例如，日本 利特開平9- 1 8 1 642號）。該元件，多用以處理高頻，故使 用應用砷化鎵（GaAs)的場效電晶體（以下稱FET，（Fieid Effect Transistor)之情形較多，因此乃促進了將前述 開關電路本身予以積體化的單石微波積體電路（MM j C Monolithic Microwave Integrated Circuit)的開發 。 以往’在半導體裝置之封裝體上’係以在與引W同 一材料的島部進行晶粒黏接後，再進行樹脂模塑的構造最 為普遍。以下’以化合物半導體之GaAs開關電路裝置為例 以說明該半導體裝置。 ' ^ 第8圖，係顯示習知之化合物半導體開關電路裝置之 電路圖。第1FET1與第2FET2之源極（或汲極）連接於共通輸 入端子IN，而FETH、FET2之各閘極隔著電阻μ、R2分別連 接於第1及第2控制端子Ctl~~l、ctl-2，此外FET1、FET2之 汲極（或源極）則連接於第1與第2輸出端子OUT-1、OUT-2。 施加於第1及苐2控制端子ctl - 2的控制訊號為互補
314084.ptd 第8頁 561599 五、發明說明（2) 訊號，係在施加Η水平訊號側之FET導通時，將施加於共、 輸入端子IN的輸入訊號傳送至其中一方的輸出端子。電通 R1、R 2之目的係在防止高頻訊號經由閘極漏出而配置在， 成交流接地之控制端子Ct 1-1、CT1-2之直流電位對面。形 第9圖，係將化合物半導體開關電路裝置積體化之 合物半導體晶片的1範例。 將進行開關的FET1與FET2配設於GaAs基板之中夫部 並於各FET的閘極上連接電阻R卜R2 。此外，與共通輪’ 端子IN，輸出端子out卜OUT2對應之控制端子Ct 1-1、
Ctl-2的焊墊I、〇卜〇2、（：卜C2則配設於基板的周邊。此 外’虛線所示之第2層配線係與各FET的閘極同時形成之閘 極金屬層（Ti/Pt/Au)20，而實線所示之第3層配線係用以 進行各元件的連接與銲墊的形成之焊墊金屬層（Ti/Pt/Au) 40°歐姆接觸第1層基板之歐姆金屬層（AuGe/Ni/Au)係用 以形成各F E T的源極、汲極、以及各電阻兩端的取出電極 之金屬層，在第9圖中，因與焊墊金屬層重疊之故而未加 以圖示。 此外，第1 0圖，係顯示將控制端子Ct 1 - 1的位置由第8 圖移動至FET2側，將控制端子ct 1-2的位置由第8圖移動至 FET1側的開關電路圖。配合使用者的需求，有時必須組裝 與第8圖、第9圖所示圖案的邏輯電路（以下稱之為一般圖 案的開關電路裝置）相反的邏輯電路。換言之，係一種邏 輯電路，於訊號通過輸出端子〇UT1時，對遠離輸出端子 0UT1之控制端子Ctl-1施加例如3V、而對控制端子ctl_2施
314084.ptd 第9頁 561599 五、發明說明（3) 加0V，反之’當訊號流通於輸出端子0ϋΤ2時，則對遠離輸 出端子01^2之控制端子（：1：1 — 2施加3¥、而對控制端子（：1:1-1 施加0V的偏壓訊號，（以下稱之為反向控制開關電路）在該 情況下’必須變更晶片内的配置。 第1 1圖係將反向控制型開關電路裝置積體化之化合物 半導體之1範例。將進行開關的？5：11與FET2配設於GaAs* 板之中央部’並於各fet的閘極上連接電阻m、R2 。此 外，對應共通輸入端子IN，輸出端子〇Un、〇UT2，控制端 子ctl_l、ctl - 2的焊墊係設置於基板之周邊、FET^FET2 的周圍。此外，點線所示之第2層配線係在形成各FET之閘 & 極時同時形成之閘極金屬層（Ti/pt/Au)2〇，而實線所示之 第3層配線係用以連接各元件及形成銲墊之焊墊金屬層 (Ti/Pt/Au)30。歐姆接觸第1層基板之歐姆金屬層 (AuGe/Ni/Au)為用以形成各FE1^源極、汲極、以及各電 阻兩端的取出電極之金屬層，在n圖中，因與焊墊金屬層 重疊之故而未加以圖示。 晶片内部配置有與共通輸入端子I N、控制端子c t丨一 i 以及Ctl_2或輸出端子0UT1以及〇UT2對應的焊墊I、ci、 C 2、（Π、0 2。在反向控制型開關電路中，與第9圖相同， 與FET1的閘極與控制端子Ctl —丨對應的焊墊C1係以電阻R1 φ 連接，而與FET2的閘極與控制端子Ctl—2對應的焊墊。係 以電阻R2連接’但自第9圖起焊墊C1#移動至FET2側，而 焊墊C2則移動至FET1側。
561599 五、發明說明（4) (A)為上面圖，B-B線剖面圖顯示於第1 2圖（B)。
形成開關元件之化合物半導體晶片6 3利用銲錫等導電 漿7 0固定黏裝於引線架的島部6 2 e，化合物半導體晶片6 3 的各電極焊墊I、C卜C2、（H、02與引線62係藉由接合引 線6 4連接。藉此，使控制端子C11 - 1連接引線6 2 a、輸入端 子I N連接引線62b、控制端子Ctl- 2連接引線6 2 c、輸出端 子OUT 1連接引線62d、OUT2連接引線62f。固定有半導體晶 片63的島部62e形成GND端子。半導體晶片63的周邊部分係 由與金屬壓模形狀一致的樹脂7 5所被覆，而引線6 2的前端 部分則導出至樹脂75的外部。 W 【發明内容】 【發明所欲解決之課題】 為配合使用者的需求，如第1 1圖所示，有時須變換連 接於FET的控制端子Ctl-1與Ctl-2的位置或提供反向控制 型開關電路裝置，在此情況下，則必須從晶圓起重新投 入。然而，若因應需求而各別對應時，因晶圓的製作上必 須耗時1至2個月，組裝上又須耗時1個月左右的時間，而 導致無法迅速對應，且耗費巨額成本的問題。 此外，若將第9圖所示之一般圖案的開關電路裝置的 佈線變換為第1 1圖所示之反向控制型邏輯電路的佈線時， 因晶片内部無多餘空間，故須沿著晶片的外周配置電阻。 然而，若依照該種配置方式，則須在晶片之X方向（左右） 各擴大25// m，而在Y方向擴大5 0// m，因此將導致晶片尺 寸的加大。
314084.ptd 第 11 頁 561599 五、發明說明（5) 此外，在以 構造上，由於必 上，因此須採用 配合各種尺寸的 目前在；5夕半 其利用在局頻的 率）在25GHz以上 改善應用電路， 路相近的性能。 易，只好採用昂 體晶片的性能， 合物半導體晶片 換言之，藉由縮 課題。此外，即 低價化，若封裳 晶片縮小的優勢 之小型化亦為刻 【解決課題之手 本發明係鑑 其中，半導體梦 複數電極焊墊^ 焊墊個別對應之 之連接機構，♦ 田 至與導電圖案對 往之 須廣 可配 引線 導體 可能 的石夕 而能 以往 貴的 使之 在晶 小晶 使可 體之 ，因 不容 段】 於上 置係 半導 導電 導電 應之 化合物半 泛使用在 合較大晶 架而導致 晶片之性 性亦逐漸 半導體電 夠達到與 ，由於石夕 化合物半 具有利用 圓本身之 圓尺寸以 以達成化 外型仍維 此在追求 緩的課題 導體 各種 片尺 成本 能的 提南曰 日日體 使用 晶片 導體 的可 價格 達到 合物 持大 a曰 片 開關電路裝置的封裝體 不同大小的半導體晶片 寸的引線架。因採用可 的提高。 提昇上極為驚人，此外 。例如使用f τ(戴止頻 的局部振盪電路可透過 GaAsFET之局部振盈電 在高頻之利用上相當不 晶片’若能提高石夕半導 能性，則價格高昂的化 戰上當然不具競爭力。 低價化業已成為重要之 半導體晶片的小型化與 尺寸’便完全無法發揮 小型化的同時，封裝體 述問題而研發者，其目的在提供一種 具備有：絕緣性支撐基板；表面擁有 體晶片；配置於基板，與複數之電極 圖案，連接複數電極焊塾與導電圖宰 圖案中至少兩個導電圖案接近並延伸 至少兩個電極焊墊，並利用連接機構
第12頁 561599 五、發明說明（6) 連接至少兩個導電圖案與至少兩個電極焊墊時，係藉由選 擇其中一方的導電圖案，以切換與至少兩個電極焊墊對應 的連接端子的位置，以藉此解決問題。藉由上述方法，以 同一封裝體、同一晶片，即可同時提供一般的開關電路裝 置與反向控制開關電路裝置。此外由於係晶片尺寸之封 裝，故可達到晶片之小型化、及封裝體之小型化、而有助 於成本之刪減以及使用者側在安裝上的小型化。 【實施方式】 以下詳細說明本發明之實施形態。 本發明之半導體裝置係由：絕緣基板1 ;導電圖案2 ; 半導體晶片3 ;連接機構4 ;貫通孔5以及外部連接電極6所 構成。 參照第1圖至第4圖詳細說明本發明之第1實施形態。 第1圖（A )為配置於基板1的導電圖案2的一部份。基板 1係由陶瓷、玻璃環氧樹脂等所構成的大型絕緣基板，將 該基板以一片或數片重疊，當合計板厚為10 8至250// m 時，便具有可維持製造過程中之機械強度之板厚。 導電圖案2係由配設於絕緣基板1上的6條引線2所構 成，係與配置於半導體晶片上的電極焊墊呈對應配置。導 電圖案2以鍍金形成，其中的2條引線2延伸至點線所示之 半導體晶片的固定區域1 1，係以該2條引線2的兩端由半導 體晶片之固定區域1 1露出的形狀配置。半導體晶片的固定 區域1 1中並無相當於以往之島部的構造，半導體晶片係藉 由絕緣性樹脂固定於延伸的2條引線2上。各導電圖案2在
314084.ptd 第13頁 561599 、發明說明（Ό 一點鏈線所示的各射姑μ 部12連接配置。各封ΐ件區域10中為同一形狀，係由連 2mrax 0.8隨的矩形开，壯4件區域10例如擁有長邊X短邊1· 37mm，但該固定區域二固定區域U，例如為〇.30mfflx 〇. 此外，各封裝件區域ln::導體晶片的大小而有所不同。 的距離縱橫配置。前if門V電圖案2，互相以間隔1 0 m 此，各圖案2雖藉由全H隔形成安裝步驟的切割線。在 鍍，此時由於無連拯鍍形成，但亦可使用無電解電 案。 ^而要，因此可分別設置各導電圖 五 以 接 如第1圖（B)所示， 1 〇 0個）對應1個半導體 第2圖係表示半導 半導體開關電路裝置， 基板1上縱橫配置了複數個（例如 晶片的封裝件區域1 0。 體晶片3。半導體晶片3係為化合物 其背面為半絕緣性砷化鎵（GaAs)基
板。該開關電路裝置，將在GaAs基板上進行開關的FET1與 FET2配設於中央部，各FET的閘極17連接電阻m、R2 。此 外’對應共通輸入端子IN，輸出端子OUTH、OUT2的電極焊 墊I、（Π、02、以及分別對應控制端子Ctl-1、Ctl-2的電 極焊墊C卜C 2則配設於基板的周邊。控制端子用電極焊墊 C1係連接於FET1的閘極17，而控制端子用電極焊墊C2則連 接於F E T 2的閘極1 7。此外，控制端子用電極焊墊C1、C 2，
分別與控制端子控制端子C11 -1、C11 - 2連接。在此，在對 應輸入端子與輸出端子的電極焊墊中如後文所述其連接之 引線係呈固定。 此外，點線所示之第2層配線係在形成與各FET之通道
314084.ptd 第14頁 561599 五、發明說明（8) 區域1 4形成肖特基接合之閘極丨7時同時形成之閘極金屬層 (Ti/Pt/Ai〇20 ’而實線所示之第3層配線係用以連接各元 件的連接及形成辉墊之焊墊金屬層（Ti/pt/Au)4〇。歐姆接 觸第1層基板之歐姆金屬層，（AuGe/Ni/Au)係用以形成各 FET的源極1 3、汲極1 5、以及各電阻兩端之取出電極之金 屬層’在第2圖中’因與焊墊金屬層重疊之故而未加以圖 不。此外，因本發明之實施形態之電路圖係與第8圖相 同，故省略其說明。 第3圖係表示將半導體晶片3固定於絕緣基板1之範 6t第3圖（A)所示，由鍍金層所形成之引線2c、2&上1 Ϊ雷ί ί體晶片3,引線2C、2a係接近並延伸至控制端子 式配蓄干墊C卜C2，並以兩端分別由晶片的端部露出之： 1 ^ 。在此’引線2c、2a所露出位置雖不限定於圖上； ^位置’但引線2c以及23由晶片#部所露出之部 ς ^ 1於所對應之2個電極焊墊的附近，同時 接合時所需的充分面積。 丁 引#弓i線2b對應輸入端子ΙΝ、引線2d對應輸出端子out 1 、、對應輸出端子〇UT2，而引線以係對應控制端子 、引線2 a係對應控制端子c 11 _；[。半導體晶片俜 由絕緣性黏合劑固定於引線2c、2a上。 係“ ^合線4，係用以連接半導體晶片3的各電極焊墊！、 曰 雨2 C卜c2與引線2。使控制端子用電極焊墊c 1與由 曰硌出之引線2 a連接，並使控制端子用電極焊墊c 2與】
561599 五、發明說明（9) --~----- ί = ΐ出之引線2c連接。此外，將輸人端子用電極焊墊I =引線2b、㉟出端子用電極焊墊01連接於引線2d、
出、子用電極焊墊〇2連接於引線2f。此外，丰導辦曰y Q pi · 丁 f 曰曰方 j 、内面為半絕緣性基板而引線2e則作為GND電位。 於该位置上藉由引線接合，使引線2c與FET2的控制端 子用電極焊墊C2連接以對應控制端子Ctl —2，而使引線^ 與FET1的控制端子用電極焊墊C1連接並與控制端子[η ^ 對應。f即，可在與以往為同一晶片圖案（一般圖案）的情 況下’貫現第1 〇圖及第丨丨圖所示之反向控制型之開關 裝置。 另一方面’第3圖（B)係表示以第8圖之電路圖所示之 身又圖案使用該晶片時的情況。此時，係讓控制端子用電 極焊塾C1與由晶片露出之附近的引線2c連接，而讓控制 端子用電極焊墊C 2與由晶片露出之附近的引線2 a連接。 在該位置上藉由引線接合，使引線2c與FET1的控制端 子用電極焊墊C1連接並與控制端子ctl-1對應，而使引線 2a與FET2的控制端子用電極焊墊c2連接而與控制端子 C11 - 2對應。 如上述一般，藉由使配置於絕緣基板上之控制端子用 的導電圖案中延伸至晶片下方，使兩端由晶片端露出，再 藉由選擇以接合線連接的引線，即可在同一晶片圖案、同 一導電圖案下，可簡易地將連接於FEH、FET2的控制端子 C11 - ；l、C11 - 2的位置予以切換。亦即，可藉由將與2個引 線連接的接合線的位置予以切換，即可使2個控制端子用
ill _ ¥ 314084.ptd 第16頁 561599 五、發明說明（ίο) 電極焊墊C卜C2的排列順序以及所對應之控制端子 C11 - ：l、C11 - 2的排列順序以順向/逆向交錯的方式來配 置。因此，即使在同一晶片圖案（一般的晶片圖案）、同一 導電圖案的情況下，同樣可僅藉由接合線的連接端的切 換，而完成一般的開關電路裝置與反向控制型的開關電路 裝置。 在此，由於該導電圖案2在鍍覆圖案的形成上係使用 厚膜印刷，故可將圖案（引線）間的最小間隔設定為75// m。此與在採用習知之引線架時，沖壓方式的引線架沖切 界限為引線架的板厚（1 5 0/z m )x 0 . 8，其最小間隔為1 2 0// m的情況相較，可大幅縮小引線間的距離，而有助於達成 封裝體之小型化的目的。 第4圖，顯示將上述之化合物半導體晶片3組裝於封裝 體後所形成之化合物半導體開關電路裝置，為第3圖之A-A 線所示之剖面。 基板1中，設有對應各引線2的貫通孔5。貫通孔5貫通 基板1，其内部係埋設於鎢等導電材料。此外，其背面設 有對應各貫通孔5的外部連接電極6。 化合物半導體晶片3，係利用絕緣性黏合劑5 0以橫跨 在2條引線2 a、2 c上的方式固定，晶片3的各電極焊墊I、 01、02、CM、C2分別介由焊線4、引線2、貫通孔5，與對 應各位置的外部連接電極6進行電性連接。 亦即6個外部連接電極6，係以對應封裝體外形的中心 線呈左右（上下）對稱的圖案配置。具體而言，係沿著封裝
314084.ptd 第17頁 561599 五、發明說明（11) 體側面的一邊，配置控制端子C 11 - 1 (或C11 - 2 )、輸入端子 IN、控制端子Ct 1-2 (或Ct 1-1 )，並沿著封裝體側面的另一 邊，依序配置輸出端子ουπ、GND端子、輸出端子0UT2。 封裝體周圍的4個側面，係由樹脂層1 5與絕緣基板1的 切斷面所形成，封裝體的上面由平坦化之樹脂層1 5表面所 形成，而封裝體的下面係由絕緣基板1的背面側所形成。 該化合物半導體開關電路裝置，其絕緣基板1上面被 覆有約0 . 3nim左右的樹脂層1 5以密封化合物半導體晶片3。 化合物半導體晶片3擁有約1 3 0// m程度的厚度。 此外，封裝體的表面側為全面樹脂層1 5，而内面側的 絕緣基板1的外部連接電極6，係以左右（上下）對稱的圖案 配置，因電極的極性不易判斷，故可在樹脂層1 5的表面側 形成凹部或印刷等，但以刻設顯示極性的方式較佳。 如上所示，本發明之特徵為係為不使用沖切引線架之 晶片尺寸封裝體，將控制端子所連接的2條引線延伸，並 於其上固定半導體晶片，使各引線兩端由晶片的端部露 出。藉此可在使用同一晶片圖案、同一導電圖案的情況 下，僅藉由切換以接合線連接的引線，即可輕易地完成一 般圖案與反向控制型圖案，並迅速廣泛地回應使用者的需 求。 <· 在將晶片固定於習知的沖切引線架的構造下，為實現 反向控制型圖案必須變更晶片的圖案，如此一來除了會導 致半導體晶片尺寸的增大外，亦會使封裝體外型變大，但 根據本發明之構造，不但可實現封裝體小型化的目的，同
314084.ptd 第18頁 561599 五、發明說明（12) 時因半導體晶片僅需要一種圖案，故可大幅降低成本。 在此，參照第5圖與第6圖以表示本發明之第2實施形 態。平面圖因與第3圖所示之第1實施形態為相同之内容故 加以省略，第5圖為第3圖的A-A線剖面圖。第2實施形態， 係為將苐1貫施形態之晶片尺寸封裝（CSP Chip Scle Package)多晶片模組化之步驟，其乃將導電圖案包覆在形 成支撐基板之絕緣性樹脂中之構造。 形成支撐基板的絕緣樹脂2 1，將半導體晶片2 3與複數 的導電圖案（引線）2 2完全地被覆，於引線2 2之間的分離溝 3 1中填充絕緣性樹脂2 1 ’使之與引線2 2側面的彎曲構造 (圖中雖省略該構造，但引線側面實際上呈彎曲狀）崁合且 緊密地接合。此外引線22係藉由絕緣性樹脂21支撐广二 定在引線22上的半導體晶片23一併被覆，以同時進 塑。在樹脂的材料中，環氧樹脂等熱硬二 轉模塑法獲得，而聚醯亞胺樹脂、聚苯硫醚 错由移 (Pol yphany 1 cnc siilfij ,, 成型獲得。 sulilde)專熱可塑性樹脂則可藉由射出 絕緣性樹脂2 1 m ώ： 24的最頂部以可被覆二^，係由半導體晶片23的接合引線 配合強度所需使之；；的程度進行調整。其厚度可 樹脂21的表面平坦化:5夂潯。此外，利用退火使絕緣性 面積時，特別在作為。二=，當絕緣性樹脂21具有寬闊之 樹脂21的模塑樹脂心,的導電箱30與形成絕緣性 低導致成形收縮率’s、恥脹係數或回流烊接後因溫度降 差異下，會造成導電落_弯曲。換 561599 五、發明說明（13) 〜~ 吕之’係為了抑制、纟巴緣性樹脂2 1表面產生彎曲而藉由退火 使其平坦化。 接合線2 4，係用以連接半導體晶片2 3的各電極焊墊 I、0卜02、（：卜C2與各引線22，藉由利用熱壓 (thermocompress ion)之球形銲合（Bal 丨 Bonding)與利用 超音波之楔形銲合/(Wedge Bonding)而一併進行引線接 合，藉此，可使控制端子Ctl-1、輸入端子IN、Ctl-2、輸 出端子0UT1、OUT 2與各引線2 2連接。引線中的1條係連接 於半導體晶片的背面，形成GND (接地）端子。 導電圖案2 2，係由絕緣樹脂2 1所包覆，並與配置於半 導體晶片2 3上之電極焊墊對應配設。固定區域中並無相當 於習知之島部的構造，半導體晶片2 3係藉由絕緣性接合劑 5 0固定於延伸在固定區域的略中央部的引線2 2 a、2 2 c上。 如後所述，如第5圖（B)所示，導電圖案22係為導電箔 3 0。設有分離溝3 1的導電箔3 0，係藉由研磨、研削、姓 刻、雷射之金屬蒸發等，以化學以及/或物理方式去除背 面，而分離為導電圖案2 2。藉此以形成在絕緣性樹脂2 1上 露出導電圖案2 2的背面的構造。填充於分離溝3丨的絕緣性 樹脂2 1的表面與導電圖案2 2的表面，係形成實質為一致的 構造。 半導體晶片2 3，因與第1實施形態相同之故而省略其 詳細說明，在此為化合物半導體之開關電路裝置，其背面 形成半絕緣性的GaAs基板。因其為開關電路裝置之故，晶 片之表面有與輸入端子IN、控制端子ctl-1、Ctl-2、輸出
Bill· 314084.ptd 第20頁 561599 五、發明說明（14) ' ' ----— 端子ΟϋΠ、0UT2連接之5個電極焊墊卜c卜C2、 環繞晶片夕卜圍之方式配置。此外，係 1 連接FEH的控制端子用電極焊塾⑶系 卜連f /其 接FET2的控制端子用電極焊墊。2則是與cti_j:。 絕緣性接合劑固定在形成控制端子ctl ut cu_f错由 22a、22c上，並利用•合線24 二線 外部連接電極26，係利用光阻導 預定的位置上設置開口二U ί:ϊ 行對準之特徵。踢4表面張力直接進行水平移動以自 « ㈣第的成Λ電圖]案之導電箱3 °。為顧及之後的 此係採用=H ?岐30 0"的程度為佳，在 "m以下，。要i J :)的銅备。但不管是以上或10 Μ即可。藉此在Λ 導電箱30的厚度為淺的分離溝 區域之封穿I*單—^矩形之導電箔30上形成有多數固定 方式排列ϋ 多數個（在此為4至5個）間隔之 示之1個5 ϋ為單具元體^導電圖案22。本圖乃將第6圖（Α)所 裝件區域^ ΛΓ ^以放大之圖。虛線所示部分為1封 以矩陣狀排列。導固tY案體1兀3二多數的導電圖案22係 的區域的導電炫 \ ^ 等至夕形成導電圖案22以外 該導電箱3。之：料:成:分^1以做為導電圖案2。 性、電鍍性等牲二、擇，係考慮焊料的附著性、接合 專特性，其材料多採用，例如以銅（Cu)為主材
314084.ptd 第21頁 561599 五、發明說明（15) __
料的導電箔、以鋁（A (F e - N i )等合金所形 ·、、、主材料的導電箔或由鐵-鎳 此外，由於導電圖、‘電箔。 於以往技術中，沖切θ ” 2 2係利用姓刻形成，因此，相較 間距離的界限之情形，線架之板厚（1 5 〇// m )χ 〇 · 8為圖案 離，且有助於達成封壯本發明不僅可大幅縮小圖案間的距 第2實施形態的特\7、型化的\的° Φ 以形成導電圖案2 2的道。、·在被覆絶性樹脂2 1之前，係 基板之導電箔3〇係電$磘30作為支撐基板，而形成支撐 省構成材料之優點:料之必要材料。故具有可大幅節 此外，由離2達到成本之降低。 厚度，故導電箱30並ί ^ 成較導電箱3〇之厚度為淺的 具有1特：=電圖案22。因此，乃 €緣性樹脂2 la# 作為片狀V電箔30使用，並在模塑 ；b 〇 21時，使搬送至模具、及安裝於模具的作業簡 爲板ΐί 4本^施形態中係針對導電落30進行說日月，但 “同d 基板、銅引線架等材料所構成時亦具 六木發明卜Φ 7圖所不’引線可沿著晶片的外周配置。 ^ #子用π i错由切換接合線的連接處來選擇分別對應控 制，用烊墊Cb C2的控制端子Ctl-1、cti-2之位置，只 要使^ ^ 2a與2c延伸接近至控制端子用焊墊ci、C2即可。 V .1如圖所示即使是沿著晶片外周配置之圖案，亦 玎褚、擇其中一方的引線，切換分別對應2個電極焊墊
314084.ptd 第22頁 561599 五、發明說明（16) 的連接端子的位置。 在此，可在任一實施形態中安裝的元件，不限於化合 物半導體開關電路裝置、其他積體電路、電晶體、二極管 等半導體晶片，亦可以是晶片電容器、晶片電阻、晶片感 應器等被動元件，另外，雖會使厚度增加，但亦可是 CSP、球腳格狀陣列（BGA， Ball Grid Array)(BGA)等面朝 下的半導體元件等表面安裝元件。 【發明之效果】 本發明之特徵係不使用沖切引線架之CSP，將形成控 制端子的2個導電圖案延伸至半導體晶片的下方，並由晶 片露出端部。 藉此，第1，可藉由線接合之固定位置，而以同一圖 案之晶片、及導電圖案，可輕易地變更開關電路裝置的控 制端子的引線端子配置。換言之，藉由使對應控制端子的 引線通過晶片的下方，由晶片端露出，再以接合線選擇該 引線的其中一方，即可切換對應控制端子用電極焊墊的連 接端子的位置。在使用習知沖切引線架的構造下，由於必 須變更晶片内的圖案，因此將導致晶片尺寸增大並提高成 本。但根據本發明之構造，即可在同一晶片圖案（一般的 晶片圖案）、同一導電圖案下，僅藉由切換接合線的連接 端，即可完成一般的開關電路裝置與反向控制型開關電路 裝置。若依照習知之方式，需變更晶片内的圖案，因此由 晶圓之製作開始需耗費1至2個月的時間，而在組裝上則需 要1個月的時間，但若根據本發明之構造，則只須變更接
314084.ptd 第23頁 561599 五、發明說明（17) 合位置而能夠以1/6程度的周轉時間（TAT， Turn Around T i me )迅速地對應。換言之，本發明乃具有可迅速、且以 十分低廉的成本彈性對應使用者之需求的優點。 第2 ’封|體構造為CSP，相較於以往使用引線進行樹 脂模塑的封裝體構造，可大幅地將封裴體尺寸小型化。以 往因廣泛使用沖切引線架，而對晶片尺寸使用不必要的過 大引線，同時會使引線導出模塑樹脂外側，而使封裝體外 形變得過大，但若採用csp，即可將大小抑制在最小範圍 的λ!、。& 7¾ 囷案取小間隔，藉此可達成封裝體 ^ i化此乃因為相對於以往採用沖切引線_，利用中 壓進行沖切時的界限為用彳m卞，利用冲 鍍的厚膜印刷、咬是導雷:的^8"m，而本發明係利用電 言，在引線架的㈡刻形成圖案之故。具體而 至75以m，能對封筆 ，原本為I20"—最小間隔縮小 第4,特別是= =有助益。 裝置時，可藉由將ri古相七日曰4片為化合物半導體開關電路 CU-卜CU-2以及GN:子/配形成之電位之控制端子 Frequency)線之於 山 於形成射頻RF(Radio 而形成截止高心= 之間， 點。 此具有提幵隔離特性之優
561599 圖式簡單說明 【圖式簡單說明】 第1圖為用以說明本發明之（A )平面圖、（B)斜視圖。 第2圖為用以說明本發明之平面圖。 第3圖為用以說明本發明之平面圖。 第4圖為用以說明本發明之剖面圖。 第5圖為用以說明本發明之剖面圖。 第6圖為用以說明本發明之平面圖。 第7圖為用以說明本發明之平面圖。 第8圖為用以說明先前技術之電路圖。 第9圖為用以說明先前技術之平面圖。 第1 0圖為用以說明先前技術之電路圖。 第1 1圖為用以說明先前技術之平面圖。 第1 2圖為用以說明先前技術之（A )平面圖、（B )剖面 圖0 1 絕緣基板 2 導電圖案（引線） 2 a、2 c、6 2 引線 3 ^ 23 半導體晶片 [24' 64 接合線 5 貫通孔 6 外部連接電極 10 封裝件區域 11 固定區域 12 連接部 13 源極 14 通道區域 15 没極（樹脂層） 17 閘極 20 閘極金屬層 21 絕緣樹脂
314084.ptd 第25頁 561599 圖式簡單說明 22 導電 27 光阻 30 導電 31 分離 40 鮮塾 62e 島部 63 化合 70 導電 Cl > C2 控制 I、（Η、02 電極 Ctl-1> Ctl-2 控制 FET卜 FET2 IN 輸入 Oim、OUT2 輸出 圖案（引線）26 劑 箔（銲塾金屬層） 溝 3 2 金屬層 50 物半導體晶片 漿 7 5 端子用電極銲墊 銲墊 端子
GND 端子 FH、 端子 外部連接電極 封裝體單元 絕緣性黏合劑 導出樹脂 端子（接地端子 R2電阻
314084.ptd 第26頁

Claims (1)

  1. 561599 六、申請專利範圍 1. 一種半導體裝置，係具備： 絕緣性支撐基板； 表面具有複數電極焊墊之半導體晶片； 配設於前述基板上，與前述複數之電極焊墊個別 對應之導電圖案；及 用以連接前述複數電極焊墊與前述導電圖案之連 接裝置， 其特徵為：前述導電圖案中至少有兩個導電圖案 係接近並延伸至與該導電圖案對應之至少兩個前述電 極焊墊，在利用前述連接裝置連接前述至少兩個導電 圖案與前述至少兩個電極焊墊時，係藉由選擇其中一 方的導電圖案，以切換對應前述至少兩個電極焊墊之 連接端子的位置。 2. 如申請專利範圍第1項之半導體裝置，其中，前述半導 體晶片之背面係由半絕緣性之化合物半導體基板所構 成。 3. 如申請專利範圍第1項之半導體裝置，其中，前述半導 體晶片係藉由絕緣性樹脂固定於至少兩個導電圖案 上，而前述至少兩個導電圖案的兩端則分別露出於前 述晶片的端部。 4. 如申請專利範圍第1項之半導體裝置，其中，係藉由切 換與前述至少兩個電極焊墊連接的連接機構的位置， 使前述至少兩個電極焊墊的排列順序與所對應之前述 連接端子的排列順序得以順向/逆向之方式配置。
    314084.ptd 第27頁 561599 六、申請專利範圍 5 ·如申請專利範圖楚 ..... 妒曰tl盔p日 弟員之半導體裝置，复由 >、f主莫 體曰曰片為開關電路裝置， /、中，則述丰V 6. 子係連接於前$ & + ^述開關包路裝置的控制端 一 兩個導電圖案。 千♦體I置，係具備： 絕緣基板； 之化合物ΐί J板表面、表面擁有複數電極焊墊 塾個= = J板表面’與前述複數之電極焊 用乂連接前述複數電極焊聲盘 接機構； 电位斗墊與則述導電圖案之連 對應前述導電圖幸 + a 孔； α案且貝通則述絕緣基板之貫通 對應該貫通孔而配置於前述 連接電極， 以4巴、家暴板者面之外部 、其特徵為：前述導電圖案中的兩個導雷 近並延伸至與該導電圖案對應之兩圖木係接 在利用前述連接機構連接前述兩個；圖| :焊墊， ;電極焊塾時，係藉由選擇其中一=述兩 換對應前述兩個電極焊墊的連接端子圖案，切 電極的位置。 吨外部連接 一種半導體裝置，係具備： 絕緣樹脂； 由該絕緣樹脂所包覆，表 m擁有複數電極焊墊之
    ^4084.ptd 第28頁 561599 六、申請專利範圍 化合物半導體晶片； 由前述絕緣樹脂所包覆，、 個別對應之導電圖案； 〜則述複數之電極焊墊 用以連接前述複數電極二 接機構； 墊〇别述導電圖案之連 與前述絕緣樹脂之背面 之外部連接電極； 斤路出的導電圖案相對應 其特徵為··前述導電圖案 近並延伸至與該導電圖案廡、兩個導電圖案係接 在利用前述連接機構連接前;^ f個前述電極焊墊， 個電極焊墊時，係藉由選擇^中電圖案與前述兩 換形成與前述兩個電極焊墊^=的導電圖案，切 部連接電極的位置。 、…連接端子的前述外 8·=申請專利範圍第6項或第7項之半 刖述化合物半導體晶片係豆衷置，其中， 兩個導雷囝安μ 1 +係精由絕緣性樹脂固定於前述 _方4山&圖木上，則述兩個導電圖案係由前述晶片的 9·如^:延：至另一方的端部而由前述晶片露出。 信一明專利範圍第6項或第7項之半導體裝置，其中， 置精由切換與丽述兩個電極焊墊連接的連接機構的位 ’使珂述兩個電極焊墊的排列順序與所對應之前述 I n f接端子的排列順序得以順向/逆向之方式配置。 •二申睛專利範圍第6項或第7項之半導體裝置，其中， II Γ述化合物半導體晶片之背面係半絕緣性基板。 • σ申凊專利範圍第6項或第7項之半導體裝置，其中，
    314084.ptd
    561599
    314084.ptd 第30頁
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI508362B (zh) * 2008-02-14 2015-11-11 Viasat Inc 積體波導封裝之系統及方法
US9426929B2 (en) 2010-08-31 2016-08-23 Viasat, Inc. Leadframe package with integrated partial waveguide interface

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4765004B2 (ja) 2006-09-04 2011-09-07 富士電機株式会社 半導体装置およびその製造方法
JP5809500B2 (ja) 2011-09-16 2015-11-11 ルネサスエレクトロニクス株式会社 半導体装置
CN103928431B (zh) * 2012-10-31 2017-03-01 矽力杰半导体技术(杭州)有限公司 一种倒装封装装置
CN110892522B (zh) * 2017-08-01 2023-09-12 株式会社村田制作所 高频开关
US20210376563A1 (en) * 2020-05-26 2021-12-02 Excelitas Canada, Inc. Semiconductor Side Emitting Laser Leadframe Package and Method of Producing Same

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4595945A (en) * 1983-10-21 1986-06-17 At&T Bell Laboratories Plastic package with lead frame crossunder
EP0162521A3 (en) * 1984-05-23 1986-10-08 American Microsystems, Incorporated Package for semiconductor devices
US4612564A (en) * 1984-06-04 1986-09-16 At&T Bell Laboratories Plastic integrated circuit package
US4937656A (en) * 1988-04-22 1990-06-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US5976912A (en) * 1994-03-18 1999-11-02 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
JPH08148603A (ja) * 1994-11-22 1996-06-07 Nec Kyushu Ltd ボールグリッドアレイ型半導体装置およびその製造方法
US6066890A (en) * 1995-11-13 2000-05-23 Siliconix Incorporated Separate circuit devices in an intra-package configuration and assembly techniques
US5691568A (en) * 1996-05-31 1997-11-25 Lsi Logic Corporation Wire bondable package design with maxium electrical performance and minimum number of layers
US5825628A (en) * 1996-10-03 1998-10-20 International Business Machines Corporation Electronic package with enhanced pad design
US5907769A (en) * 1996-12-30 1999-05-25 Micron Technology, Inc. Leads under chip in conventional IC package
US6103547A (en) * 1997-01-17 2000-08-15 Micron Technology, Inc. High speed IC package configuration
US6054754A (en) * 1997-06-06 2000-04-25 Micron Technology, Inc. Multi-capacitance lead frame decoupling device
JP2954110B2 (ja) * 1997-09-26 1999-09-27 九州日本電気株式会社 Ｃｓｐ型半導体装置及びその製造方法
JP4037589B2 (ja) * 2000-03-07 2008-01-23 三菱電機株式会社 樹脂封止形電力用半導体装置
TW530455B (en) * 2001-04-19 2003-05-01 Sanyo Electric Co Switch circuit device of compound semiconductor
JP2003204009A (ja) * 2001-11-01 2003-07-18 Sanyo Electric Co Ltd 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI508362B (zh) * 2008-02-14 2015-11-11 Viasat Inc 積體波導封裝之系統及方法
US9426929B2 (en) 2010-08-31 2016-08-23 Viasat, Inc. Leadframe package with integrated partial waveguide interface

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