TW550818B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW550818B
TW550818B TW091115771A TW91115771A TW550818B TW 550818 B TW550818 B TW 550818B TW 091115771 A TW091115771 A TW 091115771A TW 91115771 A TW91115771 A TW 91115771A TW 550818 B TW550818 B TW 550818B
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Taiwan
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gate electrode
semiconductor device
source
insulating film
gate insulating
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TW091115771A
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English (en)
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Eiji Nishibe
Shuichi Kikuchi
Masaaki Momen
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Sanyo Electric Co
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

550818 五、發明說明(1) 【發明所屬技術領域】 本發明係關於半導體裝置,詳言之,關於藉由電晶體 構造的多角形化,可防止弱反轉漏洩之同時,亦可微細化 之技術。 【習知之技術】 第3圖及第4圖係用以說明習知半導體裝置之剖視圖及 俯視圖。 圖中,5 1係為一導電型,例如P型半導體基板,介由 該基板5 1上之元件分離膜5 2以外的區域所形成之第1閘極 絕緣膜5 3,以及比該第1閘極絕緣膜5 3厚的第2閘極絕緣膜 5 4,形成有閘極電極5 5。 又,以介由上述第2閘極絕緣膜5 4鄰接於上述閘極電 極5 5之方式,形成有低濃度的N型源極/汲極區域(N -層、 漂移區域)5 6、5 7。 從上述第2閘極絕緣膜5 4到上述元件分離膜5 2間,形 成有高濃度的N型源極/汲極區域(N +層)5 8、5 9。 6 0係為通道區域。尚且,上述構造的半導體裝置係為 所謂的L0C0S偏置型半導體裝置。 如上述,習知電晶體形狀基本上為長方形。而且,為 了抑制弱反轉漏泡的發生,如第4圖所示,由N -層5 6、5 7 突出為凸狀的凸部分(參照第4圖所示之陰影線區域)是 必要的。 【發明所欲解決之問題】 如上述,習知的半導體裝置,為了抑制弱反轉漏洩的
313869.ptd 第6頁 550818 五、發明說明(2) 發生,第4圖所示之凸部分是必要的,而會有可實現之最 小的電晶體尺寸S2僅有此凸部分變大的問題。 因此,高财壓邏輯部分,會成為驅動能力上形成必要 以上的電晶體尺寸,並且會有晶片尺寸變大的缺點。 【解決問題之方案】 於此,有鑒於上述問題,本發明之半導體裝置係為在 具有:於一導電型半導體基板上,介由閘極絕緣膜而形成 的閘極電極,以及以與該閘極電極相鄰接之方式形成的逆 導電型源極/汲極區域,其特徵在:上述閘極電極與源極/ 汲極區域係形成多角形形狀。 又,上述閘極電極與源極/汲極區域係形成8角形形 狀。 【發明之實施形態】 以下,參照圖面說明關於本發明半導體裝置的一實施 形態。 第1圖及第2圖係用以說明本發明半導體裝置的剖視圖 及俯視圖。 圖中,1係為一導電型,例如P型半導體基板,介由該 基板1上元件分離膜2以外的區域所形成之第1閘極絕緣膜3 及比該第1閘極絕緣膜3厚的第2閘極絕緣膜4,形成有閘極 電極5。 又,以介由上述第2閘極絕緣膜4鄰接於上述閘極電極 5之方式,形成有低濃度的N型源極/汲極區域(N -層、漂 移區域)6、7。
313869.ptd 第7頁 550818 五、發明說明(3) 從上述第2閘極絕緣膜4到上述元件分離膜2間,形成 有高濃度的N型源極/汲極區域(N +層)8、9。 1 0係為通道區域。尚且,上述構造的半導體裝置係為 所謂的L0C0S偏置型半導體裝置。 於此,本發明的特徵如第2圖所示,係以電晶體形狀 成為多角形(本實施形態中為8角形)形狀之方式構成。 如上述,本發明中以多角形(八角形)形成構成電晶 體之閘極電極5、通道區域1 0、源極/汲極區域(N -層) 6、7之各構成要素的形狀,據此不會造成習知的電晶體尺 寸增大,並可設置相當於習知構造的凸部分之弱反轉漏洩 防止區域(第2圖所示之陰影線區域)。尚且,上述源極/ 汲極區域(N+層)8、9的形狀亦可以成為多角形(8角 形)形狀之方式構成。 據此,電晶體單體中的最小電晶體尺寸S 1,比習知構 造的電晶體尺寸S 2還小,可配合必要的驅動能力之最小尺 寸來設計高耐壓邏輯部分。 此外,亦可使各電晶體間的密集度增大,使晶片全體 的面積縮小。 因為電晶體各邊的端部,可緩和至較習知的9 0度更多 (例如1 3 5度),所以可緩和電界集中而達成高耐壓化。 尚且,本實施形態中,說明關於L0C0S偏置型半導體 裝置,然而本發明並不限定於此,亦可應用於具有各種構 造之半導體裝置。 【發明之效果】
313869.ptd 第8頁 550818 五、發明說明(4) 根據本發明,可使電晶體單體中的最小電晶體尺寸變 小,也可配合必要驅動能力之最小尺寸來設計高耐壓邏輯 部分。 此外,亦可使各電晶體間的密集度增大,使晶片全體 的面積縮小。 因為電晶體各邊的端部,可緩和至較習知的9 0度更多 (例如1 3 5度),所以可緩和電界集中而達成高耐壓化。
313869.ptd 第9頁 550818 圖式簡單說明 【圖面之簡單說明】 第1圖係表示本發明一實施形態的半導體裝置之剖視 圖。 第2圖係表示本發明一實施形態的半導體裝置之俯視 圖。 第3圖係表示習知半導體裝置之剖視圖。 第4圖係表示習知半導體裝置之俯視圖。 [元件符號之說明] 卜51 P型半導體基板 3、5 3 第1閘極絕緣膜 4、54 第2閘極絕緣膜 6、7、5 6、5 7 N型源極/没極區域(N -層) 8、9、5 8、5 9 N型源極/沒極區域(N +層) 10、6 0 通道區域 52 元件分離膜 55 閘極電極 S卜S 2電晶體尺寸
313869.ptd 第10頁

Claims (1)

  1. 550818 六、申請專利範圍 1. 一種半導體裝置,具備有:於一導電型半導體基板上 介由絕緣膜所形成的閘極電極,以及與該閘極電極相 鄰接之方式形成的逆導電型的源極/汲極區域,其特徵 在: 上述閘極電極與源極/汲極區域係形成多角形形 狀。 2. 如申請專利範圍第1項之半導體裝置,其中,上述閘極 電極與源極/汲極區域係形成8角形形狀。
    313869.ptd 第11頁
TW091115771A 2001-08-09 2002-07-16 Semiconductor device TW550818B (en)

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Publication number Priority date Publication date Assignee Title
JP4849504B2 (ja) * 2005-03-29 2012-01-11 ラピスセミコンダクタ株式会社 半導体装置、その製造方法、出力回路および電子機器
KR100817084B1 (ko) * 2007-02-02 2008-03-26 삼성전자주식회사 고전압 트랜지스터 및 그 제조방법
JP5141069B2 (ja) * 2007-03-28 2013-02-13 株式会社リコー 半導体装置
US7982247B2 (en) * 2008-08-19 2011-07-19 Freescale Semiconductor, Inc. Transistor with gain variation compensation

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GB1142674A (en) * 1966-02-18 1969-02-12 Mullard Ltd Improvements in and relating to insulated gate field effect transistors
US3427514A (en) * 1966-10-13 1969-02-11 Rca Corp Mos tetrode
JPH0669418A (ja) * 1992-08-21 1994-03-11 Fujitsu Ltd 半導体装置
JP2800884B2 (ja) * 1995-10-27 1998-09-21 日本電気株式会社 横型dsaパワーmosfetを備えた半導体装置
JP4032443B2 (ja) * 1996-10-09 2008-01-16 セイコーエプソン株式会社 薄膜トランジスタ、回路、アクティブマトリクス基板、液晶表示装置
US6140687A (en) * 1996-11-28 2000-10-31 Matsushita Electric Industrial Co., Ltd. High frequency ring gate MOSFET
KR100241523B1 (ko) * 1996-12-28 2000-02-01 김영환 플래쉬 메모리 소자 및 이를 이용한 프로그램, 소거 및 독출방법

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US20030030105A1 (en) 2003-02-13
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KR100482717B1 (ko) 2005-04-13

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