TW543090B - Method of fabricating high melting point metal wiring layer, method of fabricating semiconductor device and semiconductor device - Google Patents

Method of fabricating high melting point metal wiring layer, method of fabricating semiconductor device and semiconductor device Download PDF

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TW543090B
TW543090B TW091110623A TW91110623A TW543090B TW 543090 B TW543090 B TW 543090B TW 091110623 A TW091110623 A TW 091110623A TW 91110623 A TW91110623 A TW 91110623A TW 543090 B TW543090 B TW 543090B
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layer
mentioned
wiring layer
point metal
semiconductor device
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TW091110623A
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Shigenori Kido
Takeshi Kishida
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/263—Bombardment with radiation with high-energy radiation
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Description

543090
炎、發明說明（1) [發明所屬之技術領域] 本發明一般有關於尚炼點金屬布線層之製造方法，特別 有關於不使用光抗蝕劑就可以進行圖型製作之改良之高炫 點金屬布線層之製造方法。本發明更有關於包含有用Z形 成該高熔點金屬布線之步驟之半導體裝置之製造方法。^ 發明更有關於利用該種方法所獲得之半導體裝置。 [習知之技術] 、下面將說明習知之場效電晶體（以下簡稱為M0SFET)之制 造方法，包含與本發明有關之閘極電極之形成步驟。衣 爹照圖6 ’在半導體基板1之表面，形成閘極氧化膜2和 元件分離氧化膜3。在閘極氧化膜2之上，形成多晶矽層 參照圖6和圖7，使用光抗蝕劑圖型作為遮罩，對多曰 層4和閘極氧化膜2進行圖型製作，用來形成間極電極5B曰。 參照圖8，卩閘極電極5作為遮罩，料導體基板i之表 面，植入雜質離子，用來形成源極/汲極區域6、7。 々參照Γ: '半導體基板1之上，以覆蓋閘極電極5之方 式’形成層間絕緣膜8。在層問纟g《矣时。山 十& π』/ 牡膚間絶緣膜8中，形成接觸孔8a 使源極/汲極區域6、7之表面之一部份露出。形成銘 布線9使其經由接觸孔8&連接到源極/汲極區域6、了。 點二Li使開極電極成為低電阻者1年來使用高-[發明所欲解決之問題] 在此種方式之習知之M0SFET之製造方法中，參照圖
543090 五、發明說明（2) 在對閘極電極5進行圖型製作時，使用光抗蝕劑進行。 但是，對於使用光抗钱劑之步驟，當考慮到製作遮罩之 成本等時，不利於微小面積之圖型製作為其問題。 本發明用來解決上述之問題，其目的是提供改良之高熔 點金屬布線層之製造方法，可以有利的進行微小面積之圖 型製作。 本發明之另一目的是提供包含有上述之高熔點金屬布線 層之形成步驟之半導體裝置之製造方法。 本發明之另一目的是提供利用此種方法所獲得之半導體 裝置。 [解決問題之手段] 在本發明之高熔點金屬布線層之製造方法中，首先，在 半導體基板之上形成矽層。在上述之矽層之上形成高熔點 金屬層。在欲形成布線層之部份，形成上述之矽層和上述 高熔點金屬層之混合層。在上述之混合層以外之部份，蝕 刻和除去上述之矽層和上述之高熔點金屬層，用來形成布 線層。對上述之布線層進行熱處理。 依照本發明之較佳實施態樣時，用以形成上述之混合層 之步驟包含以離子照射欲形成上述布線層之部份，所選擇 之能量使離子可以植入到上述之矽層和上述之高熔點金屬 層1 1之境界部份。 上述之離子照射之進行最好不使用遮罩。 上述之矽層和上述之高熔點金屬層之膜厚最好分別選擇 使構成該等之原子之數目之比成為2 ·. 1。
\\312\2d-code\91-08\91110623.ptd 第6頁 543090
形秒層。 五、發明說明（3) 。該惰性氣體之離子包 上述之矽層包含多晶矽層或非晶 上述之離子包含惰性氣體之離子 含Ar之離子。 上述之離子照射之進行最好使用聚集離子射 上述之高熔點金屬包含Co、Ti或W。 ° 上述之布線層包含閘極布線。 在依照本發明之另一態樣之半導體裝置之製& 在半導體基板之上形成矽層。在上述之矽 ' ’尽之上开4占宜、咬 點金屬層。在欲形成配線層之部份，形成上述 $风冋& 述之高熔點金屬層之混合層。在上述混合層二: 份，、蝕刻和除去上述之矽層和上述之高熔點金屬層了用= 形成布線層。對上述之布線層進行熱處理。 e 依照本發明之更另一態樣之半導體裝置具備有半導體其 板。^上述之半導體基板之上，設置以高熔點金屬矽化ς 層形成之布線層。在上述之高熔點金屬矽化物 性氣體成分。 曰匕3有^ 上述之惰性氣體成分包含Ar。 [發明之實施形態]
下面將根據圖面用來說明本發明之實施形態。 實施形態1 〜、 圖1〜圖4是實施形態丨之高熔點金屬布線層之製造方法 之各個步驟之半導體裝置之剖面圖。 參照圖1，在矽基板1之上，形成閘極氧化膜2。 參照圖2，在閘極氧化膜2之上，形成多晶矽層1 0。在多
543090 五、發明說明（4) 曰0之上’設置由co、Τι.等形成之高溶點金屬層 m莖々k Γ 屬層11之膜厚’分別堆積成使 才，亥專之原子之數目之比成為2:卜另夕卜，亦可以使用 非晶形石夕層代替該多晶矽層1 〇。 參照圖3，在多晶石夕居1 η夺〇古 八w m 牡夕7層1 U和呵熔點金屬層11之境界部 伤’利用能植入離子之選定夕e 八防u、疋之此ΐ ’對欲形成布線層之部 伤知、射惰性氣體之紅之離子12。離子12之劑量為10"〜1015 atoms/cm2 〇 :用忒離子照射，因為在離子接觸到之位置可以成為混 合層拉所以只在欲形成布線層之部份，形成多晶石夕 ，金属之混合層（由c〇2Si、cosu〇c 成）。該離 射亦可以使用光遮罩進行，但是經由使用聚集離子射束， 可以不使用遮罩’選擇所欲照射之部份的進行離子照射。 參照圖3和圖4，對非照射部份之高溶點金屬層和多晶石夕 層，順序的進灯濕式蝕刻，用來形成電極〗3。混合層， 晶矽層和，熔點金屬層之蝕刻速度互不相同。因此’非照 射部份之高溶點金屬層和多晶矽層可以選擇性的蝕刻和除 去。 利用其後之熱處理，混合層13全部變化成為。另 夕上，多矽層1 0和高熔點金屬層J i之膜厚分別被選擇成使 構成該4之原子之數目之比成為2 : i。另外，所產生之 C〇Si2其電阻值低至1G〜2〇 # Ω。因&，成 極電極。 -心阑 以此種方法形成之金屬矽化物層所構成閘極電極，包含
543090
有A r原子。 圖9之步驟，可以獲得 然後，經由習知步驟之圖8 M0SFET 。 依照此種方式，使用聚集離子射 L7 ^ ^ ^ ^ 加丄本 町米時，不使用遮罩亦可 =士細線’叙如為微小區域時，可以減小製作遮罩之工 夫和成本。 性氣體之理由是當使用活性 兩炼點金屬層可能進行反 成不良之影響。 另外，上述之實施例使用惰 氣體時，該氣體與多晶矽層和 應，會對閘極電極之導電性造 實施形熊2
在上述之實施形態1中，所示之實例是多晶矽層1〇形成工 層、，在其上形成1層之高熔點金屬層丨丨之情況，但是本發 明並不只限於此種方式。亦即，參照圖5，首先形成多晶 矽層10a，其次形成高熔點金屬層丨丨，然後，在其上形成 多晶矽層10b。多晶矽層（i〇a + i〇b)和高熔點金屬層丨丨之膜 厚分別被選擇成為在垂直方向使矽原子和高熔點金屬原子 之數目之比成為2 : 1。其次，對各個之境界部植入惰性氣 體’用來形成混合層。即使成為此種構造，亦可以獲得盥 實施形態1同樣之效果。 〃
一另外，在上述之實施形態中，所示之實例是使用c〇作為 咼熔點金屬之情况，但是使用W時石夕化物層成為ψ g丨2，使、 用T i時矽化物層成為T i s i2。 2 此處所揭示之實施形態之所有部份只作舉例之用，不廉 被視為限制性者。本發明之範圍不以上述說明表示，而:
543090 五、發明說明（6) 以申請專利範圍表示，包含與申請專利範圍同等意義和範 圍内之所有之變更。 [發明之效果] 如以上之說明，依照本發明時，在使用聚集離子射束之 情況，不使用遮罩亦可以形成細線，假如為微小面積時， 具有可以減小製作遮罩之工夫和減小成本之效果。 元件編號之說明 1 半 導 體 基 板 2 閘 極 氧 化 膜 10 多 晶 矽 膜 11 熔 點 金 屬層 13 混 合 層
C:\2D-C0DE\91-08\91110623.ptd 第10頁 543090 圖式簡單說明 圖1是實施形態1之高熔點金屬布線層之製造方法之步驟 之第1步驟之半導體裝置之剖面圖。 圖2是實施形態1之高熔點金屬布線層之製造方法之步驟 之第2步驟之半導體裝置之剖面圖。 圖3是實施形態1之高熔點金屬布線層之製造方法之步驟 之第3步驟之半導體裝置之剖面圖。 圖4是實施形態1之高熔點金屬布線層之製造方法之步驟 之第4步驟之半導體裝置之剖面圖。 圖5是實施形態2之高熔點金屬布線層之製造方法之主要 步驟之半導體裝置之剖面圖。 圖6是習知之M0SFET之製造方法之步驟之第1步驟之半導 體裝置之剖面圖。 圖7是習知之M0SFET之製造方法之步驟之第2步驟之半導 體裝置之剖面圖。 圖8是習知之M0SFET之製造方法之步驟之第3步驟之半導 體裝置之剖面圖。 圖9是習知之半導體裝置之剖面圖。
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C:\2D-CODE\91-08\91110623.ptd 第11頁

Claims (1)

  1. 六、申請專利範圍 1 · 一種南炼點金屬布線層之製造方法，其特徵是呈 之步驟包含有： / 在半導體基板1之上形成矽層10 ; 在上述之石夕層10之上形成高炼點金屬層η ; 在欲形成布線層之部份，形成上述之^層10和上 熔點金屬層11之混合層1 3 ; ^ 在_^之5合層13以外之部份’麵刻和除 10:上述之…金屬層11，用來形成布線層；和 層 對上述之布線層進行熱處理。 U請專利範圍第！項之高 法，其中用以形成上述之混合芦毋/炎嘈又衣4方 欲形成上述布線層之部份，所二 ν驟包含以離子照射 到上述之石夕層….上述之高可以植入 3 ·如申請專利範圍第2項之古 屬層1 1之埦界邛份。 法，其中上述之離子照射之雄巧炫點金屬布線層之製造方 4 ·如申請專利範圍第丨 古仃不使用遮罩。 法，其中上述之矽層丨〇和上阿炫J點金屬布線層之製造方 別選擇使構成該等之原子之^之高熔點金屬層11之膜厚分 5·如申請專利範圍第i 目~之比成為2·· 1。 法，其中上述之矽層丨〇包含夕阿曰炫點金屬布線層之製造方 6·如申請專利範圍第2匕3夕&晶石夕層或非晶形矽層。 如申請專利範圍第3項之古 ，其中上述之離子照射、、阿椒點金屬布線層之製造方 、之進行是使用聚集離子射束。 法，其中上述之離子包人^之高炫點金屬布線層之製造方 7 ·如申請專利笳阁哲〇胃〖生氣體之離子。 法 543090
    六、申請專利範圍 1 --------- 广：：”利範圍第“員 “由土述之惰性氣體之離子包含…子 法，·：中：ίΓ 3第1項之高熔點金屬布線層之製造方 /ΛΛ 炼點金屬層11包含c〇、Ti，或w。 法：中申Λ L”第1項之高溶點金屬布線層之製造方 法其中上述之布線層包含閘極布線。 11 · 一種半導體裝置之釗 驟包含有·· 之衣&方法，其特倣是所具備之步 在半導體基板1之上形成矽層10 ; 在上述之石夕層1 〇之上形成高熔點金屬層丨i ; 在欲形成布線層之部份，形成上述之矽層丨〇和上述之高 炫點金屬層11之混合層1 3 ; 在上述之混合層1 3以外之其餘之部份，姓刻和除去上述 之石夕層1 0和上述之高炼點金屬層丨丨，用來形成布線層；和 對上述之布線層進行熱處理。 1 2 · —種半導體裝置，其特徵是具備有： 半導體基板1 ;和 布線層，被設在上述之半導體基板之上，以高熔點金屬 矽化物層11形成； 上述之高溶點石夕化物層11包含有惰性氣體成分。 13.如申請專利把圍第12項之半導體裝置，其中上述之 惰性氣體成分包含Ar。
    C:\2D-00DE\91-08\91110623.ptd 第13頁
TW091110623A 2001-07-24 2002-05-21 Method of fabricating high melting point metal wiring layer, method of fabricating semiconductor device and semiconductor device TW543090B (en)

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US20090236676A1 (en) * 2008-03-20 2009-09-24 International Business Machines Corporation Structure and method to make high performance mosfet with fully silicided gate
US8324031B2 (en) * 2008-06-24 2012-12-04 Globalfoundries Singapore Pte. Ltd. Diffusion barrier and method of formation thereof
JP6800026B2 (ja) * 2017-01-17 2020-12-16 エイブリック株式会社 半導体装置及び半導体装置の製造方法

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US4622735A (en) * 1980-12-12 1986-11-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device utilizing self-aligned silicide regions
US4755256A (en) * 1984-05-17 1988-07-05 Gte Laboratories Incorporated Method of producing small conductive members on a substrate
US4569124A (en) * 1984-05-22 1986-02-11 Hughes Aircraft Company Method for forming thin conducting lines by ion implantation and preferential etching
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US6096638A (en) * 1995-10-28 2000-08-01 Nec Corporation Method for forming a refractory metal silicide layer
US5888888A (en) * 1997-01-29 1999-03-30 Ultratech Stepper, Inc. Method for forming a silicide region on a silicon body
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