TW519744B - Semiconductor-element with surface-metallization - Google Patents

Semiconductor-element with surface-metallization Download PDF

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Publication number
TW519744B
TW519744B TW090112633A TW90112633A TW519744B TW 519744 B TW519744 B TW 519744B TW 090112633 A TW090112633 A TW 090112633A TW 90112633 A TW90112633 A TW 90112633A TW 519744 B TW519744 B TW 519744B
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TW
Taiwan
Prior art keywords
patent application
welding
semiconductor device
scope
semiconductor
Prior art date
Application number
TW090112633A
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English (en)
Inventor
Herbert Brunner
Thomas Hoefer
Harald Jaeger
Original Assignee
Osram Opto Semiconductors Gmbh
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Publication of TW519744B publication Critical patent/TW519744B/zh

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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
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    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Description

519744 五、發明説明（1 ) 本發明涉及一種依據申請專利範圍第1項之前言之具 有表面金屬層之半導體元件。 具有表面金屬層之半導體元件例如在US 5 0 81 5 20中 已爲人所知。此處之半導體元件具有半導體本體及基板 ，基板之主面具有形式是導電軌結構之表面金屬層。半 導體本體經由導電軌結構之部份區域而可被接觸。導電 軌結構之其它部份區域用作此元件之連接區。 此種以表面金屬層構成之連接面用在所謂MID (Molded Interconnected Device)技術或 CIMID (Chip Integrated Molded Interconnected Device)技 中，其在 US 5 9295 1 6中爲人所知。 由US 5 08 1 5 20中可知，此種連接面通常形成在外殻-或基板外邊緣之附近中。習知之連接方式是：使連接面 配置在二個平行之列中，這些列沿著此外殼之一個相面 對之外邊緣而延伸。 但上述方式之缺點是：在此種形式之組件在已焊接之 狀態下各焊接端很容易斷開，若此組件受到一種溫度交 變之負載時。此種溫度交變之負載可在正常操作時例如 藉由外部溫度之季節性改變在品質控制措施（例如，溫 度交變檢測及溫度變動）中發生或在焊接過程本身中發 生。 本發明之目的是提供一種具有表面金屬層之半導體元 件，其熱性（例如，耐溫性、熱之可負載性）已改良。 此外，此種元件可以較低成本製成。 519744 五、發明説明（2 ) 此目的藉由申請專利範圍第1項之半導體元件來達成 。本發明有利之其它形式描述在申請專利範圍各附屬項 ρ|^ί 〇 依據本發明，此半導體元件設有至少一個半導體本體 及一個外殼基體，此外殼基體具有一個接觸面以安裝此 半導體元件，其上藉由表面金屬層而形成許多焊接點， 這些焊接點組合成多個焊接列（row)。各焊接列之間之距 離保持儘可能小。 所謂儘可能小之距離是指一種範圍中之距離，其下限 是由各別接點之間所需之隔離以及此元.件之可操縱性（ 特別是在焊接過程時）所決定。此種距離特別是須選擇 成夠大，使此元件所設定之規格中在各接點之間不會發 生短路。 各焊接列之間之儘可能小之距離之另一決定性因素是 半導體工業中一般所用之連接網目（raster)大小。焊接列 之間之距離較佳是等於此種沿著一個焊接列之二個相鄰 之焊接點之間之距離。 上述距離之範圍之上限一方面是由外殻材料及電路板 材料之熱膨脹係數之差（d i f f e r e n c e)且另一方面是由此元 件操作時之溫度範圍所決定。此種上限就所使用之材料 而言是由簡易之溫度交變檢測所測定。由此可得知：各 焊接列之間之距離應選擇成多小，使得在此種元件所設 定之溫度範圍中在表面金屬層或焊接點上不會產生此種 與熱膨脹有關之損害。此種損害特別是在一種經由焊接 -4- 519744 五、發明説明（2 ) 點 而 固 疋 至 電 路 板 上 之 元 件 中 產 生 ， 追 是 由 於 外 殼 基 體 和 電 路 板 之 間 之 機 械 應 力 所 造 成 此 種 應 力 又 與 電 路 板 和 外 殼 基 體 之 不 同 之 熱 膨 脹 有 關 〇 在本 發 明 中 可 有 利 地 使 表 面 金 屬 層 5 焊 接 點 或 ( 在 已 焊 接 狀 態 時 ) 焊 接 連 接 ( 例 如 表 面 金 屬 層 之 焊 接 點 ) 之 受 損 程 度 下 降 1 亦 可 使 焊 接 連 接 區 之 斷 裂 危 險 性 降 低 〇 此 外 利 用 本 發 明 可 擴 大 此 元 件 操 作時之 溫 度 範 圍 〇 本 發 明 之 其 它 優 點 是 : 藉 由 焊 接 點 之 緊 密 配 置 y 則 連 接 網 巨 可 與 外 殻 大 小 j \ \\ 關 〇 本 發 明 特 別 有 利 之 實 施 形 式 是 使 焊 接 列 平 行 配 置 ， 這 是 因 爲 這 允 許 各 別 焊 接 點 有特 別 緊 密 之 配 置 〇 此 種 配 置 在 使 用 白 動 之 配 備 裝 置 時 是 有 利 的 〇 此外 ， 就 已 焊 接 之 組 件 之 機 械 定 性 而 言 使 二 個 導 電 軌 對 稱 於 此 外 殼 之 對 稱 軸 而 配 置 時 是 有 利 的 0 在 本 發 明 之 較 佳 實 施 形 式 中 ， 焊 接 點 配 置 在 外 殼 之 凹 P 中 0 藉 由 焊 接 點 之 間 這 樣 所 形 成 之 條 件 ， 則 焊 接 點 和 電 路 板 表 面 之 間 之 距 離 可 準 確 地 決 定 0 此外 5 各 別 焊 接 點 之 間 之 隔 離 作 用 須 提 高 以 防 止 有 缺 陷 之 焊 接 橋 之 形 成 〇 在 特 別 有 利 之 實 施 形 式 中 使 用 PPA(polyphthalami [d)作 爲 外 殼 成 型 材 料 0 這 樣 可 很 省 成 本 地 製 成 此 元 件 〇 此 外 ? PPA 可 有 利 地 由 白 動 製 造 機 輕 易 地 成 型 且 進 行 處 理 0 本 發 明 允 許 PPA 之 使 用 ， 此 乃 5- 因 Jib 有 缺 陷 之 效 應 ( 其 519744 五、發明説明（5 ) 在外殻之外側上藉由導電軌結構7而形成焊接點1。 晶片連接區4 (或接線連接區5)和焊接點1之間之電 性連接同樣藉由導電軌7來達成。導電軌7在外殼基體 2之表面上延伸。 第1 a圖中顯示此外殼之側邊上之俯視圖，其上形成 一些焊接點1。全部6個焊接點配置成二列（每列三個 焊接點），本發明中之焊接點數目當然不限於6個。這 些列平行而延伸且狹窄地相鄰。藉由此種緊密之配置可 防止：外殻基體2之熱膨脹使焊接點1造成很大之偏移 。所謂偏移此處是指一個區段，即，在加熱或冷卻時在 所考慮之溫度範圍中由於外殼基體2之膨脹使焊接點1 相對於電路板而偏移此一區段。此種組件之由於本發明 所造成之有利之熱特性是與下述情況有關：此偏移之大 小以線性近似之方式和焊接點之距離成比例，使焊接點 1 (其相互間之距離很小）之緊密之配置只使焊接點1 造成很小之偏移。在此種元件之焊接狀態中很小之偏移 只會在焊接位置中造成很小之應力，因此可防止此種焊 接位置斷裂之危險。 第3圖中顯示先前技藝中之焊接位置之配置以便比較 。焊接點1 a、1 b此時沿著外殼邊緣附近而配置成二列 。相面對之焊接點1 a和1 b因此互相遠離。這樣會在熱 膨脹時造成上述較大之偏移且使各焊接位置不能持久地 對抗溫度交變應力。 第2圖顯示另一實施例之透視圖。導電軌7和焊接點 519744 五、發明説明（6 ) 1配置在外殻表面上之凹口中。各導電軌之間這樣所形 成之條片8在此元件之焊接狀態中直接位於電路板上且 可準確而可再生性地決定各焊接點1和電路板之間之距 離。藉由此種決定，則電路扳與此元件之間之焊接連接 件之品質可進一步提高。 此外，藉由條片8可有效地使各別焊接點1互相隔開 。這樣可防止：在裝配過程中各別焊接點1之間形成一 些有缺陷之焊接斷裂。 可使用熱塑性塑膠（例如，PPA )作爲外殻材料。這 些材料在外殼製造時已在濺鍍澆注法中受考驗，但其熱 膨脹係數是與典型電路板材料（例如，FR4 )之熱膨脹 係數差異很大。 熱膨脹係數與電路板材料相似之其它材料（例如， LCP )昂貴很多，在濺鍍澆注法中不易處理或不足以金 屬化成P P A。在本發明之元件中可使用熱塑性塑膠（例 如，PPA)作爲外殼成型材料。 以CIMID技術製成之外殻適合構成較大之三維元件結 構。此種外殼之另一應用領域是光學元件，例如，發光 二極體、光二極體或反射光柵，其中半導體本體之範圍 是由適當之透光材料所覆蓋。本發明當然不限於上述之 實施例，而是可用於各種具有表面金屬層之元件之連接 設計，其可在組裝之狀態中提高此元件之熱學上之可負 載性。 符號說明 519744 五、發明説明（7 ) 1…焊接點 2…外殼基體 3…半導體本體 4…晶片連接區 5…接線連接區 6…接線連接件 7…導電軌 8…條片 -9-

Claims (1)

  1. 519744 __知和《一,« - ««· - ......... /~.x. "陳上匚六、申請專利範圍 第90112633號「具有表面金屬層之半導體元件」專利案 (9 1年1 0月修正） 六、申請專利範圍： 1. 一種半導體元件’其具有一個外殼基體（2)及至少一 個本體（3)，外殻基體（2)具有一個接觸面以 安裝此半導體元件，此接觸面上藉由表面金屬層而 开多$多個l·焊接點（1 )，各焊接點（丨）組合成多個焊接 列，其特徵爲： 各焊接列配置在一種間距中，此間距須適當地夠 大以防止各焊接點（丨）之間發生短路且須足夠小，以 防止表面金屬層上或焊接點（1 )上之受損現象，其是 與外殻基體之與熱有關之膨脹有關。 2. 如申請專利範圍第1項之半導體元件，其中各焊接 列平行而配置著。 3. 如申請專利範圍第1或2項之半導體元件，其中各 焊接列對稱於外殻之對稱軸而配置著。 4. 如申請專利範圍第1或2項之半導體元件，其中各 焊接點（1 )配置在外殼基體之凹口中。 5. 如申請專利範圍第1或2項之半導體元件，其中外 殼基體由成型材料製成。 6·如申請專利範圍第5項之半導體元件，其中成型材 料含有PPA。 519744 六、申請專利範圍 7. 如申請專利範圍第1或2項之半導體元件，其中在 接觸面上形成二個焊接列，其具有相同數目之焊接 點（1 )。 8. 如申請專利範圍第1或2項之半導體元件，其用來 製成發光二極體、光二極體及反射光柵。
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JP5376742B2 (ja) 2013-12-25
US7109590B2 (en) 2006-09-19
JP2003534662A (ja) 2003-11-18
CN100339980C (zh) 2007-09-26
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WO2001091184A2 (de) 2001-11-29

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