TW517310B - A method of manufacturing semiconductor devices - Google Patents

A method of manufacturing semiconductor devices Download PDF

Info

Publication number
TW517310B
TW517310B TW090115593A TW90115593A TW517310B TW 517310 B TW517310 B TW 517310B TW 090115593 A TW090115593 A TW 090115593A TW 90115593 A TW90115593 A TW 90115593A TW 517310 B TW517310 B TW 517310B
Authority
TW
Taiwan
Prior art keywords
film
wiring
dielectric constant
insulating film
layer
Prior art date
Application number
TW090115593A
Other languages
English (en)
Inventor
Takao Kinoshita
Kunihiko Orita
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Application granted granted Critical
Publication of TW517310B publication Critical patent/TW517310B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Description

5!73l〇
A7 B7 五、發明説明（1 ) 發明背景 1 .發明範疇 本發明係有關於一種製造半導體裝置之方法。詳言之它 是關於一種製造具有雙刻紋配線之半導體裝置之方法。 2·先前技藝之説明
裝 正如最近縮小尺寸半導體裝置之縮小配線之結果，配線 電阻及配線電容大幅地增加，以致以RC表示不利於大型積 體電路（LSI)操作速率之配線延遲無法被忽略。再者，搭配 縮小尺寸之配線，配線電流密度亦會增加，其因爲電子遷 移升高了配線可信度滑落的嚴重問題，且因爲配線電容的 增加提高了電力消耗。 所以，銅已經開始被使用當作配線材料，其具有較低的 阻抗且顯現比鋁有更高的電子遷移容限。
然而，因爲銅利用傳統乾式蝕刻技術的圖樣化很困難， 使用化學機械研磨法（CMP)之刻紋方法已經被應用。詳言 之’最近已經發展出一種雙刻紋方法，其中配線渠溝及觸 點孔同時被形成。 在下文中，一種通用的雙刻紋方法將被説明。 首先，如圖2(a)中所顯示，一種以BPSG (硼磷矽酸鹽玻 璃）所製作的中間層絕緣薄膜22形成於其上有電晶體形成之 半導體基板2 1上。觸點孔被形成於中間層絕緣薄膜22中。 在含有觸點孔的中間層絕緣薄膜22上，鎢薄/膜被形成且利 用CMP法知其表面拋光，以致於鹤栓23被埋在觸點孔中。 然後，如圖2(b)中所顯示，蝕刻停止薄膜24被沉積且介 -4-
517310
發明説明 二¥數3.0之無氟有機聚合物薄膜25被形成於其上。在此無 軋有機聚合物薄膜25中，一種渠溝被形成用於刻紋配線結 冓且銅被埋入刻紋配線渠溝中形成第一層銅配線2 6。
接著，如圖2( c)所顯示，利用電漿化學氣體沉積法（cVD) 在無氟有機聚合物薄膜2 5及第一層銅配線2 6上形成一種鋼 擴政禁止薄膜27，且在其上形成無亂有機聚合物薄膜28、 鋼擴散禁止薄膜29、無氟有機聚合物薄膜3〇及蝕刻停止薄 膜31。然後，利用使用預定形狀抗蝕罩32之乾式蝕刻法形 成用於連接第一銅配線26及第二配線之觸點孔33。 如圖2( d)中所顯示，利用使用預定形狀抗蝕罩34之乾式 餘刻法形成配線渠溝3 5，以便含括觸點孔3 3。 裝 如圖2( e)所頦示，銅被埋入觸點孔33及配線渠溝3 5中以 形成銅雙刻紋配線3 6。
、如此雙刻紋方法，爲了要在中間層絕緣薄膜中以乾式蝕 刻形成配線渠溝步驟中控制配線渠溝的深度，使用蝕刻停 止薄胰疋必須的，因爲渠溝的深度會直接影響配線的電阻 率。再者，亦需要銅擴散禁止薄膜用於防止銅在形成配線 〈後在中間層絕緣薄膜中擴散，目爲銅甚至在低溫熱處理 可以輕易地在中間層絕緣薄膜中擴散。 a通常，SiN薄膜被使用當作蝕刻停止絕緣薄膜，因爲它在 乾式I虫刻與諸如三氧化石夕（Si〇2)薄膜或氣化二氧化石夕（fsg) 薄膜相比之下可以容易地達到選擇。再者，肩膜亦被使 用當作銅擴散禁止層，因爲它具有禁止銅擴散的功能。 然而，因馬SiN薄膜具有不低於7的高介電常數，所以使 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 517310
用^述方法中所形成之SlN薄膜甚至它合併一種低介電材料 薄膜（具有介電常數不超過3 · 〇之薄膜）當作多層配線結構中 的中間層絕緣薄膜很難有效地降低配線電容。在這裡，配 線電容的意思是在以垂直方向或以水平方向所配置的配線 之間所產生之電容。 在一另方面，在形成雙刻紋結構配線的時候有可能為了 降低配線電容而不使用已經被使用當作蝕刻停止薄膜之 薄膜。在此例中，然而，這些帶來了其他問題，例如配線 渠溝的深度很難控制且根據乾式蝕刻之平面内之一致性， 觸點孔的形狀會大幅地改變，且因此，雙刻紋結構配線的 電阻率變得不穩定。 此外，例如，在日本專利特許H7( 1995)_ 2833 12中說明使 用爛氮化物（BN)薄膜當作蝕刻停止薄膜。然而，因為利用 傳、’先B N /彝膜形成方法只能完成大約4相對較高的介電常 數，例如，利用使用Β^6及&當作材料在溫度大約35〇t電 漿氣壓300 W之電漿CVD法，在垂直方向及水平方向之配線 電容尚未達到足夠的下降。 此外，如上文所述沉積BN薄膜之方法可以只提供9毫微米 /分鐘或更低的沉積速率。這樣會增加問題，諸如拉長製造 的程序及提高製造的成本。 發明概要 , 本發明已經考慮到上述的問題。本發明的厂.個目的是提 供一種製造半導體裝置之方法，其可以藉由低介電常數之 中間層絕緣薄膜的形成實現在垂直方向及水平方向之;咸少、 -6- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 517310 A7 ____ B7 五、發明説明（4 ) 配線電容且利用簡單的方法實現高速的操作。 如本發明，提供一種製造半導體裝置之方法，其含有的 配線形成步驟包含：形成由在第（n)層配線上介電常數低於 4之侧氮化物薄膜所組成之中間層絕緣薄膜，在中間層絕緣 薄膜中形成穿孔及/或渠溝，以導電材料填入穿孔及/或渠 溝中且在穿孔及/或渠溝上形成第（n+ 1)層配線。 圖式摘要説明 圖1 ( a) 土 1 ( e)疋説明根據本發明製造半導體裝置方法實施 例之主體部分之概要截面視圖；且 八 圖2( a)至2( e)是説明根據先前技藝製造半導體裝置方法之 主體郅分之概要截面視圖。 較佳實施例説明 在如本發明製造半導體裝置之方法中，一中間層絕緣薄 膜通常被形成於半導體基板上。 半導體基板可以是任何一種經常被使用在半導體裝置中 而/又有特別限制且説明地包含元素的半導體，諸如矽、 鍺，及合成半導體，諸如GaAs、InGaAs及ZnSe。在它們之 中，矽基板較佳。在此半導體基板上，一或 區：諸如電晶體、電容器'電阻器及其類似元件裝；= 成 < 電路、中間層絕緣薄膜、其他半導體裝置及其類似裝 置Z以以單層或多層結構被形成。在它們之中，較佳的半 導體基板是其上有一個或多個諸如電晶體、電容器、電阻 器及其類似元件、其所形成之電路、其他半導體裝置及其 相似裝置以單層成形。 517310
—本發明中配線形成步驟通常意味著一連率步驟，包含在 J(:)層配線上形成一中間層絕緣薄膜；形成_穿孔及/或 木/ $與其相似之結構；以|電材料填人穿孔及/或渠溝； 且在穿孔及/或渠溝上形成第（n+1)層配線。 第U)層配線在此的意思，舉例來說，是一基板，豆中一
層被形成，如上文所述之元件、電路或與其相似 衣置之、包極被形成於基板上，一配線被形成於第二或上面 装
一 ^或與其相似層中。雜質擴散層被形成於其中之基板可 以疋P型或N型雜質以相較高濃度被擴散其中之基板。此 外’電極與配線之材#、其厚度及與其相似之特性可以與 :些經常使用於電極及配線的—樣而沒有特別的限制，1 說明地包|，例如，無定型的單層或薄片層、單晶或多晶N 型或P型元素半導體(例如矽、鍺等）或合成半導體(GaAs、 mi-zmcss等）；金屬，諸如金、舶、銀、銅、紹極斑 其相似之金屬或它們的合金；高熔點之金屬，諸如鈦、 組、鎢及其他相似之金屬；石夕化物、高熔點金屬之聚合物 或其他類似金屬化物。 中，層絕緣薄膜可以是-種能夠在配線之間保持電隔離 之薄膜且可以被形成於介電常數小K42Bn薄膜之單一層 中或具有其他絕緣薄膜，諸如Si〇2薄膜、fsg薄膜、 hydrogenized sil- sesquioxane resin 薄膜、含有低介電常數碳 之薄膜（例如CVD-Si〇C薄膜等）或其他相類似之薄膜，之^ 疊薄膜中’它是由包含BN薄膜且介電常數小於4之薄膜戶^ 形成。在它們之中，其他絕緣薄膜最好是具有與bn薄膜相 8- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 517310 A7
:1於丄的“常數。此外，βΝ薄膜的介電常數小於4， :::大约3 5較佳，更好的是不高於大约3。且甚至二 同於大約2.0最好。介電常數小於4之而薄膜的 於不 裝置上之♦恿;3並尸传到半導體的效能、施加志半導體 ττ彳 ^他類似特性作適當地調整。在單層的情 如’大/約5至30毫微米厚度可以被討論。在層疊薄 蓴膜二Γ:’薄膜具有足夠的厚度以致於它能與其他絕緣 銅等人絕緣，但是如果薄膜厚度能夠當作禁止諸如 钢寺至屬擴欢之薄膜，且/或能夠當作在使用銅作材料雙列 紋結構形成多層I❹驟中渠溝配㈣成之乾式㈣停止 濟月吴則更佳，如下文所描述。例#，在該其他絕緣薄膜且 度大約300至500毫微米的情況中，_薄膜的厚度最好 爲大、勺5至2G«c微米。當ε被使用作爲禁止金屬擴散的薄膜 且/或渠溝配線形成之乾式蝕刻停止薄膜的時候，將薄膜 設置於中間層絕緣薄膜的底部是較佳的。 介電常數小於4之BN薄膜可以利用；τ、同的方法被形成，例 如，化學蒸氣沉積（CVD)法、氣壓CVD法、減壓法、 熱（高溫、正常溫度、低溫）CVD法、電漿CVD法、照相 CVD法、ECR電漿CVD法及與其類似之方法。其中，以電裝 CVD法及低溫熱CVD法較·佳。 例如，以電漿CVD法爲例，最好使用Β2Ηδ&ΝΗ3氣體當作 材料且除了這些氣體之外，也可以使用惰漱氣體，諸如 氦、說、氬極與其類似之氣體。適當的Β2Η^ΝΗ3的體積比 例爲1比大約10至50、1比大約40、1比大約3〇或者i比大約 -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 517310
20 〇 電漿CVD法的適各你彳土、^, Λ ·、 7迥田條件被選擇以便得到想要的介電常 婁平L地進订/几積（例如沉積速率：不低於大約⑺毫微米 /分鐘，較佳地不低於大約15毫微米/分鐘等），不會因爲下 層中配線材料的熔解引起原子遷移且不會破壞下層中的配 線、基板及與其類似物件，如上文所述。例如，較佳地停 件被顯示如下：CVD設備内的壓力可以是大約〇 5至”匈爾
(torr);大氣溫度不超過大約45〇。〇，大約25〇至35〇。(：較 佳；電力大約40至200 W左右。 裝 此外，在低，皿熱CVD法的例子中，使用teab (triethylamine bane複合物）及^^3氣體當作材料較佳，且除 了這些氣體之外，載體氣體可以被使用。TEAB與NH3的適 當體積比例是1比大約10至5〇、i比大約40、i比大約3〇且進
線 步1比大約20。低溫熱CVD法的適當條件被選擇以便得到 一想要的介電常數，平穩地進行沉積，不會因爲下層中配 線材料的熔解引起原子遷移且不會破壞下層中的配線、基 板及與其類似物件，如上文所述。例如，較佳地條件被顯 示如下：CVD設備内的壓力可以是大約；[至3陶爾（t〇rr);大 氣溫度不超過大約450°C，大約350至400T：較佳；電力大约 40至200 W左右。 穿孔通常被形成以穿過中間層絕緣薄膜，用於將中間層 絕緣薄膜的上一層與下一層接觸。例如，其/包含觸點孔， 通道孔、穿孔及與其類似孔。渠溝通常被形成用於中間層 絕緣薄膜表面中之配線配置，如同不穿透之凹形部分。只 -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公爱) 517310 要是被應用於半導體奘菩 . 沒有特別的限制 置上，穿孔及渠溝在大小及形狀上 ^^及/或渠溝或類似機構可以制傳統方法形成，諸如 :、相千版印刷及姓刻法”虫刻可以以不同的方法實施，例 二使：諸如氣酸、熱，酸'确酸、硫酸及與其類似之酸 或驗性溶液之濕式触刻；嫌刻，即諸如喷濺或 與其類似 < 物理紐舍丨，$ 2 诸如RIE法或與其類似方法之化學蝕 :二：：在使用BN薄膜當作蝕刻停止薄膜的例子中，最 率^ X的條件’以便增加絕緣薄膜至BN薄膜的選擇比 裝 渠溝可以被填平，例如，藉由在含有穿孔或渠溝 ^中間^緣薄膜的整個表面上形成—傳導材料之薄膜， 諸如PVD法、喷賤法或與其類似方法之 法或猎由諸如CVD法或其他與其類似之化學方法 穿孔或渠溝外側傳導材料不需要的部分移除。傳導材料Ϊ 上述配線材料。在它們之中，銅或其合金較 ^ k田的；度沒有特別地限制且，例如，最好不 ，孔或渠溝總深度。此外’在傳導材料形成之前，諸如敛 L : :鈮、-及與其類似之金屬或合金的單層薄膜 ^登層可以被形成於孔及/或渠溝表面上1導材料 的那为可以利用不同的物理或化學蝕刻方法要 噴歲、CVD法、CMP法及與其類似之方法。/在它例:， 以CMP法較佳。 < 中， 此外，上述本發明配線步驟可以只實施—次或複數次。 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公爱） 517310 A7 _______ B7 五、發明説明（9 ) 而且在複數個配線步驟中，配線步驟至少被實施一次。 本叙明製造半導體裝置之方法將參照附圖在下文中加以 詳細解釋。
如圖1 ( a)中所顯不，在諸如電晶體及與其類似元件被製 仏於其中之矽基板1表面上（未由附圖所顯示），由BpSG薄 膜所組成之中間層絕緣薄膜2以氣壓CVD法被形成。在此中 間層絕緣薄膜2之預定區域中，連接矽基板丨之觸點孔以照 相平版印刷及乾式|虫刻技術被形成。在包含這些觸點孔之 中間層、纟巴緣薄膜2整個表面上，一鎢薄膜依據喷濺法及CVD 法被形成，且以CMP法將鎢薄膜不需要的部分去除，以將 觸點栓3埋入觸點孔中。 後，如圖1(b)中所顯示，以使用混和氣體^仏與 NH3 50 · 1當作來源之電漿CVD法在電漿氣不大於⑼〇 w中 服度低於4:>〇 C下形成厚度50毫微米之硼氮（BN)薄膜當作渠 溝蝕刻停止薄膜。一種厚度500毫微米具有介電常數3之非 氟有機聚合物薄膜5以在氮氣中每分鐘2〇⑻轉（2〇〇〇 rpm)且 熱在20(TC的旋轉塗覆被形成。在此非氟有機聚合物薄膜5 之預定區域中，_照相平版印刷法及乾式钱刻技術形成 配線渠溝。在含有配線渠溝之非氟有機聚合物薄膜5表面上 利用噴濺法及EP法形成銅薄膜且利用CMp法將鋼薄膜不需 要的部分去除，埋入第一層銅配線6。 接著，如圖1(c)中所顯示，在整個含有第τ層鋼配線6之 非氟有機聚合物薄膜5表面上，形成一個厚度5〇亳微米2BN 薄膜7當作銅擴散禁止薄膜。利用旋轉塗覆法且然後利用孰 -12 - 本紙張尺度適用中國國家標準(CNS) A4規格(21GX 297公爱) 一 -------- 517310
。在/、上开/成厚度500愛微米之非氟有機聚合物薄膜 :後在，、上依序形成厚度50毫微米之BN薄膜9、厚度 毛微米4非氟有機聚合物薄膜1〇及厚度π毫微米之⑽薄 :11 一此外：在其上利用照相平版印刷法及乾式蝕刻法形 成預足形狀之柷|虫遮罩12。传闱朴戶益、产宠 ^ 使用此抗蝕遮罩12形成連接第 一銅配線6之觸點孔14。
此外，如圖1(d)中所顯示，利用照相平版印刷法及乾式 蚀刻法形成預定形&之抗蚀遮罩13且然後使用隸钱遮罩 13形成用於刻紋配線之渠溝1 5。 裝
線 然後，如圖1(e)中所顯示，利用噴濺法及£1>法在βν薄膜 11上形成一銅薄膜，連接觸點孔14及用於刻紋配線之渠溝 15。利用CMP法將銅薄膜不需要的部分去除，將第二銅配 線16埋入觸點孔14及渠溝15，藉以形成雙刻紋疊層配線。 利用與上述相同的製造步驟，在介電常數3之非氟有機聚 合物薄膜被使用當作中間層絕緣薄膜且具有介電常數3的 ΒΝ薄膜或具有介電常數8的siN薄膜被使用當作刻紋渠溝處 理I虫刻停止薄膜及銅擴散禁止薄膜的事例中，銅雙刻紋多 層配線中垂直及水平配線電容被測量。 因此，當在刻紋配線距離爲〇·21 μιη且配線深度爲0.45 μιη 的條件下時，使用BN薄膜比使用SiN薄膜可以達成減少1〇% 的水平配線電容。 ， 此外’當在雙刻紋孔的深度爲〇·5 μηι的條种下時，使用 ΒΝ薄膜比使用SiN薄膜可以達成減少1 〇%的垂直配線電容。 而且’在以介電常數2· 7之非氟有機聚合物薄膜當作中間 -13- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 517310 A7 B7 五、發明説明（11 ) 層絕緣薄膜且以介電常數8之SiN薄膜、用傳統方法所形成 介％常數4之BN薄膜或用上述製造步驟所形成介電常數3或2 之BN薄膜被形當作刻紋渠溝處理蝕刻停止薄膜及銅擴散禁 止薄膜的事例中，銅雙刻紋多層配線中的水平及垂直配線 電容被測量。 因此’如果介電常數爲8之SiN薄膜的垂直及水平配線電 答是100%，則介電常數爲4之BN薄膜的垂直及水平配線電 谷分別爲92%及95%，介電常數爲3之BN薄膜的垂直及水平 配線電容分別爲88%及91%，且介電常數爲2之BN薄膜則分 別爲8 5 %及8 7 %。 因此，吾人已經發現介電常數爲3及2之BN薄膜比起傳統 介電常數爲4之BN薄膜在操作速率可以達到10%的改良。此 外，亦可見到，當介電常數越低，則電容上中間層絕緣薄 膜厚度參差不其的作用會越小。 根據本發明，形成一種可以禁止會引發配線延遲之垂直 及水平電容增加之裝置成爲可能，利用在配線形成步驟中 藉以形成介電常數小於4之硼氮薄膜所組成之中間層絕緣薄 膜。於是，以一簡單方法可以製造一種高速裝置。 因爲本發明之中間層絕緣薄膜可以提出銅擴散禁止之功 能及/或乾式蚀刻阻斷器用於在使用銅作爲配線材料之雙刻 紋結構中多層配線形成步驟中渠溝配線之形成，所以有可 能有效地利用低介電常數的特性而保留這些^功能。因此， 可以降低垂直及水平配線電容，而導致高速裝置之實現。 -14- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）

Claims (1)

  1. 517310 A8 B8 C8
    1· 一種製造半導體裝置之方法，其含有一配線形 包.含： 人夕驟， 在第η層配線上形成以介電常數小於4之硼氮薄 成之中間層絕緣薄膜， 、所組 在中間層絕緣薄膜中形成一穿孔及/或渠溝， 將傳導材料填入穿孔及/或渠溝，及 在穿孔及/或渠溝上形成第（η+丨）層配線。
    裝 2·如申請專利範圍第丨項之方法，其中半導體裝置具有雙 金屬鑲嵌（damascene)結構之銅製多層配線且硼氮薄膜= 形成當作配線行成時之銅擴散禁止薄膜及/或蝕 薄膜。 T 3·如申請專利範圍第！或2項之方法，其中硼氮薄膜是以使 用B^6及NH3為材料之電漿CVD法被形成。 4·如申請專利範圍第1或2項之方法，其中硼氮薄膜是以使 用TEAB及ΝΑ為材料之熱CVD法被形成。
    5_如申凊專利範圍第1項之.方法.，其中第（n)層配線是一具 有雜質擴散層形成在其中之基板，一電極被形成於基板 上或一配線被形成當作第二或上一層。 6. 如申請專利範圍第丨項之方法，其中中間層絕緣薄膜是 一介電常數小於4之BN薄膜及介電常數實質相等或低於 此BN薄膜介電常數之另一絕緣薄膜之疊層薄膜。 7. 如申凊專利範圍第6項之方法，其中介電常數小於4之BN 溥膜被置於中間層絕緣薄膜的底部。 ^ 8·如申请專利範圍第1項之方法’其中配線形成步驟被執 行複數次。 -15- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)
TW090115593A 2000-06-27 2001-06-27 A method of manufacturing semiconductor devices TW517310B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000193001A JP3696055B2 (ja) 2000-06-27 2000-06-27 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
TW517310B true TW517310B (en) 2003-01-11

Family

ID=18692065

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090115593A TW517310B (en) 2000-06-27 2001-06-27 A method of manufacturing semiconductor devices

Country Status (5)

Country Link
US (1) US6511908B2 (zh)
EP (1) EP1168433A3 (zh)
JP (1) JP3696055B2 (zh)
KR (1) KR100421824B1 (zh)
TW (1) TW517310B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI423327B (zh) * 2006-12-26 2014-01-11 Lam Res Corp 降低後段製程配線結構之整體介電常數的處理整合系統

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4036075B2 (ja) * 2002-10-29 2008-01-23 豊田合成株式会社 ｐ型ＳｉＣ用電極の製造方法
US6969902B2 (en) * 2003-03-21 2005-11-29 Texas Instruments Incorporated Integrated circuit having antenna proximity lines coupled to the semiconductor substrate contacts
KR100562675B1 (ko) * 2003-11-04 2006-03-20 주식회사 하이닉스반도체 반도체 소자의 제조방법
DE102004021261B4 (de) * 2004-04-30 2007-03-22 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einem Hybrid-Metallisierungsschichtstapel für eine verbesserte mechanische Festigkeit während und nach dem Einbringen in ein Gehäuse
KR100568257B1 (ko) * 2004-07-29 2006-04-07 삼성전자주식회사 듀얼 다마신 배선의 제조방법
KR100703425B1 (ko) * 2005-04-21 2007-04-03 삼성전자주식회사 이동통신 단말기용 안테나 조립체
KR100711912B1 (ko) * 2005-12-28 2007-04-27 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 형성 방법
KR100731075B1 (ko) * 2005-12-29 2007-06-22 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
KR100712398B1 (ko) * 2006-02-28 2007-05-02 고창석 폐비닐 절단장치
US20070238309A1 (en) * 2006-03-31 2007-10-11 Jun He Method of reducing interconnect line to line capacitance by using a low k spacer
DE102007004860B4 (de) * 2007-01-31 2008-11-06 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Kupfer-basierten Metallisierungsschicht mit einer leitenden Deckschicht durch ein verbessertes Integrationsschema
US20130193445A1 (en) * 2012-01-26 2013-08-01 International Business Machines Corporation Soi structures including a buried boron nitride dielectric
US9048292B2 (en) 2012-10-25 2015-06-02 Micron Technology, Inc. Patterning methods and methods of forming electrically conductive lines
CN104347477B (zh) * 2013-07-24 2018-06-01 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US9231063B2 (en) 2014-02-24 2016-01-05 International Business Machines Corporation Boron rich nitride cap for total ionizing dose mitigation in SOI devices
US9269563B2 (en) * 2014-06-06 2016-02-23 Applied Materials, Inc. Methods for forming interconnect structure utilizing selective protection process for hardmask removal process
US10269706B2 (en) 2016-07-26 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5739579A (en) * 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
US5272117A (en) * 1992-12-07 1993-12-21 Motorola, Inc. Method for planarizing a layer of material
JP3695771B2 (ja) 1994-04-12 2005-09-14 シャープ株式会社 半導体装置及びその製造方法
US5641974A (en) 1995-06-06 1997-06-24 Ois Optical Imaging Systems, Inc. LCD with bus lines overlapped by pixel electrodes and photo-imageable insulating layer therebetween
US6069069A (en) * 1996-12-16 2000-05-30 Chartered Semiconductor Manufacturing, Ltd. Method for planarizing a low dielectric constant spin-on polymer using nitride etch stop
US6194321B1 (en) * 1998-08-19 2001-02-27 Micron Technology, Inc. Semiconductor processing methods utilizing boron and nitrogen, and semiconductor wafers comprising boron and nitrogen
US6165891A (en) * 1999-11-22 2000-12-26 Chartered Semiconductor Manufacturing Ltd. Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI423327B (zh) * 2006-12-26 2014-01-11 Lam Res Corp 降低後段製程配線結構之整體介電常數的處理整合系統

Also Published As

Publication number Publication date
EP1168433A2 (en) 2002-01-02
US6511908B2 (en) 2003-01-28
JP2002016135A (ja) 2002-01-18
KR100421824B1 (ko) 2004-03-12
KR20020000842A (ko) 2002-01-05
EP1168433A3 (en) 2004-04-14
US20020001939A1 (en) 2002-01-03
JP3696055B2 (ja) 2005-09-14

Similar Documents

Publication Publication Date Title
TW517310B (en) A method of manufacturing semiconductor devices
US7119441B2 (en) Semiconductor interconnect structure
US6352921B1 (en) Use of boron carbide as an etch-stop and barrier layer for copper dual damascene metallization
US7262505B2 (en) Selective electroless-plated copper metallization
KR100652120B1 (ko) 구리 보호층 및 열 전도체로서의 알루미늄 나이트라이드
US20020025653A1 (en) Method of forming multilevel interconnection structure having an air gap between interconnects
JP2000106396A (ja) 半導体装置の製造方法
JP3193335B2 (ja) 半導体装置の製造方法
US7586142B2 (en) Semiconductor device having metal-insulator-metal capacitor and method of fabricating the same
US6191031B1 (en) Process for producing multi-layer wiring structure
US6123992A (en) Method of forming aluminum interconnection layer
KR20070008108A (ko) 저 저항의 텅스텐막 형성 방법
US7452804B2 (en) Single damascene with disposable stencil and method therefore
US6699749B1 (en) Method for manufacturing a metal-insulator-metal capacitor
TWI690003B (zh) 用於形成雙鑲嵌互連結構的方法
JPH10172969A (ja) 半導体装置の製造方法
JP2023553604A (ja) セルフアラインされたトップ・ビア
KR100909174B1 (ko) 듀얼 다마신 패턴 형성 방법
TW512488B (en) Method for increasing heat dissipation of metal wires in integrated circuit
JPH11111842A (ja) 多層配線構造およびその製造方法
US20230178379A1 (en) Film deposition for patterning process
KR100668221B1 (ko) Ｍｉｍ 캐패시터 형성 방법
JPH1074837A (ja) 半導体装置及びその製造方法
JP3620520B2 (ja) 半導体装置の製造方法
TW594925B (en) Method of fabricating metal interconnects and method of filling openings

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees