TW499761B - Monolithic integrated semiconductor component - Google Patents

Monolithic integrated semiconductor component Download PDF

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Publication number
TW499761B
TW499761B TW090104134A TW90104134A TW499761B TW 499761 B TW499761 B TW 499761B TW 090104134 A TW090104134 A TW 090104134A TW 90104134 A TW90104134 A TW 90104134A TW 499761 B TW499761 B TW 499761B
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Taiwan
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charge carrier
region
carrier region
single crystal
contact
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TW090104134A
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Robert Plikat
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Bosch Gmbh Robert
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

499761 A7 B7 五、發明說明（/ ) [詳細說明] 本發明關於申請專利範圍第1項的引文的一種單晶積 體半導體構件。 [發明的背景] 上述種類的單晶積體半導體構件係習知者。舉例而言 ，它們包含一個垂直的MOS(金屬氧化物）(Metal-Oxide_ Silicon)電晶體，該MOS-電晶體包含一個第一種電荷載體 摻雜方式的較少摻雜的基質區域，及一個相同導電類型的 較多摻雜的層用於作接觸（流極）。至少有一個相反導電類 型的導電區域設入該基質區域中，該導電區域各圍住另一 個第一種導電類型的導電區域。 如此形成二個PN-過渡區，其中第一個PN-過渡區利 用一個源極端子短路。在基質表面設有一 MOS-構造，藉 之可將第二電荷載體區域的近表面區域的極性反向，如此 在源極端子與流極端子之間造成導電連接。第二電荷載體 區域經該源極端子與第三電荷載體區域成導電連接-第一 個PN-過渡區短路一因此形成一個寄生反向二極體。這種 強迫形成的寄生反向二極體在各種不同電路變更例中可當 作無載（空載）二極體(Freilaufdiode)使用。舉例而言，如果 要利此單晶積體半導體構件切換一個單晶積體半導體構件 的電感性的負載，則這種無載二極體可將電流作換流。舉 例而言，如果該電感性的負載用一個橋式電路[它由至少二 個MOS-電晶體構成，該MOS-電晶體接在高充電電路 (Hochsetzstellerschaltung)中當作脈波交替整流器 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 '297公爱） (請先閱讀背面之注意事項再填寫本頁) -·1« mas I .iff flu emmt i 一一OJa fli n n n 1 n e 線_· 經濟部智慧財產局員工消費合作社印製 499761 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（上） (Pulswechselrichter)]控制，則一第一 M〇S-電晶體受脈動 而控制，使該電感性的負載經由該另一 M0S-電晶體的寄 生反向二極體作無載運轉，或者經該受控制的第二M0S-電晶體作後充電。此處重要的是受脈動而控制的M0S-電 晶體的啓動過程，因爲此處的情形，反向二極體被電流所 流過，而電荷放出，因爲另一個M0S_電晶體不導通。如 此造成一種所謂的電流崩潰情況(Strom_Abrissverhalten) ’ 它造成陡的ΔΙ/Δί上升。這點再產生過電壓和高頻振盪’ 它們造成不想要的干擾影響。 習知技術係將肯特基二極體與沒有儲存電荷要從 MOS-電晶體的基質區域放空出來。在歐洲專利ΕΡ 0 899 791 Α2提到，將該肯特基二極體呈空載二極體形式整合到 該單晶積體半導體構件中， 其中需要做一道附加的電荷載體植入作業。但這一道 附加的電荷載體植入作業卻需要成本很大的技術成本，因 此提高了程序成本。 [本發明的優點] 具有申請專利範圍第1項所述的特點的單晶積體半導 體構件與之相較有一優點:可用簡單方式造成一個與該寄生 反向二極體並聯的肯特基二極體。由於該第一電荷載體區 域包含另一接觸區，其中此接觸區各依該第一電荷載體區 域的摻雜濃度而定在表面附近設有另一個較大摻雜濃度的 表面附近的電荷載體區域，且與該至少一個宵特基二極體 的陽極端子連接，因此如果該另一接觸區的電位拉到高於 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --------訂---------線 . 經濟部智慧財產局員工消費合作社印製 499761 B7____ 五、發明說明（）） 第二電荷載體區域的電位，則可在第一電荷載體區域中產 生一種受遮罩的構造。如此，可在較高偏壓的MOS-電晶體 的場合將所謂的「宵特基夾緊作用」設計得令人滿意’其 中崩潰電壓的必需的保險銲劑(Sicherheitszuschlag)…在注意 到電流電壓的容許誤差的情形下…可減少’甚至可不用注 意。由於保險銲劑量減到崩潰電壓時才熔化的量，因此在 通電流的情況由於保險銲劑造成的額外的電壓降就可避免 。因此崩潰電壓的容許誤差對該寄生反向二極體的接合電 壓(Junction voltage)沒有明顯影響，在較禹偏壓的MOS-電 晶體的場合，此接合電壓在各種情形下都要保持在650mv 以下，以避免該寄生反向二極體順向操作。 該第一電荷載體區域要改裝本發明只要設一些附加的 接觸區，這些接觸區可在製造該單晶積體半導體構件時用 簡單方式藉小小的程序的變更達成，其方法係在對源極端 子的接觸區析出金屬層時，同時至少設一個附加的遮罩開 口以供該附加的接觸區之用。因此附加的程序步驟就不需 要了。所需者只要將遮罩平面的構造作改變以製造金屬鍍 層。 利用該肯特基二極體(它可經該附加的接觸區放入該電 路裝置中）另外在該肯特基二極體斷路或導通的情形中可減 少損失的功率。利用在第一電荷載體區域中該附加的接觸 區下方產生的遮罩構造，使得經該宵特基二極體只會下降 一個較小的偏壓，因此對於肯特基二極體而言典型的很高 的偏壓電流可大大減少，或可反向做較小的流動電壓。 6 表紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） " (請先閱讀背面之注意事項再填寫本頁)
499761 A7 B7 五、發明說明（f) 此外還有一優點:可使該肯特基二極體很簡單地匹配該 單晶積體半導體構件。這種在外部接到該附加的接觸區的 宵特基二極體，舉例而言，可就變化的偏壓需求或熱的需 求而選出。最後一點，由於該宵特基二極體如今可用簡單 方式對MOS-電晶體構造做空間分離的設置，因此該肯特 基二極體的附加的損失功率係在某些區域中轉變成熱，在 這些區域中該損失的功率不會促成該單晶積體半導體構件 變熱。此外，在外部用簡單方式應用肯特基二極體有一好 處:當MOS-電晶體構造並聯時，不需使各電晶體構造都和 一個本身的肯特基二極體配合，而係可對數個電晶體構造 接一個共同的肯特基二極體。 本發明的其他較佳設計見於申請專利範圍所述的其餘 特點。 本發明在以下用實施例配合圖式詳細說明。圖式中： 第1〜第3圖係本發明的單晶積體構件的示意剖面圖’ 第4〜第9圖係本發明的半導體構件的各種不同的構造 圖。 [圖號說明] (10) 單晶積體半導體構件 (12) 漂移區域 (14)(16)電荷載體區域 (18) 層 (20) 金屬鍍層 (22)(24) PN-過渡區 7 表紙張尺度適用中國國家標準（cnS)A4^格（210 X 297公爱) " 一 ^ (請先閲讀背面之注意事項再填寫本頁) 訂--------線·, 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 499761 五、發明說明（t ) (26) 金屬鍍層(接觸區） (28) 金屬鍍層(接觸區） (30) 背特基二極體 (32) 區域 (34) 電荷載體區域 (36) 導電的連接部 [實施例的說明] 第1圖顯示一種單晶積體半導體構件（10)，該單晶積 體半導體構件設計成M0S_場效電晶體形式。此半導體構 件（10)包含一漂移區域（12)，該區域具有第一種電荷載體的 摻雜方式(例如摻雜成心型）。電荷載體區域（14)[其電荷載 體的摻雜方式與第一電荷載體區域(漂移區域)(12)的摻雜方 式相反](在此例中係摻雜成P-型)裝入該漂移區域（12)中。 其他的電荷載體區域(16)整合到此電荷載體區域（14)中。電 荷載體區域（16)的摻雜方式與第一電荷載體區域（12)的摻雜 方式相同，但摻雜量較高(在此例中爲n+_摻雜）。電荷載體 區域（12)設在一層（18)上，該層的摻雜方式與第一電荷載體 區域（12)的摻雜方式相同，但摻雜量較高(在此例中爲摻 雜）。的摻雜方式與第一電荷載體區域（12)的摻雜方式相同 ，但摻雜量較高(在此例中爲摻雜）。金屬鍍層(20)在半 導體構件（1〇)上構造化’該金屬鍍層(20)把電荷載體區域 (14)與（16)在其ΡΝ_過渡區(22)的區域中短路。在電荷載體 區域（14)與（12)之間的ΡΝ-過渡區(24)利用一種氧化物(圖未 示)設另一金屬鍍層(接觸區)(26)。在此，該金屬鍍層(26)延 8 ^&尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ' ~ (請先閱讀背面之注意事項再填寫本頁) -1 ----III — — ^ ·11111111 ‘ 499761 A7 ___B7 _ 五、發明說明（6 ) 伸到整個通道範圍。 電荷載體區域（12)利用第一導電類型(在此例中爲η+-摻 雜）的一個高摻雜的一個區域設以另一個金屬鍍層（接觸區 )(28)，該金屬鍍層(28)位在相鄰的PN-過渡區(24)之間。在 此，該金屬鍍層(28)與PN_過渡區(24)之間的間隔a係各相 等者。該金屬鍍層(28)與該金屬鍍層(20)經由外部的肯特基 二極體(30)連接，其中該金屬鍍層(28)各與肖特基二極體 (30)的陽極連接。 —金屬鍍層(20)構成該MOS_場效電晶體的源極端子， 層（18)構成其流極端子，而該金屬鍍層(26)該金屬鍍層(26) 構成其閘極端子。當閘極端子上有控制電壓時，在電荷載 體區域（H)中形成近表面的導線通道，因此源極端子與流 極端子連接導通，並使該MOS_場效電晶體受控制導通。 利用電荷載體區域（14)的總距離a+b+a可以定義:從何 種偏壓起，在該PN-過渡區(24)的範圍中該電荷載體區域 (12)的一個近表面的區域(32)(它作較高量的摻雜以作接觸) 保持在一個固定的電壓電位，此電壓電位不受流極電壓進 一步升高的影響。因此在區域(32)的電壓電位限制在一個 與幾何性質有關的常數(a+b+c)。因此這種經由金屬鍍層 (28)接觸的肯特基二極體(30)可設成供較小偏壓用者，此 偏壓由區域(32)中的電壓電位決定。因而區域(32)構成一個 供宵特基二極體(30)的電應用的遮罩構造，它造成上述的 偏壓的限制。如此同時使得肯特基二極體(30)的偏壓電流 以及功率的損失減少。此肖特基二極體(30)可以…肖特基 9 1 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) f: -----訂----------· 經濟部智慧財產局員工消費合作社印製 499761
五、發明說明（？） 二極體(30)用習知方式當作空載二極體使用例如在上述的 橋式電路的場合以將電感性的負載切換。 第2圖顯示一種變更的實施例，其中同樣的部分一如 第1圖用相同的圖號表示，且不再說明。與第1圖的實施 例(其中做一個源極側的流極接點)不同者’在第2圖中做 一個通道側的流極接點[在控制金屬鍍層(26)的場合’導線 通道經過電荷載體區域（14)]。關於功能，可參見第1圖的 說明。 第3圖所示實施例中，在電荷載體區域（14)之間設有 埋設的電荷載體區域(34) ’其電荷載體摻雜方式和電荷載 體區域（14)相同。電荷載體區域(34)設在一個格狀構造中’ 如此在該電荷載體區域（14)之間造成此處所示的導電的連 接部(36)。利用該埋設的構造(34)和導電的連接部(36)形成 習知的ΠΈΤ-構造，該JFET-構造在此處擔任區域(32)的一 遮罩構造。因此，在區域(32)中的電位上升亦受限制，這 點造成宵特基(3〇)的所需偏壓電壓的上述的減少作用。 第4~第9圖顯示該構件(1〇)的各種不同的構造的變更 方式的示意上視圖。在第4~第6圖係一種所謂的條帶設計 而在第7〜第9圖則係一種所謂的格室設計。各別的摻雜 區域係用第1~第3圖所述的圖號表示’故其設置可參考這 些圖。 在此，第4與第7圖對應於第1圖’第5與第8圖對 應於第2圖，而第6與第9圖對應於第3圖。 10 I紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ----—訂------ 線_· 經濟部智慧財產局員工消費合作社印製

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  1. 499761 A8 B8 C8 D8 六、申請專利範園 1.一種單晶積體半導體構件，具有一個具第一種電荷 載體摻雜方式的第一電荷載體區域（12)，至少二個具相反 的電荷載體摻雜方式第二電荷載體區域（H)，及具第一種 電荷載體摻雜方式的第三電荷載體區域（16)，以及至少一 個肯特基二極體(3〇);該第二電荷載體區域（14)在該第一電 荷載體區域（12)內互相間隔作構造化，第三電荷載體區域 (16)在該第二電荷載體區域（14)內作構造化，其中，在第二 電荷載體區域（14)和第三電荷載體區域（16)之間的一PN-過 渡區(22)經一接觸區(20)短路(源極端子），第一電荷載體區 域（12)設有一接點（18)(流極端子），且第二電載體區域（14) 可利用第一電荷載體區域（12)和第三電荷載體區域（16)之間 的區域中的一接觸區(26)反向，該宵特基二極體(30)與該電 荷載體區域（12)和該電荷載體區域（16)並聯，其特徵在：該 第一電荷載體區域（12)有另一接觸區(28)，該觸部(28)各依 第一電荷載體區域（12)的摻雜濃度而定在表面附近設以另 一個具較高摻雜濃度且位在表面附近的電荷載體區域(32) ，如此產生一種電阻式接點，與該至少一個背特基二極體 (30)的陽極端子連接。 2·如申請專利範圍第1項的單晶積體半導體構件，其 中： 該接觸區(28)設在一個遮罩構造(32)的區域中，該遮罩 構造(32)在施流極電壓時調整。 3·如申請專利範圍第1或第2項的單晶積體半導體構 件，其中： 1 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 P. 經濟部智慧財產局員工消費合作社印製 499761 A8 B8 C8 D8 六、申請專利範圍 該遮罩構造(32)由相鄰之第二電荷載體區域（14)的PN-過渡區(24)的距離(a+b+a)定義出。 (請先聞讀背面之注意事項再填寫本頁) 4. 如申請專利範圍第1或第2項的單晶積體半導體構 件，其中： 該單晶積體半導體構件（10)有一個源極側的流極接點 (18)。 5. 如申請專利範圍第1或第2項的單晶積體半導體構 件，其中： 該單晶積體半導體構件（10)有一個通道側的流極接點 (18)。 6. 如申請專利範圍第1或第2項的單晶積體半導體構 件，其中： 該遮罩構造(32)利用一個埋設的JFET-搆造(34)(36)定 出。 經濟部智慧財產局員工消費合作社印製
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DE50115196D1 (de) 2009-12-10
EP1259989B1 (de) 2009-10-28
JP2003526923A (ja) 2003-09-09
KR20020092369A (ko) 2002-12-11
HUP0300366A2 (en) 2003-09-29
KR100712165B1 (ko) 2007-04-27
DE10008545A1 (de) 2001-08-30
CZ20022847A3 (cs) 2003-03-12
US20040075135A1 (en) 2004-04-22
WO2001067515A1 (de) 2001-09-13
US6784487B2 (en) 2004-08-31

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