TW492109B - Process for manufacturing semiconductor device - Google Patents
Process for manufacturing semiconductor device Download PDFInfo
- Publication number
- TW492109B TW492109B TW090107719A TW90107719A TW492109B TW 492109 B TW492109 B TW 492109B TW 090107719 A TW090107719 A TW 090107719A TW 90107719 A TW90107719 A TW 90107719A TW 492109 B TW492109 B TW 492109B
- Authority
- TW
- Taiwan
- Prior art keywords
- connection hole
- layer
- insulating film
- opening
- item
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims description 33
- 238000009413 insulation Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 241000238631 Hexapoda Species 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 230000002079 cooperative effect Effects 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims 2
- 239000011229 interlayer Substances 0.000 abstract 5
- 239000010410 layer Substances 0.000 abstract 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 19
- 229910052760 oxygen Inorganic materials 0.000 description 19
- 239000001301 oxygen Substances 0.000 description 19
- 239000007789 gas Substances 0.000 description 12
- 238000000151 deposition Methods 0.000 description 11
- 230000008021 deposition Effects 0.000 description 9
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- QLOAVXSYZAJECW-UHFFFAOYSA-N methane;molecular fluorine Chemical group C.FF QLOAVXSYZAJECW-UHFFFAOYSA-N 0.000 description 5
- 238000001459 lithography Methods 0.000 description 4
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910002091 carbon monoxide Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002309 gasification Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000003682 fluorination reaction Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 230000036449 good health Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
A7 五、發明說明(i ) 發明背景 1 ·發明領域 本1明與製造半導體裝置的方法有關。尤其與具内層絕 、彖膜之半導體裝置製造方法有關,其中所形成之精細連結 孔,具高度方位比,並深達下部接線層。 2 ·相關技藝之描述 隧著所設計之半導體裝置之更小型化及接線之倍增,在 如乾蝕刻的小型化製程中,所需的精確度更高。例如,在 以蝕刻方式形成諸如接觸孔之連結孔時,在内層絕緣膜中 形成之連結孔直徑變小,且其方位比增加。導致顯著的微 負載效應(直徑愈小,蝕刻速率下降愈多,甚至無法蝕刻), 造成畸形接觸孔。 此外,在微影步驟後,連結孔與矽晶圓上的抗蝕劑薄膜 的面積比降低。因此在這樣的狀況下,爲達成適當的蝕刻 私度’需相對增加蝕刻電漿中的氟化碳氣體。而後,在連 t孔底郅因氟化碳氣體造成的沉積大幅增加,造成連結孔 電阻値的增加。例如,已知所採用的光罩,使得連結孔的 面積比(連結孔對晶片的面積比)高到電阻可降低約7% ,亦 即氟化碳的沉積降低;與採用光罩者相較,連結孔的面積 比降至約3% 。 ' 馬防止氟化碳氣體過量,已有人提出在電漿中加入少量 的含氧氣體,如氧氣或一氧化碳。然而,在此方法中的含 氧氣恤内的氧’會和抗触劑薄膜内的碳反應,形成一氧化 本紙張尺度_㈣國規格―χ 297_·么Cil----- ----------------- (請先閱讀背面之注意事項寫本頁) - .線· 經濟部智慧財產局員工消費合作社印製
發明說明( 經濟部智慧財產局員工消費合作社印製 “軍發.迨成柷蝕劑薄膜的減縮,並導致連結孔頂端擴 、言疋· ·ί準4 4邊緣(頂端無邊界容許邊緣)降低所致。亦 Ρ如連〜孔頂端擴張,會造成與連結孔頂端相連之金屬 接、’泉層(上4接線層)間,發生短路現象。所設計之連結孔與 接、’泉層間,一般均有一定程度的失準。但隨著半導體裝置 的日漸小担化,微影步驟中的對準容許邊緣亦隨之降低, 導致避免短路發生的困難。連結孔與接線層間的失準,稱 之爲頂部無邊界’’。 此外,如日本]Jnexamined專利申請號Hei 7(1995)_201994 中,已k出利用蝕刻内層絕緣膜之阻絕層的步驟,在連結 孔4外,另外形成一假連結孔之方法。依據此方法,在银 刻假連結孔時,姓刻氣體中釋出的氧,可排除額外的氣化 碳氣體,繼而控制氟化碳的沉積量。以此形成之連結孔, 具向度均勻性與再造性。 爲了控制氟化碳的沉積量,並形成如上述之具良組成、 私丨生佳,以及同再造性之連結孔,一般均在假連結孔另外 提供氧氣。但與一般引入含氧氣體的方法相較,此日本 Unexamined專利申請號Hei 7(1995)-2〇1994需要額外的步驟 .>几積蚀刻阻絕層;移除蝕刻阻絕層以形成連結孔;以及 沉積内層絕緣膜。此外,當假連結孔通抵蝕刻阻絕層時, 以一氧化矽形成之絕緣膜表面_不會露出,俾停止供給用來 控制氟化碳沉積量的氧。此舉是爲了考量抑制在連結孔底 部或側壁之氟化碳沉積量的增加。如在連結孔底部的氟化 碳沉積量過多,即有造成半導體裝置中電阻增加的缺失。 -5- 張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐)"—' -----
A7
發明概要 、依據本發明所提供之半導體裝置製造方法,具依序配置 部接線層、内層絕緣膜與上部接線層,以及在内層絕 f膜中,形成於下郅接線層之上的連結孔,其中連結孔的 氣備步騍爲·在内層絕緣膜上形成光阻層;並在光阻層上 形成開口,俾形成可露出内層絕緣膜底部之連結孔,以及 内層絕緣膜底邵未露出之假連結孔。 在本發明之圖1(a)中,所形成之抗触圖樣,是用來替代日 本unexamined專利申請號Hei 7(i995)_2〇i994提出的方法中 ’所需要之下列額外步驟:沉積蝕刻阻絕層;㈣蝕刻阻 矣巴層以形成連結孔;沉積内層絕緣膜;以及上述步驟中伴 隨 < 清洗步驟與檢查步驟。此外,本發明所顯現之效果, 與上述足先前技藝相同,其中只有以微影形成連結孔,以 及以此万式形成之連結孔的檢查步驟。此外,由於無須使 用蝕刻阻絕層,即可形成假連結孔,氧之供給可持續到以 蝕刻形成連結孔完成時。 在蝕刻之初,用來作爲假連結孔之開口的底部具有抗蝕 層。因此,考量到由内層絕緣膜供給之氧的量,較日本
Unexamined專利申請號Hei 7(1995)-201994 中,所揭一、的、 法少。但可知,因爲在蝕刻之初,連結孔的方位比較低, 所以蝕刻不會停止。在連結孔的方位比增加時,所需的氧 量確實會增加,亦即在蝕刻完成時。本發明中, , τ 在蚀刻完 成時,用來控制氟化碳沉積量所供給的氧是足夠的 當可提供氧之氣體(如氧氣或一氧化碳)盘一 ^ 人厂、兩又採用之蝕 -6-
492109 A7 B7 、發明說明( 刻氣體的量相當時,氧過量所導致的效應爲,内層絕緣膜 相對於下部接線層或抗蝕層之蚀刻速率降低。亦即,用來 控制氟化碳沉積量所需的氧量非常低,使得大量攜帶氣體 充入時,對其量之調整變得很困難。但在本發明中,可有 效供給所需氧量。 這些與其它本申請之目的,經參閱附圖即可清楚了解。 但須知這些本發明之較佳具體實施例,户斤才旨陳之細部描述 及特殊示例,概爲闡示之用,在本發明之精神與範疇内所 做之變化及改良,對熟悉此技藝者均可由詳細敘述中獲得 了解。 又 圖示簡述 圖1(a)至l(c)所示爲依本發明之半導體裝置製程步驟之概 略剖面圖。 較佳具體實施例之描述 本發明即將參酌附圖1(a)至1(c)敘述之。 經濟部智慧財產局員工消費合作社印製 依本發明所提出之半導體裝置製造方法,可解決上述問 題。尤値一提的是,在具内層絕緣膜之半導體裝置中,連 結孔深達下部接線層,而所形成之抗蝕圖樣3,使得供做假 連結孔之開口 4之底部抗蝕層厚度Υ,係由後述方法求得。 以已知方法形成之抗蝕圖樣3,使得供做假連結孔之開口 4具—受控深度(如圖1(a))。如-圖1(a)中的參考碼1爲下部接 線層;2爲内層絕緣膜;5爲連結孔之開口。例如,抗姓圖 樣係以日本Unexamined專利申請號Hei 9〇997)_33〇877所揭 示之方法形成。 用家標準(CNS)A4規格(210 X 297公爱— -7- A7
五、發明說明(5 ) 在假連結孔之開口内之内層絕緣膜之餘刻,須等到厚度γ 之抗I虫層蚀刻殆盡,露出内層絕緣膜後才開始。因此,供 做假連結孔之開口底部之内層絕緣膜的蝕刻,發生於供做 L、、’。孔之開口 5底部之内層絕緣膜的蚀刻之後(如圖1 (b))。 圖1 (b)中的參考碼4a表示假連結孔之開口,用來露出其底 邵之内層絕緣膜。如此一來,所形成之假連結孔仆即不會 像在内層絕緣膜上無蝕刻阻絕層時,深達下部接線層1(如 圖 1(c))。 本發明中的下部接線層,不僅是下部接線,且爲形成於 基板上之主動層。因此,連結孔即含接觸孔與介電孔。下 部接線層爲一金屬^,如鋁、銅及類似金屬,或爲雜質擴 散層。上邶接線層爲一金屬層,如鋁、銅及類似金屬。 在假連結孔之開口底部之抗蝕圖樣厚度γ的計算方法,敎 述如後。 ~ 首先,内層絕緣膜及用來形成連結孔與假連結孔之抗蚀 層區域的蝕刻速率,係分別在用來形成連結孔的蝕刻2況 下估算。例如,用來形成連結孔之内層絕緣膜的㈣速^ 爲A ;而内層絕賴及用來形成假連結孔之抗崎的蚀刻速 率分別爲B與C。此外’㈤來形成連結孔及假連結孔之内層 絕緣膜的蚀刻時間分別以t及t,表之。^之估算應與假連纟士^ 中I虫刻進行最快的部分有關。-因此,移除假連結孔底^抗 蝕層,以露出内層絕緣膜所需時間可由t_t,得知。假設在= 層絕緣膜中蝕刻出的假連結孔深度爲〇,抗蝕層之厚度γ爲 Y=cx(t-t,)。以t,=D/B代入,得到方程式(1): 卞又馬 -8 - 492109 A7 ------------- 五、發明說明(6 ) Y=Cx(t-D/B) I n -ϋ I* ϋ ϋ n I n n I 士4.x 0 i I (請先閱讀背面之注意事項}寫本頁) 由於B、C與t均爲已知量,對應於厚度〇之假連結孔底部 抗蝕層厚度,在符合Y<Z(Z爲部份未圖樣化之抗蝕層厚度) 的條件下,可由方程式(1)求出。連結孔之形成條件爲,深 度未達下部接線層,故Bxt,< χ(χ爲内層絕緣膜厚度)。此 狀況會導致Y>Cx (t-X/B)。因此,假連結孔開口底部之抗 蝕層厚度需大於Cx(t-X/B)。 示例 自此將以示例對本發明做更詳細的描述,但本發明並不 以其爲限。 下列不例爲採用臭氧/TEOS材質,以低壓化學氣相沉積 法形成之二氧化矽内層絕緣膜中,假連結孔之開口底部抗 蝕層的厚度計算。即使内層絕緣膜是以其它材質構成,計 算方式不變。 線」 採用臭氧/TEOS材質,以低壓化學氣相沉積法形成之二 氧化矽内層絕緣膜,之蚀刻狀況如下: 八氣化四峡/ττ氣化^一石反/氣=5/10/95sccm 經濟部智慧財產局員工消費合作社印製 (seem : 〇°C、一大氣壓下之流動速率(毫升)/分) 源/偏功率= 1.9/1.4仟瓦 氣壓= 0.67帕斯卡 源功率係用來以一ICP蝕刻機產生電漿,並對蝕刻氣體之 分離有所影響。施加於晶圓的是偏功率。偏功率愈大,被 -9 - ¥紙張;^過用中國國家標準(CNS)A4規格⑵〇 x 297公爱)~ ----—.__ 492109 A7 ---—- B7 五、發明說明(7 ) 吸引到晶圓之離子愈呈直線狀,使得蝕刻更具向異性。 在這樣的條件下,連結孔之開口底部内層絕緣膜的蝕刻 速率,經估算爲750奈米/分(=A)。絕緣膜及(χ)設定爲9〇〇奈 米的姓刻速率,分別爲72〇奈米/分(=Β)及25〇奈米/分(=〇:)。 例如’分別以金屬接線及二氧化矽絕緣膜做爲下部接線 層1及内層絕緣膜。内層絕緣膜之厚度(χ)設定爲9⑽奈米, 且未圖樣化之抗蝕層厚度(ζ)爲7〇〇奈米。 爲70成連結孔’實際所需之蚀刻時間t經估算爲 900/750x60 = 72秒。例如,在蝕刻完成後,所欲得到之絕緣 膜中的假連結孔厚度(D)爲5〇〇奈米,假連結孔之開口底部 的杬蝕層厚度約爲3〇〇奈米,可在方程式(1)中代入這些値求 得。 500奈米的厚度(D)僅爲示例。並不以之爲限,而且只要 假連結孔的深度未達到下部接線層,即可配合内層絕緣膜 之厚度足出。本發明之方法適用於連結孔之方位比(連結孔 之深度/直徑)爲5或更高處的狀況。本發明更適用於連結孔 之直徑爲260奈米或更小的狀況(直徑爲15〇至26〇奈米的狀 況較佳)。 所述之触刻條件、内層絕緣膜面積,及假連結孔之開口 面積’均爲示例,本發明並不以之爲限。 在本發明中,與連結孔相異區域之假連結孔之形成,與 具較南方位比之精細連結孔之蝕刻同時進行。因此,可減 少有多餘的氟化碳氣體,俾控制連結孔底部及側壁之氟化 -10 - 本纸張尺度適时國國家標準(CNS)A4規格(210 X 297公髮) (請先閱讀背面之注意事項再^寫本頁) :裝 -丨線· 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明( /几牙貝0如此一來,即可犯a 3占… 丨了形成具艮導電性質之組成良好之 連結孔。 在本敖明中’假連結孔之開口係以微影形成,不會露出 内層.巴.彖膜此外,内層絕緣膜之蚀刻形成假連結孔,係 錢結孔形成之彳m錢在内層絕賴提供触刻阻 絕層’即可形成不會料下部接線層之假連結孔。在以蚀 刻形成連結孔之初,會將假連結孔底部—定量的内層絕緣 膜移除。隨著蚀刻的進行’連結孔變得更深,氟化碳沉積 開始附著於連結孔底部及其側壁。此時㈣掉假連結孔之 開口底部之抗蚀層,並開始㈣内層絕緣膜,且開始產生 氧根。如此即可將上述沉積去除,並可持續連結孔之蚀 刻。 從上述論點觀之,本發明對半導體裝置之製造方法著有 貢獻’其户斤含之蚀刻連結孔(如接觸孔與介電孔)步驟,=基 於精細設計規則,對工業界具高度價値。 ,土 (請先閱讀背面之注意事項再¥寫本頁) 經濟部智慧財產局員工消費合作社印製 11 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
Claims (1)
- 申請專利範圍 1. 經濟部智慧財產局員工消費合作社印製 種半導體裝置製造古、Ά 甘El , ,^ ^ ^ ^ Ik万去,其具依序配置之下部接線屉 與上邵接線層,以及在内層絕緣膜中,二 : 接、’泉層〈上的連結孔,其中連結孔的製程步 馬:在内層絕緣膜上形成光阻層;並在光阻層上形成開 口,俾形成可露*内層絕緣膜底部之連結孔,以及内二 絕緣膜底部未露出之假連結孔。 曰 t申請專利範圍第1項之方法,其中的内層絕緣膜係由二 氧化矽材質層構成。 一 申Μ專利範圍第i項之方法,其中在形成光阻層中, 孔:、叙連結孔《開口後,執行電漿蝕刻於連結孔之 口底4 ’以形成内層絕緣膜中之連結孔,直到露出下 接線層。 申π專利la圍第3項之方法,其中假連結孔之開口底部 的光阻層厚度之決定,係由對光阻層 及内層絕緣膜之蝕 刻速率(計算得知,使得以電漿!虫刻來移除假連結孔 開口辰部的光阻層的時間,與以電漿蝕刻來移除連結 《開口底部的内層絕緣膜的時間相同。 5· t申請專利範圍第1項之方法,其中假連結孔開口底部 杬蝕層厚度大於Cx(NX/B)(其中^與匸分別爲内層絕緣狀 及光阻層的!虫刻速率;^名虫刻時間;内層絕緣膜厚 度)。 如申請專利範圍第2項之方法,其中採用臭氧/TE〇s材質 ’以低壓化學氣相沉積法形成之内層絕緣膜爲二氧化矽 2. 3. 4. 6· 本紙張尺度翻巾關家鮮(CNS)A4規格(21〇 X ^ -12- 公釐) 閱 讀 背 Φ 之 注 Ϊ 連 開 部 之 孔 之 膜 填撬1 寫 頁i 訂 線 492109 A8 B8 C8 D8 六、申請專利範圍 膜。 7. 如申請專利範圍第1項之方法,其中連結孔之方位比爲5 或更高。 8. 如申請專利範圍第1項之方法,其中連結孔之直徑爲260 奈米或更低。 9. 如申請專利範圍第8項之方法,其中連結孔之直徑爲1 5 0 至260奈米。 請 先 閱 讀 背 面 之 注 意 事 項 再 獬 本 頁 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000167644A JP3818828B2 (ja) | 2000-06-05 | 2000-06-05 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW492109B true TW492109B (en) | 2002-06-21 |
Family
ID=18670772
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW090107719A TW492109B (en) | 2000-06-05 | 2001-03-30 | Process for manufacturing semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (1) | US6337270B2 (zh) |
JP (1) | JP3818828B2 (zh) |
KR (1) | KR100434887B1 (zh) |
TW (1) | TW492109B (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100470125B1 (ko) * | 2002-09-09 | 2005-02-05 | 동부아남반도체 주식회사 | 복수레벨의 다마신 패턴 형성 방법 |
JP2005064226A (ja) * | 2003-08-12 | 2005-03-10 | Renesas Technology Corp | 配線構造 |
US20050045993A1 (en) * | 2003-08-28 | 2005-03-03 | Sanyo Electric Co., Ltd. | Semiconductor device with concave patterns in dielectric film and manufacturing method thereof |
JP2006196545A (ja) * | 2005-01-11 | 2006-07-27 | Toshiba Corp | 半導体装置の製造方法 |
JP5466102B2 (ja) * | 2010-07-08 | 2014-04-09 | セイコーインスツル株式会社 | 貫通電極付きガラス基板の製造方法及び電子部品の製造方法 |
US8786094B2 (en) * | 2012-07-02 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
FR3003962B1 (fr) | 2013-03-29 | 2016-07-22 | St Microelectronics Rousset | Procede d'elaboration d'un masque de photolitographie destine a la formation de contacts, masque et circuit integre correspondants |
JP2021028968A (ja) * | 2019-08-13 | 2021-02-25 | 東京エレクトロン株式会社 | 基板および基板処理方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3348322B2 (ja) | 1994-01-06 | 2002-11-20 | ソニー株式会社 | 半導体装置の製造方法 |
US5702982A (en) * | 1996-03-28 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits |
US5753417A (en) | 1996-06-10 | 1998-05-19 | Sharp Microelectronics Technology, Inc. | Multiple exposure masking system for forming multi-level resist profiles |
US6225207B1 (en) * | 1998-10-01 | 2001-05-01 | Applied Materials, Inc. | Techniques for triple and quadruple damascene fabrication |
-
2000
- 2000-06-05 JP JP2000167644A patent/JP3818828B2/ja not_active Expired - Fee Related
-
2001
- 2001-03-26 US US09/816,259 patent/US6337270B2/en not_active Expired - Lifetime
- 2001-03-30 TW TW090107719A patent/TW492109B/zh not_active IP Right Cessation
- 2001-06-04 KR KR10-2001-0031146A patent/KR100434887B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JP2001351896A (ja) | 2001-12-21 |
KR20010110197A (ko) | 2001-12-12 |
US20010049188A1 (en) | 2001-12-06 |
KR100434887B1 (ko) | 2004-06-07 |
US6337270B2 (en) | 2002-01-08 |
JP3818828B2 (ja) | 2006-09-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW462112B (en) | Method of forming multi-level coplanar metal/insulator films using dual damascene with sacrificial flowable oxide | |
TW492109B (en) | Process for manufacturing semiconductor device | |
TW413866B (en) | Method of etching doped silicon dioxide with selectivity to undoped silicon dioxide with a high density plasma etcher | |
JPH06326061A (ja) | 半導体装置の微細パターン形成方法 | |
TW440961B (en) | Method for fabricating semiconductor device | |
TW486755B (en) | Semiconductor device and manufacturing method of the device | |
TW471024B (en) | Lithography etching method | |
TW434719B (en) | Formation of alignment mark and structure covering the same | |
TW439173B (en) | Manufacturing method of capacitor having mixed-signal devices | |
TWI236729B (en) | Method for fabricating semiconductor device | |
TW488017B (en) | Semiconductor manufacture method of black silicon removal | |
TW201304056A (zh) | 半導體裝置內開口之形成方法 | |
TW379416B (en) | Method of manufacturing dual damascence | |
JP2002075961A (ja) | 半導体装置の製造方法 | |
TW200828500A (en) | Method of manufacturing openings and via openings | |
TW477035B (en) | Manufacturing method of plug structure | |
TW425632B (en) | Etching method of contact hole | |
TW436978B (en) | Method for making via while avoiding residual photoresist | |
TW426967B (en) | Fabrication method of node contact hole | |
JPH10163216A (ja) | 半導体装置の製造方法 | |
TW498426B (en) | Dry development method | |
TW512429B (en) | Dry development method using top surface imaging technology | |
TW409381B (en) | Process of avoiding producing the dishing after etching the silicide | |
TW426952B (en) | Method of manufacturing interconnect | |
TW449828B (en) | Method for etching oxide layer with a medium/low plasma density |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MM4A | Annulment or lapse of patent due to non-payment of fees |