TW486799B - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
TW486799B
TW486799B TW090107006A TW90107006A TW486799B TW 486799 B TW486799 B TW 486799B TW 090107006 A TW090107006 A TW 090107006A TW 90107006 A TW90107006 A TW 90107006A TW 486799 B TW486799 B TW 486799B
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TW
Taiwan
Prior art keywords
film
insulating film
opening
conductor
semiconductor device
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Application number
TW090107006A
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English (en)
Inventor
Kazutaka Shibata
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Rohm Co Ltd
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Publication of TW486799B publication Critical patent/TW486799B/zh

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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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486799 A7
I I I 請 先 閱 讀 背 之 注 意 事 項 再 填 •寫 頁 k 丁
五、發明說明(2 方法係可提昇具有連接零件之半導體裝置的生產性 I、此外,本發明之其他目的在於提供一種半導體裝置的 製造方法’係可以短時間在半導體基板上的絕緣膜表面形 成附著性良好之低電阻導體膜。 本發明之半導體裝置係包含··設置於半導體基板上之 電性連接用銲墊;被覆上述半導體基板表面的同時,具有 1使上述銲墊路出之第1絕緣膜,·在第1絕緣膜的上述 開口底面上接合於上述銲墊,並延伸到上述開口外的上述 第1絕緣膜表面所形成的導體膜;被覆此導體膜的同時, 具有開口使部分導體膜露出之第2絕緣膜;以及在第2絕 緣膜的上述開口内,配置與上述導體臈相接合之連接構件 如上所述之半導體裝置可藉由包含以下之製造方法來 製作··以具有開口使上述銲墊露出之第丨絕緣膜被覆設置 電性連接用銲墊片之半導體基板表面之製程;將第〗絕緣 膜的表面以及上述開口的内壁面改質之製程;透過離子交 換反應形成薄導體膜來被覆在上述第丨絕緣膜表面、上述 開口的内壁面以及上述開口的底面所露出的上述銲墊的表 面之製程;藉由使用上述薄導體膜來供電之電解電鍍法, 使上述薄導體膜厚膜化之製程;被覆上述已厚膜化之導體 膜的同時,形成具有開口露出部分導體膜之第2絕緣膜的 製程;以及在上述第2絕緣膜的上述開口内,形成與上述 已厚膜化之導體膜相接合之連接構件的製程。 根據該方法,藉由將第1絕緣膜表面以及形成於第 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) ^^1 « ^ ^---- (請先閱讀背面之注意事項再填寫本頁) Μ*· MM 9W 醫 秦丨 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 制 486799 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(3 ) 絕緣膜之開口的内壁面改質,在被改質的表面上,透過離 子交換反應可形成附著性良好之薄導體膜。由於利用該薄 導體臈可進行供電,故利用電解電鍍法,可使薄導體膜厚 膜化。透過電解電鍍法之薄導體膜的厚膜化,由於可在短 時間進行,其結果,可在第1絕緣膜上迅速形成附著性良 好之厚膜狀導體膜。之後,用第2絕緣膜被覆已厚膜化之 _導體膜,在第2絕緣膜上形成開口,在該開口内形成與上 述已厚膜化之導體膜相接合之連接構件。 上述第1絕緣膜的表面改質處理也可以是在第丨絕緣 膜表面導入陽離子交換基之處理。藉由將已施行表面改質 處理乏第1絕緣膜的表面接觸於包含可構成導體膜之金屬 材料的離子之水溶液,可使之產生離子交換反應。透過離 子交換反應,使金屬離子與陽離子交換置互換,而吸附於 弟1絕緣膜的表面。 上述連接零件也可以是與其他固體裝置(例如其他半 導體晶片或是配線基板)相連接之凸塊。 此外,上述連接構件也可以是在第2絕緣膜的開口底 面上接合於導體膜,並延伸至第2絕緣膜表面之其他導體 膜。在此情況下,藉由第2絕緣膜之被絕緣的2層導體膜, 藉此構成所謂多層配線構造。 上述第1絕緣膜也可由聚醯亞胺樹脂構成。在此情況 下,第1絕緣膜的表面以及形成於第丨絕緣膜之開口内壁 面的改質處理也可以是例如使用氫氧化鉀水溶液使聚醯亞 胺樹脂的亞胺環裂開,將作為陽離子交換基之羧基導入第 -------------*裝--------訂-------,i線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 3 312481 486799 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明(4 ) ^絕緣膜表面之處理。之後,藉由將第i絕緣膜浸潰在包 含可構成連接零件之金屬材料的離子的水溶液中,可在= 1絕緣媒的表面產生離子交換反應,㈣】絕緣膜的表面 及其開口的内壁面與銲墊的表面形成由該金屬材料構成的 連接構件。 第1絕緣膜的材料方面,除了聚醯亞胺樹脂,也可採 用例如’環氧樹腊。在此情況下,第i絕緣膜的表面改^ 處理也可以疋藉由將第i絕緣膜浸潰在硫酸水溶液中,將 作為陽離子交換基之績基導入其表面之處理。將已表面改 質處理之環氧樹脂膜浸潰在含有金屬離子的水溶液中引起 離子交換反應,則此金屬離子吸附在第!絕緣臈的表面。 第1絕緣膜的材料方面,也可採用結合亞胺或結合酸 或是包含結合胺以及結合酸兩方之樹脂等。 上述第2絕緣膜與第1絕緣膜的情況相同,採用聚醯 亞胺樹脂或環氧樹脂,其他也可將包含結合亞胺、結合酸 或是結合亞胺以及結合酸兩方之樹脂等當作構成材料來使 用。尤其,透過第2絕緣膜使用已絕緣之一對導體膜來形 成多層配線構造的情況下,最好使用聚醯亞胺樹脂或環氧 樹脂作為第2絕緣膜的構成材料,針對第2絕緣膜的表面 及其開口的内壁面來施行如上所述之表面改質處理。 本發明其他形態之方法係包含:在半導體基板上形成 絕緣膜之製程;將絕緣膜表面改質之製程;在已改質之絕 緣膜的表面透過離子交換反應形成薄導體膜之製程;以及 藉由利用上述薄導體膜供電之電解電鍍法,使上述薄導 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -----------裝·-------訂·-------- (請先閱讀背面之注意事項再填寫本頁) 五、發明說明(5 ) 臈厚膜化之製程。 根據該方法,藉由持續絕緣膜的表面改質處理來進行 離子交換反應,可在絕緣膜的表面形成附著性良好之薄導 體臈。接著,利用電解電鍍使薄導體膜厚臈化,其結果, 可短時間在絕緣膜上形成附著性良好之低電阻導體膜。藉 此,可提昇半導體裝置的生產性。 、" 口本發明中上述之說明、或是其他目的、特徵以及效果, 可參照所添付之圖示並透過以下所述之實施形態的說明即 可明瞭。 [發明之實施形態] 第1A圖至第1E圖為按製程順序所顯示之本發明第1 實施形態的半導體裝置製造方法的剖視圖。在半導體晶圓 W(半導體基板)的表面上設置複數件元件形成領域以對應 於複數個半導體晶片,係利用劃線領域L來區分複數件元 件开y成領域。劃線領域L係利用切割鑛刀沿著從晶圓w切 割出各個半導體晶片時的切斷線領域。 在對應於各個半導體晶片之元件形成領域上將與其他 固體裝置(半導體晶片或是配線基板等)電性連接之銲塾p 設置於活性面Wa。此銲墊P從覆蓋活性面Wa之第1聚醯 亞胺膜11(第1絕緣膜)所形成的開口 lla露出。使電性連 接之内部配線之一部分露出於埋設於活性面Wa之電晶體 或電阻器等功能元件所構成的内部電路。 係如第1B圖所示,在活性面Wa形成第1聚酿亞胺膜 11之第1A圖的狀態下形成薄導體臈21a。此薄導體膜21a 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 請 先 閱 讀 背 面 之 注 意 事 項 再 填 , 襄裝 頁 訂 線 經濟部智慧財產局員工消費合作社印製 312481 五、發明說明(6 的形成方面,例如,可採用「有關利用聚醯亞胺樹脂及環 氧4樹脂的表面改質之Direct Metallization的基礎研究」(繩 舟等’電子實裝學會誌V〇 1.2 No5( 1999),pp390-393)以及 「 利用聚酿亞胺樹脂的表面改質之Co/Pt多層膜的製作以 及磁性特性」(田村等,表面技術協會第99屆演講大會要 旨集(1999),pp35_36)等所提出的方法。 亦即’針對第1聚醯亞胺膜11的表面以及開口 11 a 的内壁面施行表面改質處理。此表面改質處理具體而言, 係將形成第1聚醯亞胺膜11之第1A圖之狀態的半導體晶 圓W次潰在氫氧化鉀水溶液中,藉此使在第丨聚醯亞胺膜 11表層部分之亞胺環裂開,然後透過將羧基導入第1聚醯 亞胺膜11的表面來進行。 如此一來針對已施行表面改質處理之第i聚 =二由離子交換反應,可以良好的附著性設置薄 亞胺膜!二離子父換反應’係例如,將針對第1聚醯 生表面施行表面改質處理後的狀態的半導體 ,在含有金屬離子之水溶液中來進行。例如、主 在硫酸銅水溶液中,作為薄導體膜21a之鋼 置二 第1聚醯亞胺膜U的表面以及開口 ! 、1又置於 Ρ的表面。 Ν壁面以及銲墊 然後在第1聚酿亞胺膜11的表面形成薄導體膜21 後,藉由利用薄導體膜21凌 駿膜21a 寸〒肢联來供電之電解電 1C圖所示,形成厚導俨膣 又去,係如第 心欣与導體膜21。亦即,透過電 薄導體膜21a厚臈化,萨此. 電鍍法使 ,_電阻化之導體模21形成
本紙張尺度顧中國國家標準(CNS)A4規格(21〇 X " 312481 486799 經濟部智慧財產局員Μ消費合作社印製 312481 A7 五、發明說明( 於第1聚醯亞胺膜11的表面。電解電鍍時的供電可透過將 劃線領域L中的薄導體膜21a連接於電極來進行。 由於可在短時間使用電解電鍍法進行薄導體膜21的 厚膜化,故經由離子交攀反應之薄導體膜21的形成及其厚 膜化所形成的導體膜21可在短時間之製程中完成。 其次,係如第1D圖所示,在第χ聚醯亞胺膜u的表 I面讓抗#劑膜15形成圖案。也可在進行光阻膜ι5的形成 之前,在已厚膜化之導體膜21a上對應於開口 Ua之部分 所形成的凹部2 5埋入絕緣材17。 接者’藉由將抗姓劑膜15作為遮罩之钱刻,導體膜 21即圖案化。之後,係如第1E圖所示,抗蝕劑膜15剝離, 形成第2聚醯亞胺膜12(第2絕緣膜),以供被覆導體臈21 的表面和透過將導體膜21不要的部分蝕刻去除而露出之 第1聚酸亞胺膜11的表面。在第2聚醯亞胺膜12上,於 避開第1聚醯亞胺膜11的開口 lla處形成開口 i2a。然後 在開口 12 a内設置凸塊b。 在劃線領域L·中於第丨聚醯亞胺膜丨丨形成開口 j lb 後,藉由從開口 11b露出的導體膜21供電進行電解電鍍, 可迅速地形成凸塊B。凸塊B係透過電解電鍍法之快速製 程,掩埋開口 12a,並形成從第2聚醯亞胺膜12的表面隆 起的厚臈狀。 之後’使用切割鋸刀沿著劃線領域L切斷晶圓w,藉 此可得到各片半導體晶片。 如以上所述,根據本實施形態,藉由第1聚醯亞胺臈 巧長 (CNS)A4 規^^_公爱)---- ----------------I--I I ^ · I I I----- * (請先閱讀背面之注意事項再填寫本頁) 牝6799 A7 _________ B7 五、發明說明(8 ) 在經由離子交換反應 此外,透過電解電鍍 藉此,可提昇半導體 (請先閱讀背面之注意事項再填寫本頁) 11的表面改質處理與針對表面改質處理後之第1聚醯亞胺 膜11的表面進行離子交換反應,而形成薄導體膜21a。接 著,藉由將該薄導體膜21a厚膜化,可使低電阻化之導體 膜21设置於第1聚醯亞胺膜丨丨上 形成導體膜21時,不需過多的時間 可加速進行薄導體膜2;^的厚膜化 晶片的生產性。 如第1E圖所示,依照本實施形態的方法所製作的半 導體晶片在形成從第1聚醯亞胺膜u之開口 Ua偏離處, 具有凸塊B以供作為與其他固體裝置的連接構件。其結 果,在凸塊B與作為半導體基板之晶圓w的活性面wa之 間,隔有.第1聚醯亞胺膜U。如上所述之構造在與其他固 體裝置接合時,凸塊B承受的壓力對在半導體基板(晶圓 W)未直接作用之點有利。此外,在其他固體裝置與該半導 體晶片的活性面Wa之間,由於陪古势Ί ^ J田於隔有第1以及第2聚醯亞 胺膜11、12’可使固體裝置盘該丰逵神 、系牛導體晶片等的熱膨脹係 數吸收良好。如此^一來,可古7立丨rm 了有放抑制因半導體基板熱膨脹 經 濟 部 智 慧 財 產 局 員 工 消 費 合 社 印 製 差所產生的應力。 第2圖係說明本發明第2 f絲形萨 t 乐貫施形恶之半導體裝置之製 造方法的圖解剖視圖。第2圖中,對庵^ 口 r對應於上述第1A圖至 第1E圖所示之各部分,標上與第 、乐iA圖至第1E圖相同之 參考付號。 在第2實施形態中,在晶圓w 卸〜上形成多層配線構造。 亦即,在第2聚醯亞胺膜12的表面报 > 姑 刃衣面形成第2導體膜22。 ^紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 8 312481
五、發明說明( 此 著開口 12a的内璧面開始’ 的表面 第2導體獏22係在形成 底部與第1導體膜接合2聚醯亞胺膜12的2a 並延伸到第2聚醯亞胺獏12 第2導體膜2 2係盘第 .〇弟1導體膜21相同,町透過製程 來形成。亦即,與第1聚 邳 相同,進行第7安妒 胺瞑11的表面改質處理情況 ^ 1J進仃第2聚醯亞胺臌 ,^ P ^ 、 2的表面改質處理0然後’如 丨此在已施仃表面改質處理 ^ * Μ ^ ^ ^ 第2聚醯亞胺膜12的表面,猎 田才彳用離子父換反應而形 銀„】 厚 >體膜。由於該薄導體膜接 觸開口 12a中的第1導體 m太,、 膜21,故藉由從第1導體膜21 的供龟,使形成於第2聚酸& 亞胺膜12上之薄導體膜經由電 解電鍍法厚膜化,並可設 上之薄分 置尽膜狀之導體膜22。雖然第2 導體膜22在對應開口 12a舍a ^ 處具有凹部26,但凹部26隨需 要填充絕緣材2 7。 第2導體膜22隨需要而R # 而要而圖案化。之後,形成絕緣膜 13(例如,聚醯亞胺膜)以供 J 供覆盖第2導體膜22與透過第2 導體膜22的圖案化而露出之第2聚醯亞胺膜_表面。 在此絕緣膜u上,於避開開口 12a處形成開口 na。在此 開 上埋入凸塊B。在劃線領域L·中於絕緣膜13形成 開口 13bS ’藉由隔著劃線領域L中的第i導體膜?!以 及第2導體膜22來供電,可使用電解電鍍法來形成凸塊 B。 根據如上所述之第2實施形態,藉由聚醯亞胺膜的表 面改質處理與離子交換反應下的薄導體膜的形成、以及經 由電解電鍍法的薄導體膜的厚膜化,可在晶圓w上設置2 iH·· a··^ MM* MM· W· I I MM· CUM I I · · n I n flu n n an 一 a n mem9 n n an n n f (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧'財產局員工消費合作社印製
486799 A7 B7 五、發明說明(10) 層構造之配線。 以上’雖然已經說明本發明之2種實施形態,但本發 明也可在其他形態下實施。例如在第1實施形態以及第2 實施形癌中’雖然使用聚醯亞胺樹脂作為第i以及第2絕 緣膜的材料,但也可使用環氧樹脂。在此情況下,表面改 質處理也可透過將環氧樹脂膜所形成的晶圓浸潰在硫酸水 溶液中’藉此在環氧樹脂膜的表面進行磺基的導入處理最 好。接著,經由離子交換反應,使磺基與金屬離子交換, 可在環氧樹脂膜的表面形成薄導體膜。 此外’上述第1以及第2實施形態中,雖然在第1以 及第2導體膜21、22上的凹部25、26填充絕緣材17、27, 但絕緣材17、27的填充也可省略。 此外,導體膜21、22的材料方面,除了銅,也可使用 始或鎳等其他良導性金屬材料。凸塊B的材料也是一樣, 不過最好使用與導體膜21、22相同的材料。 此外’上述第2實施形態中,雖然已經說明在晶圓w 的活性面Wa上設置2層構造的配線的實施例,但同樣地 也可形成3層以上的多層配線構造。 此外,上述第1以及第2實施形態中,雖然已經說明 第1以及第2絕緣膜均可由聚醯亞胺樹脂構成的實施例, 但也可如上述由環氧樹脂構成,或是第1以及第2絕緣膜 由不同絕緣性樹脂材料構成。 雖然已經詳細說明本發明之實施形態,但這只不過為 了說明本發明之技術性内容所提出的具體實施例,本發明 (請先閱讀背面之注意事頊再填寫本頁) I ----------訂---- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 10 312481 486799 A7 B7 五、發明說明(η ) 之解釋並不限於這些具體實施例,本發明的精神以及範圍 僅限於所添附之申請專利範圍。 本項申請可對照於2000年3月28曰在曰本國特許廳 (專利局)所提出之特願2000-89174號,本項申請之所有揭 示者係從當中引用並歸納形成。 [圖面之簡單說明] 籲 第1A圖至第1E圖為按製程順序所顯示之本發明第1 實施形態的半導體裝置製造方法的剖視圖。 第2圖為說明本發明第2實施形態之半導體裝置製造 方法的圖解剖視圖。 (請先閱讀背面之注意事項再填寫本頁} 經濟部智慧財產•局員工消費合作社印製 第3圖為說明在半導體基板的活性面上形成凸塊之以 往技術的剖視圖。 [元件符號] la、lib、12a、13a、13b、53 開口 11 第1聚醯亞胺 12 第2聚醯亞胺 15 抗姓劑膜 17、27 絕緣材 21 第1導體膜 21a 薄導體膜 22 第2導體膜 51 半導體基板 51a 、Wa 活性面 52、P 銲墊 54 聚醯亞胺膜 55、B 凸塊 L 劃線領域 W 半導體晶圓 ^紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 11 312481

Claims (1)

  1. 486799 、申請專利範圍 h 一種半導體裝置係包含: 設置於半導體基板上之電性連接用鲜塾; 被覆上述半導體基板表面的同時,具有開口使上述 鲜墊露出之第1絕緣膜; 在第1絕緣膜的上述開口底面上接合於上述銲 塾’並延伸到上述開口外的上述第 的導體膜; 4第1、,·邑緣膜表面所形成 被覆導體膜的同時,具有開口使此導體膜露出之第 2絕緣膜;以及 在第2絕緣膜的上述開口内’配置與上述導體膜相 接合之連接構件。 2·如申請專利範圍第!項之半導體裝置,其中,上述連接 零件包含:與其他固體裝置相連接之凸塊。 3. 如申請專利範圍第!項之半導體裝置,其令,上述連接 零件包含:在上述第2絕緣臈的上述開口底面上接合於 上述導體膜,並延伸到上述開口外的上述第2絕緣膜表 面所形成的其他導體膜。 、 4. 如申請專利範圍第!項至第3項之任一項的半導體裝 置,其中’上述第1絕緣膜至少包含結合亞胺或結合酸 之其中一種的樹脂。 5·如申請專利範圍第4項之半導體裝置,其中,上述第2 絕緣膜至少包含結合亞胺或結合酸之其中一種的樹 I 6·如申請專利範圍第丨項至第3項之任一項的半導體裝 本紙張尺度適用巾闕家鮮(CNS)A4規格(21G X 297公爱) 12 裝 312481 A8 B8 C8 D8
    7 "too /yy 申請專利範圍 置,其中,上述第2絕緣膜至少包含結合亞胺或結合酸 之其中一種的樹脂。 一種半導體裝置的製造方法係包含·· 以具有開口使上述銲墊露出之第丨絕緣膜被覆設 置電性連接用銲墊之半導體基板表面之製程; 又 將第1絶緣膜表面以及上述開口的内壁面改質之 製程; 透過離子交換反應形成薄導體膜來被覆在上述第i 絕緣膜表面; 上述開口的内壁面以及上述開口的底面露出的上 述銲墊的表面之製程; 藉由使用上述薄導體膜來供電之電解電鍍法,使上 述薄導體膜厚膜化之製程; 被覆上述已厚膜化之導體膜的同時,使具有開口露 出此導體膜之第2絕緣膜形成之製程;以及 在上述第2絕緣膜的上述開口内,形成與上述已厚 膜化之導體膜相接合之連接構件的製程。 予 8·如申請專利範圍第7項之半導體裝置的製造方法,其 中,上述連接構件包含與其他固體裝置相連接之凸塊。 9.如申請專利範圍第7項之半導體裝置的製造方法,其 中,上述連接構件方面,在上述第2絕緣臈的上述開〔 底面上接合於上述導體膜,並延伸到上述開口外的上述 第2絕緣膜表面所形成的其他導體膜。 10.如申請專利範圍第7項至第. L__ 弟乂項之任一項的製造方法, 本紙張尺度適用_國國家標準(CNS)A4規格(210 X 297公爱) 13 312481 --------------^ i 1 (請先閱讀背面之注意事項再填寫本頁)
    · 線· 486799 A8 B8 C8 D8
    、申請專利範圍 其中,上述第1絕緣膜至少包冬社入兀如』 ^ ^ 匕S結合亞胺或結合酸之其 中一種的樹脂。 /、 U.如申請專利範圍第10項之製造方法,其中,上述第2 絕緣膜至少包含結合亞胺或結合酸之其中_種的樹 脂。 12·如申請專利範圍第7項至第9項之任—項的製造方法, 其中,上述第2絕緣膜至少包含結合亞胺或結合酸之其 中一種的樹脂。 13· 一種半導體裝置的製造方法係包含: 在半導體基板上形成絕緣臈之製程; 將此絕緣膜表面改質之製程; 在已改質之絕緣膜的表面透過離子交換反應形 薄導體膜之製程;以及 ^ Α 藉由利用上述薄導體膜來供電之電解電鍍法, 述薄導體膜厚膜化之製程。 上 (請先閱讀背面之注意事項再填寫本頁) -裝 I----^ --------I 1 . 經濟部智慧財產局員工消費合作社印製 泰纸張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 3 U481
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JP2001230341A (ja) * 2000-02-18 2001-08-24 Hitachi Ltd 半導体装置
US6731839B2 (en) 2000-07-31 2004-05-04 Corning Incorporated Bulk internal Bragg gratings and optical devices
JP3534717B2 (ja) * 2001-05-28 2004-06-07 シャープ株式会社 半導体装置の製造方法
JP3829736B2 (ja) * 2002-02-28 2006-10-04 凸版印刷株式会社 チップサイズパッケージの製造方法
US7579681B2 (en) * 2002-06-11 2009-08-25 Micron Technology, Inc. Super high density module with integrated wafer level packages
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JP4758813B2 (ja) * 2006-04-26 2011-08-31 新光電気工業株式会社 実装基板
JP2006295209A (ja) * 2006-06-26 2006-10-26 Rohm Co Ltd 半導体装置
JP4273356B2 (ja) * 2007-02-21 2009-06-03 セイコーエプソン株式会社 半導体装置の製造方法
US8642469B2 (en) * 2011-02-21 2014-02-04 Stats Chippac, Ltd. Semiconductor device and method of forming multi-layered UBM with intermediate insulating buffer layer to reduce stress for semiconductor wafer
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