TW466720B - Semiconductor package with flash-prevention structure and manufacture method - Google Patents
Semiconductor package with flash-prevention structure and manufacture method Download PDFInfo
- Publication number
- TW466720B TW466720B TW089109804A TW89109804A TW466720B TW 466720 B TW466720 B TW 466720B TW 089109804 A TW089109804 A TW 089109804A TW 89109804 A TW89109804 A TW 89109804A TW 466720 B TW466720 B TW 466720B
- Authority
- TW
- Taiwan
- Prior art keywords
- lead frame
- patent application
- scope
- semiconductor package
- item
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 230000002265 prevention Effects 0.000 claims abstract description 23
- 229920001971 elastomer Polymers 0.000 claims description 44
- 239000003292 glue Substances 0.000 claims description 26
- 238000000465 moulding Methods 0.000 claims description 17
- 238000005476 soldering Methods 0.000 claims description 17
- 238000004806 packaging method and process Methods 0.000 claims description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 11
- 238000003466 welding Methods 0.000 claims description 9
- 238000005538 encapsulation Methods 0.000 claims description 7
- 239000000853 adhesive Substances 0.000 claims description 6
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 4
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000004593 Epoxy Substances 0.000 claims description 2
- 239000000084 colloidal system Substances 0.000 claims description 2
- 229920001296 polysiloxane Polymers 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims description 2
- 241000237536 Mytilus edulis Species 0.000 claims 1
- 239000003822 epoxy resin Substances 0.000 claims 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims 1
- 235000020638 mussel Nutrition 0.000 claims 1
- 239000004033 plastic Substances 0.000 claims 1
- 229920003023 plastic Polymers 0.000 claims 1
- 229920000647 polyepoxide Polymers 0.000 claims 1
- 239000009719 polyimide resin Substances 0.000 claims 1
- 229920005749 polyurethane resin Polymers 0.000 claims 1
- 229920005989 resin Polymers 0.000 abstract description 19
- 239000011347 resin Substances 0.000 abstract description 19
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 239000002390 adhesive tape Substances 0.000 abstract description 4
- 238000012858 packaging process Methods 0.000 abstract description 3
- 210000002414 leg Anatomy 0.000 description 9
- 239000002904 solvent Substances 0.000 description 6
- 229920000642 polymer Polymers 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 239000007769 metal material Substances 0.000 description 4
- 239000011368 organic material Substances 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000002079 cooperative effect Effects 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 210000003127 knee Anatomy 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052689 Holmium Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 230000005574 cross-species transmission Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- KJZYNXUDTRRSPN-UHFFFAOYSA-N holmium atom Chemical compound [Ho] KJZYNXUDTRRSPN-UHFFFAOYSA-N 0.000 description 1
- -1 inscription Inorganic materials 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
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- 229910000679 solder Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49558—Insulating layers on lead frames, e.g. bridging members
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
經濟部智慧財產局員Μ消費合作?i.s*i: A7 ____B7______ 五、發明說明(1 ) [發明領域] 本發明係關於一種半導體封裝件,尤指一種半導體晶 片與銲線外露於封裝膠體上所形成之開槽中的半導趙封裝 件及其製法。 [先前技藝說明] 隨電子產品之日新月異’針對不同功能之需求與不同 產品之規格需求’電子產品中所使用之半導體封裝件 (Semiconductor Package)遂愈趨多樣化,例如,導腳四面 排列之裝置(QFP)、球柵陣列裝置(Bga)、薄型裝置(TS〇p) 及影像偵測裝置(Image Sensor Device)等。 上述影像偵測裝置之結構大致上係在一具晶片座及導 腳之導線架上形成一具開槽之封裝膠體,使導線架供半導 體a日片黏著之aa片座及導腳上供金線鲜接之部位外露於該 開槽中’再以一蓋件封蓋至該封裝膠體上,以使該半導體 晶片及金線與外界氣密隔離。此種裝置之結構由於須在上 片(Die Bond)及銲線(Wire Bond)作業前,先將封裝膠體成 型於該導線架上,故在模壓製程中往往導致晶片座及導聊 外露於該開槽中之部位為形成該封裝膠體之封裝樹脂所污 染1即所謂之溢膠(F丨ash),若不予以去除(De_flash),則會 影響至晶片座與半導體晶片間之黏接品質以及導腳與金線 間之銲接品質因而,封裝業界對上述問題提出諸多去除 溢醪之方法惟該等方法均仍存在有缺點而不盡理想:故 美國專利第5、070;〇4 I號案即揭示Γ另.種去除溢勝之方 法 冀以解決習知方法之缺點 —«limn-»!-..·!»! r- --1 II ,,,,,,, ( ^丨''恨疋戈遝甲。固@家標準(CNS;A4規格i.:nc):< ::>丨9了公爱; τ----------~ I n D n 1 I» i i n 』OJ· n n n n I {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 6 6 7 2 0 A7 --B7 五、發明說明(2) 該獲准專利之方法係包括下列步驟:丨)將導線架欲外 露於封裝膠體之開槽令的部位先塗覆一層高分子有機物 質,且該高分子有機物質之熔點高於用以形成封裝膠體之 封裝樹脂;2)於該導線架上形成一具開槽之封裝膠體;3) 將包覆有該導線架之封裝膠體浸入一可溶解該高分子有機 物質而不會溶解該封裝膠體之溶劑中;4)將一半導體晶片 黏著至該導線架之晶片座上,再以銲線連接該半導體晶片 與導線架;以及5)黏接一蓋片至該封裝膠體上以封蓋該開 該方法維較習知者為佳,然而,仍具有下列之缺點: 首先,該高分子有機物質係以溶劑溶除,故產生之溶液須 予以處理*否則會造成環保問題;由於須對產生之溶液進 行後蹟處理’因此會增加製造成本並使製程複雜化;再而, 其步驟3)之溶解作業完成後’由於該導線架及封裝膠體形 成之結構體係完全浸入溶劑中,故須將溶有該高分子有機 物質之溶劑完全自導線架及封裝膠體之表面上去除,否 則’若有殘留者,則會形成二次污染,而對後績之製程造 成不利影響;然而’欲有效去除溶有高分子有機物質之溶 劑’則須使用習知製程所不具有之設備與程序,而導致製 造成本的增加與製程之複雜化;同時,在該高分子有機物 質為溶劑溶解後,該專利方法不能立即進行上片及銲線作 業’因其須經過去除溶有該高分子有機物質之溶剤之處理 時間’而令製造時程為之增加’且不利於生產效率。 綜觀上述專利方法及其它習用方法之缺點,可瞭解到 --I-— I I ------ ^---I I I i I I--—II---5^ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) 2 16018 經濟部智慧財產局員Η 4費合"社-" 16018 A7 ____B7____ 五、發明說明(3 ) 其癥結所在係該等方法均是在溢膠於模壓製程(Molding) 中產生後方予以去除溢膠之後處理,其所以會衍生諸多新 問題乃是可預見的’因而,如何避免模壓製程中於導線架 上產生溢膠,始為有效之根本解決之道》 [發明概述] 本發明之目的即在提供一種能防止溢膠發生於導線架 上之具溢膠防止結構之半導體封裝件及其製法,由於導線 架上於模壓製程中不會形成溢膠,故毋須後績之去除溢勝 處理’而能降低製造成本並簡化封裝製程,從而可確保封 裝件之品質。 依據本發明上揭及其它目的所提供之具溢膠防止結構 之半導體封裝件的製法,係包括:準備—具頂面與底面之 導線架’將一溢膝防止結構成型於該導線架上之預設位置 後,使該導線架頂面位於溢膠防止結構内之部分與其位於 該溢膠防止結構外之其餘部分隔離’並在該導線架頂面位 於該溢膠防止結構内之部分上形成一晶片黏置區與—位於 該晶片黏置區外側之鋅接區;接而’將該結合有溢膠防止 結構之導線架置入封裝模具[以成型出-與該導線架結 合並具有一開槽之封裝膠體,該開槽之形成方式係使其槽 壁底邊與該溢膠防止結構接合,而令該導線架之晶片黏置 區與銲接區外露於該開槽中;然後於該晶片黏置區上黏接 卡導U再以_線連接該丰導艘晶片與錄接區而 使該丰導體晶片與導線架電性連結最後將蓋片黏接 曼球裝膠濮以封蓋住玆開攢而將開攢中之半導體晶 -MM—.....................
If ! I « -------I ^ --------- (锖先閱讀背面之注意事項再填寫本頁) 466 72 0 a? ___ Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明(4)片及輝線與外界氣密隔離。 本發明之一較佳具體例中,該溢膠防止結構係由一黏 貼至該導線架之晶片黏置區與銲接區下方之底面上的貼 片’以及環設於該導線架銲接區外緣並與該貼片形成有黏 結關係之膠堤所構成者β該膠堤係凸出該導線架之頂面一 適當高度’且與位於其下方之貼片密合地黏接,令導線架 之頂面為膠堤所圈圍之部分(即晶片黏置區及銲接區)與導 線架位於膠堤及貼片外之其餘部分完整地隔離;故在模壓 製程中’封裝模具内之開槽成型塊的邊緣會壓抵至該膠堤 上’使用以形成該封裝膠體之融熔封裝樹脂不致溢流入導 線架之晶片黏置區及銲接區上’而得有效避免溢膠之形 成。 本發明之另一較佳具艘例令,該導線架頂面上所預設 之膠堤形成位置上’係以蝕刻或其它習知方式形成一凹部 以限成膠堤形成範園,並提高膠堤與導線架之結合性。 本發明之導線架得由一晶片座及多數之導腳所構成, 其組成方式係令各導腳之内端與晶片座之邊緣相隔一適當 距離而形成一缝隙;此時’該貼片即黏貼至晶片座與導腳 之下表面上,而將兩者間之縫隙下側封蓋住,該膠堤則成 型於導腳近内端之部位上,而使膝堤分別與各導腳與導腳 下於貼片密合地黏結’以由導腳之内端與膠堤間之頂面形 成該銲線區,晶片座之頂面形成該晶片黏置區。該導線架 亦得僅由多數之導腳所構成,令各導腳之内端間隔開一適 當距離而限定出一中空部,以在該半導體晶片黏接至該導 {請先閱讀背面之注意事項再填寫本頁) i^---— I丨—丨訂-----II--線 本紙張尺度適用令國國家標準(CNS)A4規格(210 X 297公爱) 4 16018 A7 A7 經濟部智慧財產局_H消費合"fj-Y·,· V' 圖 B7 五、發明說明(5 ) 線架上後,該中空部恰為半導體晶片所蓋覆,如此’該半 導體晶片與導線架間之黏接面積得大幅降低,以避免晶片 脫層(Delamination)的發生;此時,該貼片即黏貼至導線架 之底面上,其面積須大於中空部及半導體晶片之面積,以 在膠堤成型於該導線架上之預設位置後,各導腳供銲線銲 接之銲接區得圈圍於膠堤内易言之,此僅由導腳構成之 導線架,其晶片點置區與鲜接區均位於導腳向内部集中之 部位上。 以下茲以較佳具體例配合所附圖式進一步詳述本發明 之特點及功效。 [圖式簡單說明] 第1圊係本發明第一實施例之半導體封裝件之剖視 raa , 固, 第2A至2F圖係用以說明本發明第—實施例之半導體 封裝件製程之流程示意圖; 第3圖係本發明第二實施例之半導體封裝件之剖視 圖;以及 第4圖係本發明第三實施例之半導體封襞件之剖視 [發明詳細說明] JL—一實施体丨 第1圖係本發明第一實施例之半導體封裝件的剖視 圖如圖所示該丰導趙封裝{牛係包括有導線= 黏接於該導線架2 t.之本導髏晶^ .用以導電連接該丰
160 IS -------------^--------^--------- (請先閱讀背面之注意事項再填寫本頁) 4 66 7 A7 B7 五、發明說明(6) 導體晶片3及導線架2之金線4,用以部分包覆該導線架2 之封裝膠體5’封接至該封裝膠體5上之蓋片6。 該導線架2係以銅、銘、銅合金、銘合金或其他具導 電性佳之金屬材料製成,其具有一晶片座20以及多數之導 腳21,使該導腳21之内端210與晶片座20之邊緣200間 相隔一適當距雜而形成一縫隙22;同時,該晶片座20具 有一頂面201與一相對之底面202,各該導腳21亦具有一 頂面211與一相對之底面212。該晶片座20即係供半導體 晶片3黏接至其頂面201上’黏接之方式得使用如銀膠等 之膠黏劑或使用熱固性或熱塑性樹脂製成之貼片 (Adhesive Tape)為之。而該封裝膠體5於模壓製程中即一 體成型出一開槽50,以令該半導體晶片3及金線4均外露 於該開槽50中,而不會為封裝膠體5所包覆,故在該開槽 50為蓋片6所封蓋住後,該半導餿晶片及金線4仍得與外 界氣密隔離,不致有外界異物及水氣入侵之問題。 如第1圖所示,該導線架2上復在該開槽50之槽壁 5〇〇的底邊上形成有一連績之膠堤7,並在該晶片座20之 底面202與導脚21之底面212上黏貼一貼片8,使該縫隙 22的下側為該貼片8所密合地封蓋住,以由該膠堤7與貼 片8構成一溢膠防止結構,避免該導線架2與溢膠防止結 構結合後於進行模壓製程時有溢膠之發生◊該貼片8之寬 度須大於該膠堤7與晶片座20之邊緣200間之距離,亦即 黏貼作業完成後,該貼片8之外側邊80須向外超出該膠堤 7,以避免該膠堤7之成型作業時,構成該膠堤7之樹脂不 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 6 16018 ί請先閱讀背面之;i$項再填寫本頁)
---11 I 丨訂------- ) I 經濟部智慧財產局員工消費合作杜印製 Λ7 Λ7 經濟部智慧財產局員工消費合咋拉印" B7 五、發明說明(7 ) 致自貼>! 8之外側邊8 0向下溢流而污染作業設備,同時, 該貼片8之内側邊81則須向内延展一適當距離以超出該晶 片座20之邊緣200*而完整地封合住該縫隙22。該貼片§ 得以聚亞醯胺(Poly imide)或金屬片等材料製成:當該貼片 8為金屬材料製成時,適用之金屬材料為鋼、鋁銅合金 或鋁合金等。此外,該膠堤7之形成得以習用之點膠(G1〇b Top)或網版印刷等方式為之,其超出該導腳21之頂面2ιι 的高度以足以防止形成該封裝膠體5之封裝樹脂溢流至導 腳21頂面21]上於膠堤7與内端210間之部位為限,無特 殊限制。製成該膠堤7之樹脂材料宜為具彈性之s夕勝 (silicone),環氧樹脂(Epoxy)或聚亞醯胺。 再參照第2A至2G圖,本發明第一實施例之半導艎封 裝件1之製法’係依下列步驟為之β 首先,如第2Α圖所示,準備一由導電性之金屬材料 製成之導線架2’使之形成—晶片座2〇以及多數裝設於該 晶片座20四周之導腳2卜且在導腳21之内端21〇與晶片 座20之邊緣200間相隔出一縫隙22。 然後,如第2Β圖所示,在該晶片座2〇之底面2〇2及 導腳2丨之底面2 i 2上黏貼—貼只R .坌舡扣 ^ 貼片8,其黏貼之位置係使該 站片8得完全地封住該縫隙2 2之下側。 再而,如第2C圖所示f w + 」 ® π不以點膠或網版印刷方式於該 導線架2上之預設位置形成…将該晶片座2()及導腳2丨近 内端2丨0之部分圈圍在内之穆堤由於編“外惻 係位於該躍堤7成型位置外故移堤:,成型膝吟會 一…二^.’ ----伙一一〜… 、度適粑卞國®家橒茗…規格ΐ_2】η % H 」-1^ n n I · Et I n .^1 MM 丨 n I il It )— ! u( —i i tt IJr „1 .·/ ft, ;!. (請先閱讀背面之注意事項再填窝本頁)
\60iH 綬濟部哲慧財雇扃負>消費含作杜印製 : .6 6 7 2 0 · A7 — :'V乾先 B7 五、發明説明(8 ) 黏附至各導腳21上,並會由兩相鄰導腳21間之間隙流至 該誌片8上,以在膠堤7固化成型後,該膠堤7亦會與貼 片8彰結,而使該導脚21之頂面2n位於該穆堤7與其内 端210間之部分以及晶片座20之頂面2〇1與導線架2位於 該穆堤7與點片8外之部分隔離開。為使膠堤7、站片8 與導線架2間之黏設關係明確起見,第2C圖並以正視圖 方式表現。 謬堤7形成後,即舆該貼片8構成一溢膠防止結構, 該结合有溢膠防止機構之導線架2之隨即可置入一封裝模 具中以進行模壓製程。如第2D圖所示,該封裝模具係由 一上模90與一得與上模90合模之下模91所構成「該上模 90與下模91分別eg設有椟六900及91〇,俾供融熔封裝樹 脂注入以形成該封裝醪體5 :該上模90之模六900中並一 體設有一開槽形成塊901,該開槽形成塊9〇i在上模卯與 下模91合模後,其頂緣會壓抵至該膠堤7上,由於該膠堤 7具有彈性’故開槽形成堍90〗與之壓接後,兩者間不會 留有融熔封裝樹脂得流入之間隙,且導線架2之底部黏接 有該貼片8 ’遂不會有溢膠發生於晶片座20之頂面2〇1及 導腳2】位於膠堤7内之頂面上的情形,故在模壓作業 完成後,該-晶片座20之頂面201及導腳2ί位於膠堤7内 之i頁面211均無封裝樹腊之污染’而可直接進行後續製程 見母需任何清洗處理,所以,相較於習知製法,本發明之 製造成本得以降低且製程得以簡化並縮短時程。 如第2£圖所示’封裝製程結束並脫模後,該封裝 (請先閲讀背面之注意事項再塡寫本頁各摘} -訂----- .線 本紙張尺·度適用中囤國家標準(CNS)A4規格(210x297公釐) Ϊ6018 Λ7 Λ7 經 濟 智 慧 財 產 Μι 費 合 B7 五'發明說明(9) 體5即會形成一開槽5〇,使該晶片座2〇之頂面2〇1與導 聊21位於其内端210與膠堤7間之頂面2]1外露於該開槽 50中。 然後’將-半導體晶片3經由該開槽5〇黏接至該晶片 座20之頂面2〇1上,隨而,進行銲線作業以將金線4銲接 於半導體晶片3及導腳21位於膠堤7内之部位上而導電 連接該半導體晶片3及導線架2,如第2p圖所示。 最後’參照第I.圖,將一習用之蓋片6黏接至該封裝 勝體5上’以封蓋住該封裝膠體5之開槽5〇,而使開槽 中之半導體晶片3及金線4與外界氣密隔離。 上述之前三個步驟得由組件供應商先製成,再運交封 裝業者直接進行模壓製程後之作業,因而’本發明之半導 體封裝件製法不惟可解決溢膠發生的問題’並可直接沿用 既有之封裝設備與製程,故能有效降低製造成本。 如第3圖所示者為本發明第二實施例之半導體封裝件 1 '該半導體封裝件丨,之結構大致同於前揭之第一實施 例’其不同處在於其導線架2,係由多數之導腳2],構成。 該導線架2,之導腳2Γ的内端210,係以朝内部集令並間隔 開之方式限定出—由導腳2丨,之内端2i〇,形成之中空部 23 '以令半導體晶片3,黏設至該導線架2,上時,該尹空 # “ J恰位於半導體晶片3 ’下方並為之完全蓋覆而令該 半導體晶片3之底面3丨―僅部分與導腳2 Γ之頂面2 Π相黏 接故$減’少晶片脫層發生機會..由於該丰導體晶月3..係 直接秦1著至該導腳2 1上故須使用非導電性之膠黏劑或
I601S --------^----------^ (請先閱璜背面之注意事項再填寫本頁) 466 466 經濟邨智慧財產局員工消費合作杜印製 A7 B7 五、發明說明(10) 貼片黏接兩者,同時,各導腳21,之頂面211,上亦分別形 成有一晶片黏置區213’及位於該晶片黏置區213,外側之鮮 接區214’。 該溢膠防止結構之形成係在導腳21’之底面212,上黏 貼一貼片8’,使該貼片8,之宽度大於兩相對之導腳21,上 之銲接區214’外緣間的距離,以在該膠堤7,形成於該導腳 21’之銲接區214,的外緣上時,該膠堤7,得與該導腳21, 及位於導腳2Γ下方之貼片8’分別黏接,且在膠堤7,成形 時,形成膠堤7’之樹脂不致自貼片8’之外側邊80,向外溢 流:同時,該貼片8’黏貼至預設位置後,得完全將該中空 部23’及兩相鄰導腳2Γ位於晶片黏置區213,及銲接區214, 間之間隙封蓋住,而使晶片黏置區213’及銲接區214,上於 模壓製程申不會發生溢膠的問題。 如第4圈所示者為本發明第三實施例之半導體封裝件 的剖示圖》該第三實施例之半導體封裝件1”之結構大致同 於前揭之第一實施例’其不同處在於該導線架2”之導腳 2 1 ”供膠堤7”成型之部位上係以習知之蝕刻方式蝕刻出一 凹部215”;該凹部215”之形成在使該膠堤7”之成型範圍 得為該凹部215”所限制,而不致過度外擴,同時,亦可強 化該膠堤V’與導腳21”間之黏結性。 以上所述者’僅為本發明之具體實施例而已,其它任 何未背離本發明之精神與技術下所作之等效改變或修飾, 均應仍包含在下述專利範圍之内。
[元件符號I I--- 1 I I I I ! i •丨 I I 丨丨 i 丨訂· 1 丨 ----I r r (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 10 16018 A7 B7 五、發明說明(U ) 1M ” 半導體封裝件 20 晶片座 22 縫隙 200 邊緣 202, 212,212’ 底面 213, 晶片黏置區 215, ’凹部 3Γ 底面 5 封裝膠體 6 蓋片 8,8, 貼片 81 内侧邊 91 下模 901 形成塊 2,2’,2” 導線架 21,2Γ,21” 導腳 2 3’ 中空部 201,201’,211,21 1’ 頂面 210 内端 214’ 銲接區 3,3’ 半導體晶片 4 金線 50 開槽 7, 7%7” 膠堤 80, 80’ 外側邊 90 上模 900,910 模穴 ---------------------訂--------I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合件杜印.名
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Claims (1)
- 經濟郎中央標準局員工福利委員會印製 拍件、一 4 66 ----------- -H3_ 第89109804號專利申請案 申請專利範圍修正本 (90年8月31曰) 1- 一種具溢膠防止結構之丰導體封裝件,係包括: 一導線架,其具有頂面及相對之底面,並在預設 位置上結合有一溢膠防止結構,使該導線架頂面位於 該溢膠防止結構内之部分與該導線架位於該溢膠防止 結構外之其餘部分隔離,以在該導線架之頂面位於該 溢膠防止結構内之部分上形成一晶月黏置區與一位於 該晶片黏置區外側之銲接區; 一黏設於該導線架之晶片黏置區上的半導體晶 片; 多數導電連接元件’係銲接於該半導體晶片與該 導線架之銲接區上,以導電連接該半導體晶片舆導線 架’· —具開槽以部分包覆該導線架之封裝膠體,使該 半導體晶片與導電連接元件均外露於該開槽中;以及 一蓋接至該封裝膠體上之蓋件,以封蓋住該開槽 而使該開槽中之封裝膠體及導電連接元件與外界氣密 地隔離。 2. 如申璋專利範圍第〗項之半導體封裝件,其中,該溢 躁防止機構係由一成型於該導線架頂面上之膠堤以及 一翁貼至該導線架底面上之貼片所構成,且該醪堤係 同時舆該導線架與貼片相黏結。 3. 如申請專利範圍第2項之半導體封裝件,其中,該膠 本纸張尺度適用中§ S家標芈(C Ns〕A 4七格(2丨〇 χ Μ?公度)-- 1 16018 堤係成型於該導線架之銲接區外緣上。 4. 如申請專利範圍第2項之车连 禾,之平導體封裝件,其令,該膠 堤係凸出於導線架之頂面上。 5. 如申請專利蘇圍第2項之半導體封裝件,其中,該移 堤係由該封裝膠體之開槽之槽壁相接。 6-如申請專利範圍第2項之半導體封裝件,其中,該貼 片係黏接至該導線架之底面位於該晶片黏置區與銲接 區下方之位置上β 7.如申請專利範圍第2項之半導體封裝件,其中,該貼 片之外側邊係向外超出該銲接區之外緣一適當距離。 8·如申請專利範圍第丨項之半導體封裝件,其中,該導 線架係由一晶片座與多數之導腳所構成者。 9.如申請專利範圍第8項之半導體封裝件,其中,該晶 片座之倒邊與各導腳之内端間係相隔開一距離而形成 一缝隙。 經濟耜中央標準局員工福利委員會印製 10-如申請專利範圍第2或9項之半導體封裝件,其中, 該貼片貼黏至該導線架之底面上後,係分別與該晶片 座與導腳黏接而將該缝隙封合D Π.如申請專利範圍第2或9項之半導體封裝件,其中, 該膠堤係形成於該導脚上之預設位置,而分別與該導 腳與貼片黏接。 12.如申請專利範園第1項之半導體封裝件,其中,該導 線架係由多數導脚所構成。 】3.如申請專利範圍第12項之半導體封裝件,其中,各該 導腳之内端係向内集中並間隔開而限定出一中空部〇 本紙張尺度適用令國國家標準(CNS )A4規格(210 X 297公赞) 2 16018 4 6 6 ί 7 ------Η3 經.濟部中央標準局員工福利委員會印製 14. 如申請專利範圍第12項之半導體封裝件,其中,各該 導脚係由其内端向外依序形成該晶片黏置區及該銲接 區。 15. 如申請專利範圍第2或13項之半導體封裝件,其中, 該貼片黏貼至該導線架之底面上後,係將該中空部封 合住。 】6.如申請專利範圍第2項之半導體封裝件,其中,該導 線架頂面上供膠堤成型之部位上復形成有一凹部。 如申請專利範圍第J6項之半導體封裝件,其中,該凹 部係形成於各該導腳上。 18.如申請專利範圍第1項之半導體封裝件,其中該導 電連接元件係金線。 】9.如申請專利範圍第1項之半導體封裝件,其中,該移 堤之材料係選自由矽膠、環氧樹脂及聚亞磕胺所组成 之组群之一者。 20·如申請專利範圍第][項之半導體封裝件,其中,該貽 片係由聚亞醢胺樹脂製成者》 2】‘如申請專利範圍第1項之半導體封裝件,其中,該貼 片係金屬片。 22.—種具溢膠防止結構之半導體封裝件之製法,係包括下列#驟: 準備一結合有溢膠防止結構之導線架,使該導線 架之頂面位於該溢移防止結構内之部位與該導線竿位 於溢膠防止結構外之其餘部位隔離開,並於該導線架 之頂面位在該溢膠防止結構内之部位上形成有一晶片 本紙張尺度適用中國國家為準(CNS )Α4規格(210Χ 297公努) 3 16018 4 6 6 -----------H3 黏置區及一位在該晶黏置區外側之辑接區* 將該结合有溢膠防止結構之導線架置入封裝模具 中,進行模壓製程以形成一具有開槽而部分包覆該導 線架之封裝躁體’令該導線架上之晶片黏置區與銲接 區外露於該開攢中; 黏設一半導體晶片至該導線架之晶片黏置區上; 導電連接該半導體晶片與導線架之銲接區;以及 蓋接一蓋片至該封裝膠想上,以封蓋住該封裝膠 餿之開槽。 如申請專利範圍第22項之製法,其中,該溢移防止機 構係由一成型於該導線架頂面上之膠堤以及一黏貼至 該導線架底面上之貼片所構成,且該膠堤係同時舆該 導線架與貼月相黏結。 24·如申請專利範園第23項之製法,其中,該膠堤係成型 於該導線架之銲接區外緣上。 25, 如申請專利筑園第23項之製法,其中,該膠堤係&出 於導線架之頂面上。 經濟部中央標準局WX福利委®會印製 26. 如申請專利範圍第23項之製法,其中,該膠堤係由該 封裝膠體之開槽之槽壁相接。 27‘如申請專利範圍第23項之製法,纟中,該貼片係黏接 至該等線架之底面位於該晶片黏置區與銲接區下方之 位置上。 2S-如申請專利範圍第23項之製法,丨中,該能片之外側 邊係向外超出該銲接區之外緣一適當距離。 29·如申請專利㈣第22項之製法’纟中,該導線架係由 本纸張纽適用㈣國雜準(C N S ) A 4規格U10 X -------- 4 16018 4 66 H3 一晶片座與多數之導腳所構成者。 30.如申請專利範圍第29項之製法,其中,該晶片座之側: 邊與各導腳之内端間係相隔開一距離而形成一缝隙。 31如申請專利範園第23或29項之製法,其中,該貼片 貼黏至該導線架之底面上後,係分別與該晶片座與導 腳黏接而將該缝陳封合。 32. 如申請專利範圍第23或29項之製法,其中,該膠堤 係形成於該導腳上之預設位置,而分別與該導腳與貼 片黏接® 33. 如申請專利範圍第22項之製法,其中’該導線架係由 多數導腳所構成。 34. 如申請專利範圍第33項之製法’其中,各該導腳之内 端係向内集中並間隔開而限定出一中空部。 35·如申請專利範圍第33項之製法,其中,各該導腳係由 其内端向外依序形成該晶片黏置區及該銲接區。 36. 如申請專利範圍第23或34項之製法,其中,該貼月 黏貼至該導線架之底面上後,係將該中空部封合住。 經濟部中央標準局員工福利委員會印製 37. 如申請專利範圍第23項之製法,其中,該導線架頂面 上供膠堤成型之部位上復形成有一凹部。 如申請專利範圍第37項之製法’其中,該凹部係形成 於各碑導腳上。 39.如申請專利範圍第22項之製法,其中,該導電連接元 件係金線。 40·如申請專利範圍第22項之製法,其中,該膠堤之材料 係1 “料、環氧樹脂及聚亞醢胺所組成之组群之 未紙張元变適用巾國國準(CNS )Α4規格(2i〇x撕公愛) —- 5 16018 466720 _H3_ 一者。 41. 如申請專利範圍第22項之製法,其中,該貼片係由聚* 亞贐胺樹脂製成者。 42. 如申請專利範圍第22項之製法,其中,該貼片係金屬 片。 經濟部中央搮準局員Η福利委員會印製 本紙張尺度適用中國國家標準(CNS)A4規格^(210/297公免 6 16018
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111668197A (zh) * | 2019-03-06 | 2020-09-15 | 三菱电机株式会社 | 半导体装置及其制造方法 |
CN113396056A (zh) * | 2019-03-29 | 2021-09-14 | 太阳油墨制造株式会社 | 中空器件用干膜、固化物和电子部件 |
Families Citing this family (63)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
EP1246235A1 (en) * | 2001-03-26 | 2002-10-02 | European Semiconductor Assembly (Eurasem) B.V. | Method for encapsulating a chip having a sensitive surface |
KR100369393B1 (ko) | 2001-03-27 | 2003-02-05 | 앰코 테크놀로지 코리아 주식회사 | 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법 |
EP1357605A1 (en) * | 2002-04-22 | 2003-10-29 | Scientek Corporation | Image sensor semiconductor package with castellation |
US7164192B2 (en) * | 2003-02-10 | 2007-01-16 | Skyworks Solutions, Inc. | Semiconductor die package with reduced inductance and reduced die attach flow out |
JP4519424B2 (ja) * | 2003-06-26 | 2010-08-04 | ルネサスエレクトロニクス株式会社 | 樹脂モールド型半導体装置 |
US7245007B1 (en) * | 2003-09-18 | 2007-07-17 | Amkor Technology, Inc. | Exposed lead interposer leadframe package |
WO2005045930A1 (en) * | 2003-11-04 | 2005-05-19 | Infineon Technologies Ag | Leadframe with insulating ring |
TWI239655B (en) * | 2004-02-23 | 2005-09-11 | Siliconware Precision Industries Co Ltd | Photosensitive semiconductor package with support member and method for fabricating the same |
US7547978B2 (en) * | 2004-06-14 | 2009-06-16 | Micron Technology, Inc. | Underfill and encapsulation of semiconductor assemblies with materials having differing properties |
US20060170079A1 (en) * | 2005-02-02 | 2006-08-03 | Brennan John M | Integrated circuit device having encapsulant dam with chamfered edge |
TWI242820B (en) * | 2005-03-29 | 2005-11-01 | Siliconware Precision Industries Co Ltd | Sensor semiconductor device and method for fabricating the same |
US7507603B1 (en) | 2005-12-02 | 2009-03-24 | Amkor Technology, Inc. | Etch singulated semiconductor package |
EP1983567B1 (en) * | 2006-02-03 | 2018-08-15 | Mtex Matsumura Corporation | Hollow package made of resin, and manufacturing method therefor |
US7968998B1 (en) | 2006-06-21 | 2011-06-28 | Amkor Technology, Inc. | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
US7977774B2 (en) | 2007-07-10 | 2011-07-12 | Amkor Technology, Inc. | Fusion quad flat semiconductor package |
US7687899B1 (en) | 2007-08-07 | 2010-03-30 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US7923298B2 (en) | 2007-09-07 | 2011-04-12 | Micron Technology, Inc. | Imager die package and methods of packaging an imager die on a temporary carrier |
US7777351B1 (en) | 2007-10-01 | 2010-08-17 | Amkor Technology, Inc. | Thin stacked interposer package |
US8089159B1 (en) | 2007-10-03 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor package with increased I/O density and method of making the same |
CN101414565B (zh) * | 2007-10-16 | 2012-07-04 | 飞思卡尔半导体(中国)有限公司 | 形成预成型引线框的方法 |
US7847386B1 (en) | 2007-11-05 | 2010-12-07 | Amkor Technology, Inc. | Reduced size stacked semiconductor package and method of making the same |
US7956453B1 (en) | 2008-01-16 | 2011-06-07 | Amkor Technology, Inc. | Semiconductor package with patterning layer and method of making same |
US7723852B1 (en) | 2008-01-21 | 2010-05-25 | Amkor Technology, Inc. | Stacked semiconductor package and method of making same |
US8067821B1 (en) | 2008-04-10 | 2011-11-29 | Amkor Technology, Inc. | Flat semiconductor package with half package molding |
US7768135B1 (en) | 2008-04-17 | 2010-08-03 | Amkor Technology, Inc. | Semiconductor package with fast power-up cycle and method of making same |
US7808084B1 (en) | 2008-05-06 | 2010-10-05 | Amkor Technology, Inc. | Semiconductor package with half-etched locking features |
US8125064B1 (en) | 2008-07-28 | 2012-02-28 | Amkor Technology, Inc. | Increased I/O semiconductor package and method of making same |
US8184453B1 (en) | 2008-07-31 | 2012-05-22 | Amkor Technology, Inc. | Increased capacity semiconductor package |
US7847392B1 (en) | 2008-09-30 | 2010-12-07 | Amkor Technology, Inc. | Semiconductor device including leadframe with increased I/O |
US7989933B1 (en) | 2008-10-06 | 2011-08-02 | Amkor Technology, Inc. | Increased I/O leadframe and semiconductor device including same |
US8008758B1 (en) | 2008-10-27 | 2011-08-30 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe |
US8089145B1 (en) | 2008-11-17 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor device including increased capacity leadframe |
US8072050B1 (en) | 2008-11-18 | 2011-12-06 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including passive device |
US7875963B1 (en) | 2008-11-21 | 2011-01-25 | Amkor Technology, Inc. | Semiconductor device including leadframe having power bars and increased I/O |
US7982298B1 (en) | 2008-12-03 | 2011-07-19 | Amkor Technology, Inc. | Package in package semiconductor device |
US8487420B1 (en) | 2008-12-08 | 2013-07-16 | Amkor Technology, Inc. | Package in package semiconductor device with film over wire |
US20170117214A1 (en) | 2009-01-05 | 2017-04-27 | Amkor Technology, Inc. | Semiconductor device with through-mold via |
US8680656B1 (en) | 2009-01-05 | 2014-03-25 | Amkor Technology, Inc. | Leadframe structure for concentrated photovoltaic receiver package |
US8058715B1 (en) | 2009-01-09 | 2011-11-15 | Amkor Technology, Inc. | Package in package device for RF transceiver module |
US8026589B1 (en) | 2009-02-23 | 2011-09-27 | Amkor Technology, Inc. | Reduced profile stackable semiconductor package |
US7960818B1 (en) | 2009-03-04 | 2011-06-14 | Amkor Technology, Inc. | Conformal shield on punch QFN semiconductor package |
US8575742B1 (en) | 2009-04-06 | 2013-11-05 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including power bars |
US8664753B2 (en) * | 2009-11-25 | 2014-03-04 | Infineon Technologies Ag | Semiconductor device with protruding component portion and method of packaging |
DE102010023815A1 (de) * | 2010-06-15 | 2011-12-15 | Osram Opto Semiconductors Gmbh | Oberflächenmontierbares optoelektronisches Bauelement und Verfahren zur Herstellung eines oberflächenmontierbaren optoelektronischen Bauelements |
US8674485B1 (en) | 2010-12-08 | 2014-03-18 | Amkor Technology, Inc. | Semiconductor device including leadframe with downsets |
US8648450B1 (en) | 2011-01-27 | 2014-02-11 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands |
TWI557183B (zh) | 2015-12-16 | 2016-11-11 | 財團法人工業技術研究院 | 矽氧烷組成物、以及包含其之光電裝置 |
US9704725B1 (en) | 2012-03-06 | 2017-07-11 | Amkor Technology, Inc. | Semiconductor device with leadframe configured to facilitate reduced burr formation |
CN107589842B (zh) * | 2012-11-27 | 2020-06-05 | 原相科技股份有限公司 | 复合式光学装置 |
US20140238726A1 (en) * | 2013-02-28 | 2014-08-28 | Cooper Technologies Company | External moisture barrier package for circuit board electrical component |
KR101486790B1 (ko) | 2013-05-02 | 2015-01-28 | 앰코 테크놀로지 코리아 주식회사 | 강성보강부를 갖는 마이크로 리드프레임 |
US9478473B2 (en) * | 2013-05-21 | 2016-10-25 | Globalfoundries Inc. | Fabricating a microelectronics lid using sol-gel processing |
KR101563911B1 (ko) | 2013-10-24 | 2015-10-28 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 |
US9673122B2 (en) | 2014-05-02 | 2017-06-06 | Amkor Technology, Inc. | Micro lead frame structure having reinforcing portions and method |
JP6387824B2 (ja) * | 2014-12-25 | 2018-09-12 | 日亜化学工業株式会社 | パッケージ、発光装置及びそれらの製造方法 |
US11211305B2 (en) | 2016-04-01 | 2021-12-28 | Texas Instruments Incorporated | Apparatus and method to support thermal management of semiconductor-based components |
US10861796B2 (en) * | 2016-05-10 | 2020-12-08 | Texas Instruments Incorporated | Floating die package |
US10074639B2 (en) | 2016-12-30 | 2018-09-11 | Texas Instruments Incorporated | Isolator integrated circuits with package structure cavity and fabrication methods |
US10830656B2 (en) | 2018-06-01 | 2020-11-10 | Sensata Technologies, Inc. | Overmolded lead frame assembly for pressure sensing applications |
TWI721837B (zh) * | 2020-03-26 | 2021-03-11 | 勝麗國際股份有限公司 | 感測器封裝結構 |
US11881494B2 (en) * | 2020-09-20 | 2024-01-23 | UTAC Headquarters Pte. Ltd. | Semiconductor package with dams |
CN116435201B (zh) * | 2023-06-12 | 2023-09-12 | 四川遂宁市利普芯微电子有限公司 | 一种塑封封装方法以及器件封装结构 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5648155A (en) * | 1979-09-27 | 1981-05-01 | Hitachi Chem Co Ltd | Package forming method for semiconductor |
JPS62229949A (ja) * | 1986-03-31 | 1987-10-08 | Oki Electric Ind Co Ltd | 樹脂封止型半導体装置の製造方法 |
US5106784A (en) * | 1987-04-16 | 1992-04-21 | Texas Instruments Incorporated | Method of making a post molded cavity package with internal dam bar for integrated circuit |
MY104152A (en) * | 1988-08-12 | 1994-02-28 | Mitsui Chemicals Inc | Processes for producing semiconductor devices. |
US5070039A (en) * | 1989-04-13 | 1991-12-03 | Texas Instruments Incorporated | Method of making an integrated circuit using a pre-served dam bar to reduce mold flash and to facilitate flash removal |
US5177591A (en) * | 1991-08-20 | 1993-01-05 | Emanuel Norbert T | Multi-layered fluid soluble alignment bars |
US5859471A (en) * | 1992-11-17 | 1999-01-12 | Shinko Electric Industries Co., Ltd. | Semiconductor device having tab tape lead frame with reinforced outer leads |
JPH0738035A (ja) * | 1993-07-22 | 1995-02-07 | Toppan Printing Co Ltd | 樹脂封止電子回路装置の製造方法 |
US5441684A (en) * | 1993-09-24 | 1995-08-15 | Vlsi Technology, Inc. | Method of forming molded plastic packages with integrated heat sinks |
JP2663897B2 (ja) * | 1995-01-26 | 1997-10-15 | 日本電気株式会社 | リードフレームおよびその製造方法 |
US6058602A (en) * | 1998-09-21 | 2000-05-09 | Integrated Packaging Assembly Corporation | Method for encapsulating IC packages with diamond substrate |
JP2806328B2 (ja) * | 1995-10-31 | 1998-09-30 | 日本電気株式会社 | 樹脂封止型半導体装置およびその製造方法 |
JPH09153586A (ja) * | 1995-12-01 | 1997-06-10 | Texas Instr Japan Ltd | 半導体装置、その製造方法、及びリードフレーム |
TW380288B (en) * | 1996-06-25 | 2000-01-21 | Seiko Epson Corp | Conductive pattern transfer printing method on film carrier and the mask and film carrier using the same |
JP2825084B2 (ja) * | 1996-08-29 | 1998-11-18 | 日本電気株式会社 | 半導体装置およびその製造方法 |
US5909058A (en) * | 1996-09-25 | 1999-06-01 | Kabushiki Kaisha Toshiba | Semiconductor package and semiconductor mounting part |
US5990545A (en) * | 1996-12-02 | 1999-11-23 | 3M Innovative Properties Company | Chip scale ball grid array for integrated circuit package |
JP2953424B2 (ja) * | 1997-03-31 | 1999-09-27 | 日本電気株式会社 | フェイスダウンボンディング用リードフレーム |
-
2000
- 2000-05-22 TW TW089109804A patent/TW466720B/zh not_active IP Right Cessation
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2001
- 2001-05-22 US US09/862,347 patent/US6696752B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN111668197A (zh) * | 2019-03-06 | 2020-09-15 | 三菱电机株式会社 | 半导体装置及其制造方法 |
CN111668197B (zh) * | 2019-03-06 | 2023-09-19 | 三菱电机株式会社 | 半导体装置及其制造方法 |
CN113396056A (zh) * | 2019-03-29 | 2021-09-14 | 太阳油墨制造株式会社 | 中空器件用干膜、固化物和电子部件 |
CN113396056B (zh) * | 2019-03-29 | 2024-05-14 | 太阳控股株式会社 | 中空器件用干膜、固化物和电子部件 |
Also Published As
Publication number | Publication date |
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US6696752B2 (en) | 2004-02-24 |
US20010042915A1 (en) | 2001-11-22 |
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