TW463347B - A method of assembling a semiconductor device package - Google Patents

A method of assembling a semiconductor device package Download PDF

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Publication number
TW463347B
TW463347B TW089110605A TW89110605A TW463347B TW 463347 B TW463347 B TW 463347B TW 089110605 A TW089110605 A TW 089110605A TW 89110605 A TW89110605 A TW 89110605A TW 463347 B TW463347 B TW 463347B
Authority
TW
Taiwan
Prior art keywords
semiconductor device
lead frame
coating
device package
electrical connection
Prior art date
Application number
TW089110605A
Other languages
English (en)
Inventor
Charles Wee-Ming Lee
Helmut Strack
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of TW463347B publication Critical patent/TW463347B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/4805—Shape
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

463347 Λ7 B7 ^©33^7 五、發明說明（） 發J9領域_ (請先閱讀背面之注意事項再填寫本頁) 本發明是關於一種组合半導體裝置封裝之方法特別 地有鼸一種避免或儘量減少封裝内之介面發生脱層之方 法。 琎明_背骨 塑腠表面安裝型半導體裝置封裝易於在銲錫回流（s〇lder reflow)期間破裂（crack),這個現象通稱為"爆米花破 裂"（Popcorn cracking)·燔米花破裂的發生楚因為用 來封裝半導醴裝置的環氧樹脂模塑混合物容易潮溼 並 且很快的從周圍琛境吸收水分。在銲錫回流期間，由於 吸收水氣的快速蒸發以及封裝中不同材料膨脹傺數的差 異而産生高熱應力· 一0該窿力到逹一臨界值，脱層便 發生，通常是在最弱的界面，跟著脱層洞穴内部的蒸氣 壓形成一圓頂狀的膨脹，最後造成封裝材料的崩裂。 燔米花破裂是一個潛在的可靠性間題，因為脫層的匾 域與/或破裂會造成腐蝕失敗，改變功率元件的熱表現， 影堪應力的分佈與濃度。 經濟部智慧財產局員工消費合作社印製 已知模塑混合物/銲墊<die-pad)介面容易受到脱層以 及大多數爆米花失敗模式來源的影氇，這痼情況随著較 大較薄封裝的出現而變得更為明顯〇再者，溼氣會影響 聚合物/金屬的界面耐久性，減少模塑混合物在回流溫 度下的結構強度。此外，在封裝過程中以銅為基礎的導 線架材料的氣化會導致模塑混合物與銲墊之間的接著力 變差，使接著力變差的主要原因在於導線架表面形成網 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 463347 B7_ 五、發明說明（） 氧化物，研究報告指出模塑混合物與銅導線架之間的接 著強度隨箸氣化層厚度增加而減少。 各種加強模塑混合物/銲墊接著力的技術提議作為解 決爆米花破裂的方法，然而，大部份的解決方法無法完 全解決爆米花破裂的問題，並且對於大多數的産品不符 經濟效益且/或不可行。 例如，有機黏著催化劑例如矽烷網合媒介廣泛地使用 在晶粒黏貼黏著劑以及模塑混合物以改善不同界面的黏 著。然而，這些材料對於溫度敏感並且容易因溫度提高 而變質（典型地髙於攝氏2 0 0度），例如，在引線接合期 間〇 使用無機鲜-絡（Zn-Cr)導線架塗層（商業上常用Olin Metal Research Laboratories提供之"Olin A2”）相 信能夠有效去除爆米花破裂的問題，然而，鋅-銘塗層 僳藉由電鍍製程電解地沉積在導線架上，而且，由於鋅 -鉻塗層對於溫度穩定，它會妨礙或者干擾接下來的固 態接合，熔化或者銲錫製程例如引線接合等等。因此， 必須在塗佈過程中遮住這些接合/銲錫區域，或者随後 去除這些區域的塗層^因此，導線架表面以及完成封裝 的半導體裝置没有鋅-銘塗層，仍然容易發生爆米花破 裂。 晶Η緩衝塗層例如聚亞酷胺（PI),廣泛地用來減少模 塑混合物與晶片界面之間的熱-機械應力與脫層。然而， 聚亞醯胺具有容易吸收水分的缺點，因此更容易肋長發 -4 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------- 1 I — .1 I - I------訂------ ！線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4633 4 7 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（） 生爆米花破裂。 發明概诚 根據本發明第一個觀點，一種紐合半導體裝置封裝之 方法，包括： 黏貼一半導體裝置至一導線架上的晶粒銲墊（die-pad) 區域； 在半導體裝置上的電氣接觸區域與導線架的電氣接觸 區域形成電性連接形成一裝置，導線架組合； 沉積一黏箸加強塗層於該裝置/導線架組合之曝露之 表面；以及 以一電絶緣材料包覆該塗佈之裝置/導線架組合β 根據本發明第二個觀點，一種^導體裝置封裝包括一導 線架；一半導體裝置黏貼在導線架之第一部份；由半導 體裝置上的電氣接觸匾域至導線架上第二部份的電氣接 觸區域之電性連接；一黏箸加強塗層位於該導線架，該 電性連接以及該半導體裝置之表面；以及一電絶緣材料 包覆該半導體裝置，該電性連接，以及該導線架之第一 與第二部份β 本發明之一優點在於藉由在半導體裝置與導線架形成 電性連接之後，沉積一黏著加強塗層於導線半導體 裝置，該黏箸加強塗層同時也沉積在半導體裝置與導線 架之間的電性連接上。另一個優點在於如果黏著加強塗 層像以電鍍製程電解地沉積，該電性連接提供一導電路 徑從導線架至半導體裝置，使黏著加強塗層的電解沉積 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----I -----1 I -------^--------* (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 6334 7 A7 B7 ί …I ΙΓ·— 五、發明說明（） 形成於半導體裝置的導電表面。 較佳者，黏著加強塗靥僳一金屬塗層並且典型地籍由 電鑛製程電解地沉積。 較佳者，該金屬塗層像一無機鋅-鉻塗層，例如Olin A2 c 典型地，該半導體裝置係藉由一環氣樹脂晶粒-黏阽 黏著劑或者以銲錫晶粒-黏貼黏貼在導線架上。 較佳者，該半導體裝置封裝僳與表面安裝型半導體裝 置封裝。 _式簡盟說明 根據本發明一種組合半導體裝置封裝之方法之一較佳 實施例將伴隨圖式來描述，其中： 第1圖偽根據習知技藝中一具有黏著加強塗層之表面 安裝型半導體裝置封裝的剖視圖； 第2圖偽一表面安裝型半導體裝置之剖視圖，其中一 半導體裝置以一環氧樹脂晶粒-黏阽黏著剤以及混合根據 本發明之黏箸加強塗層黏貼於一導線架； 第3圃俗一表面安装型半導體裝置之剖視圖，其中一 半導體裝置以一銲錫以及混合根據本發明之黏箸加強塗 層黏阽於一導線架；以及 第4圖顯示一表面安裝型半導體裝置之剖視圖，其中 包括一功率半導體裝置以及延伸一散熱塊。 詳細說朋 第1圖傜一表面安裝型半導體裝置封裝1之剖視圖。 -6 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 297公釐） ----------1 I I--· I I t--— — 訂----I ----*3^*. (請先閱讀背面之注意事項再填寫本頁) 463347 經濟部智慧財產局員工消費合作杜印製 A7 B7 五、發明說明（） 其中導線架2包括一晶粒-銲墊區域2 a以及引腳2b被塗 佈鋅-鉻塗層3(例如Olin A2),該鋅-銘塗層3係在半導 體裝置4黏貼至晶粒-銲墊區域2 a之前藉由電鍍製程電 解地沉積在導線架上。 在塗層3沉積期間，必須遮住引腳2b上銲接引線5的 銲接區域7,或者以兩階段電鍍與剝除製程進行鋅-鉻塗 層3的沉積。一般而言遮住或者去除晶粒-銲墊區域的 一部份也是必須的，以允許半導體裝置4與晶粒-銲墊 區域2 a之間建立電性接地接觸。 在移除導線架上的遮單，或者塗層已經從柑關區域被 去除之後，半導體裝置4藉由一環氣樹脂晶粒-黏_占黏 箸劑6黏貼至晶粒-銲墊部份2ae黏貼半導體裝置4的導 線架2接下來經過引線接合製程使引線5接合於引脚2b 的銲接匾域7與半導體裝置4之電性接觸區域之間。 一般而言，導線架2只是許多導線架2形成一導線架 2之帶狀或矩陣的其中之一 β每一帶狀或矩陣中的導線 架2包括一晶粒-銲墊區域2a以及各自的引腳2b,導線 架2上的毎一晶粒-銲墊區域2 a會有一半導體裝置藉由 晶粒-黏阽黏著劑黏貼在它上面。具有帶狀或者矩陣的 導線架2裝載許多半導體裝置4,能夠使組合半導體裝 置封裝1期間較為容易處理導線架 在引線接合製程之後，導線架2的帶狀或矩陣通過一 模塑成型製程，其中一電絶線封裝材料8塑模成型包圍 晶粒-銲墊區域2a,接合區域7,半導體裝置4以及引線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — — — — — — — - 1 I I I I I I ·11------ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 6334 7 A7 B7 ___ ----- "B ~ 五、發明說明（） 5,只留下引腳2b的末端伸出封裝材料8。 在模塑成型製程之後，導線架2—値一個將毎一半導 體裝置4,及其各自的晶粒-銲墊區域2a與引脚2b與相鄰 的半導體装置4,及其各自的晶粒-捍墊區域2a與引WP2b 分開。可薙揮地，在楔塑成型製程之後，塗層可以從弓丨 脚2b的末端以及延伸出的散熱塊（如杲有的話）去除。 這個習知技藝的塗佈製程具有許多缺點，特別是 遮住導線架的一些部份或者隨後得去除例如接合區域7 與晶粒-銲墊區域2a上之接地接合區域等區域的塗屬》 此外，這傾習知技蓊的塗佈製程不能塗佈半導體裝置4 的表面，因此，造個傳統的組合方法不能防止模塑混# 物8與半導體裝置4之間的脱層以及後纗界面3的燸米 花破裂。 第2圖顯示一半導體裝置封裝10之剖視圖，其包括輿 半導體裝置封裝1相同的組成，其中同樣的元件被使用 與第1圖相同的圔铖。然而，半導體裝置封裝的組合 方法與第1圈所示之半導醴裝置封裝1有些許的不同》 在封裝10的組合中，在沉積鋅-銘塗層之前，半導體 裝置4藉由一環氣樹脂晶粒-黏阽黏著劑6黏貼至晶粒 -銲墊部份2a。如同上面討論的例子，導線架2起初是 許多導線架2形成帶狀或矩陣的其中之一。在半導體装 置4黏貼至晶粒-銲墊部份2a之後，裝載有黏阽之半導 體裝置4之導線架2的帶狀或矩陣經過引線接合製程使 引線5接合在半導體裝置4的接觸區域與引腳2 b的接合 本紙張尺度適用中國國家標準（CNS)A4規格（2]〇x297公釐） i --------訂--— — — — — — — (請先閲讀背面之注意事項再填寫本頁> 4 6334 7 A7 B7 -1- 五、發明說明（） 區域7之間β 在引線接合製程之後，導線架2的帶狀或矩陣，伴隨 箸黏阽的半導體裝置4與引線5,浸入一電鍍液中，鋅-鉻塗層3藉由電鍍製程電解地沉積在導線架2上圖示的 區域，引線5,以及半導體裝置4的導電表面。 在沉積鋅-鉻塗層3之後，電絶縳的封裝材料8模塑成 型在半導體裝置4,導線架2與引線5的周圍，如同習知 技饉封裝1β導線架2的帶狀或矩陣随後被分成單一半 導體裝置封裝。 第3圖顯示一半導體裝置封裝30,其使用相似於半導 體裝置封裝10的組合方法，然而，半導體裝置4係藉由 銲錫31黏貼在晶粒-銲墊區域2ae因此，由於銲錫31導 電，鋅-絡塗層3也沉積在銲錫31的侧邊β 第4圖顯示一半導體裝置40,其使用相似於半導體裝 置封裝1G、30的組合方法，然而，封裝40包括一功率半 導體裝置41藉由銲錫31黏阽在一增厚的晶粒-銲墊匾域2c β因此，由於銲錫31導電，鋅-鉻塗層3也沉積在銲錫 31的倒邊，如同半導鱔裝置封裝30。此外，由於晶粒-銲墊區域2c的底面未覆蓋材料8,旦銲錫31導熱，晶粒 -銲墊區域2c被作為裝置41的散熱塊^ 在裝置封裝10、30、40中，塗層從導線架2未封裝的 部份移除。在封裝10、30中，塗層從引腳2b未被封裝的 部份移除，在封裝40中，塗層從引脚2b與晶粒-銲墊區 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------.---------J! — 訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 463347 A7
B7 S 五、發明說明（） 域2 c的表面43移除，然而，移除這些部份的塗層並不是 必要的，而且不是唯一一種可能的選擇。 藉由在黏貼半導體裝置4、41至導線架2之晶粒-銲墊 區域2a, 2c,並且形成引線5之後，才沉積鋅-鉻塗層， 便不需要在塗佈製程中遮住導線架2的任何區域。 此外，藉由在引線接合之後，模塑成型之前沉積塗層 3,其優點在於全部的引線接合組合下沉至塗佈製程的 電鍍路徑，並且由於引線5建立從導線架2至半導體裝 置4之電氣接觭表面的電氣路徑，綍-銘塗層3也沉積 在半導體裝置4的電氣接觸表面。半導體裝置4上塗層 覆蓋範圍的程度係取決於表面導電路徑的有效性，這可 能會受到元件設計，金屬的分佈，元件鈍化的種類，本 身/外部鈍化的提供以及本身/外部電性接觸的影罌。 由於電解地沉積的方式可供選擇，使用濕式化學接觸 反應的製程，或者乾式物理/化學沉積製程來沉積塗層 是可能的。此外，雖然鋅-鉻塗層的沉積已經被描逑， 任何金屬的或非金鼹的塗層也能夠使用本發明來沉積β -------- - - - . I i I — — — 1 訂.-------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 體架 導線 半導 粒腳 晶引 鋅半 装 域 封 區 置 墊 装 銲 層 塗 絡 置 裝 廣 導 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 463347 A7 B7 五、發明說明（ 6 # - ο ο 8 9 13 區緣 線粒合絶 引晶接電 劑 著 黏 貼 黏 域 料 材 裝裝 0 封 置置置 裝裝裝 摸匿澧 βηρ 導導導 半半半 錫 銲 域 區 塾 裝置ΡΙ μί 銲 封裝-Ϊ 置體粒 裝導晶 體半的 導率厚 半功增 ---------.-----裝—— (請先閱讀背面之注意事項再填寫本頁) 訂· -I - 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）

Claims (1)

  1. 4 633 4 7 A8 Βΰ CS 1)8 六、申請專利範圍 1. 一種組合半導體裝置封装之方法，包括下列步驟： 黏阽一半導體裝置至一導線架上的晶粒銲墊區域； 在半導體裝置上的電氣接觭區域與導線架的電氣接 觸區域形成電性連接，以形成一裝置/導線架組合； 沉積一黏箸加強塗層於該裝置/導線架组合之曝露 之表面；以及 以一電絶線之材料包覆該塗佈之裝置/導線架組合。 2. 如申請專利範圍第1項之方法，其中該黏箸加強塗層 僳藉由電鍍製程電解地沉積。 3. 如申請專利範圍第1項或第2項之方法，其中該半導 體裝置封裝傑一表面安裝型半導體裝置封裝〇 4. 如申請專利範圍第1項之方法，其中更包括在包覆該 塗佈之裝置/導線架組合後，移除導線架沒有被包覆 之部份上的塗層β 5. —種半導體装置封裝，包括：一導線架；一半導體裝 置黏阽在該導線架之第一部份；由該半導體裝置上的 電氣接觸區域至該導線架上第二部份的電氣接觭區域 之電性連接；一黏著加強塗雇位於該導線架，該電性 連接以及該半専體裝置之表面；以及一電絶緣材料包 覆該半導體装置，該電性連接，以及該導線架之該第 一與第二部份。 6. 如申請專利範圍第5項之半導體裝置封裝，其中該黏 著加強塗層係一金屬塗層。 7. 如申請專利範圍第6項之半導體裝置封裝，其中該金 本紙張尺度適用中國國家標準（CNS)A.l規格（210 X 297公f ) -------^-------裝--------訂·--------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 46334 7 η Lb I)S 六、申請專利範圍 属塗層僳一無機鋅-鉻塗層β 8. 如申請專利範圍第5項，第6項或第7項之半導體裝 置封裝，其中該半導體裝置僳藉由一黏著劑黏貼至該 導線架之第一部份。 9. 如申鯖專利範圍第5項，第6項或第7項之半導體裝 置封裝，其中該半導體裝置傜藉由銲錫貼附至該導線 架之第一部份。 10. 如申請專利範圍第5項之半導體裝置封裝，其中該 半導體裝置封裝僳一表面安裝型半導體裝置封裝。 11. 如申請專利範圍第5項之半導體裝置封裝，其中該 半導體裝置係一功率半導體裝置〇 12. 如申請專利範圍第5項之半導體裝置封裝，其中該 導線架之第一部份形成該半導體裝置的散熱塊，並且 該第一部份之一表面未被該電絶綠材料覆蓋。 -------；-------裝---；-----訂·-------- (請先閱讀背面之注意事項乒4寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公蓳）
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