TW461181B - Logic circuit and its manufacturing method - Google Patents

Logic circuit and its manufacturing method Download PDF

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Publication number
TW461181B
TW461181B TW087119189A TW87119189A TW461181B TW 461181 B TW461181 B TW 461181B TW 087119189 A TW087119189 A TW 087119189A TW 87119189 A TW87119189 A TW 87119189A TW 461181 B TW461181 B TW 461181B
Authority
TW
Taiwan
Prior art keywords
node
controlled
source
input
effect transistor
Prior art date
Application number
TW087119189A
Other languages
English (en)
Chinese (zh)
Inventor
Shunzo Yamashita
Kazuo Yano
Yasuhiko Sasaki
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW461181B publication Critical patent/TW461181B/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
TW087119189A 1997-11-28 1998-11-19 Logic circuit and its manufacturing method TW461181B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32753697A JP3701781B2 (ja) 1997-11-28 1997-11-28 論理回路とその作成方法

Publications (1)

Publication Number Publication Date
TW461181B true TW461181B (en) 2001-10-21

Family

ID=18200202

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087119189A TW461181B (en) 1997-11-28 1998-11-19 Logic circuit and its manufacturing method

Country Status (4)

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US (5) US6124736A (US06696864-20040224-M00004.png)
JP (1) JP3701781B2 (US06696864-20040224-M00004.png)
KR (1) KR100592051B1 (US06696864-20040224-M00004.png)
TW (1) TW461181B (US06696864-20040224-M00004.png)

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US7741879B2 (en) * 2007-02-22 2010-06-22 Avago Technologies Enterprise IP (Singapore) Pte. Ltd. Apparatus and method for generating a constant logical value in an integrated circuit
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Also Published As

Publication number Publication date
US20030071658A1 (en) 2003-04-17
US6400183B2 (en) 2002-06-04
US6124736A (en) 2000-09-26
US6486708B2 (en) 2002-11-26
KR19990045623A (ko) 1999-06-25
US20020149394A1 (en) 2002-10-17
KR100592051B1 (ko) 2006-12-01
US6323690B1 (en) 2001-11-27
JPH11161470A (ja) 1999-06-18
JP3701781B2 (ja) 2005-10-05
US6696864B2 (en) 2004-02-24
US20010054916A1 (en) 2001-12-27

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