TW452938B - A logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit - Google Patents

Abstract

The present invention provides a logic circuit by combining the pass transistor logic circuits and CMOS logic circuits to have excellent performance on circuit characteristic such as the area, delay time and power consumption; a binary decision diagram is made from logic functions, each node of it is converted to a pass transistor selector with 2 inputs, 1 outputs and 1 control input to synthesize a pass transistor logic circuit; and, in the pass transistor logic circuit, one input of the two inputs other than the control signal input is fixed at logical constant ""1"" or ""0"" and used as a pass transistor selector with NAND logic or NOR logic operations and is changed into an equivalent CMOS gate such as NAND or NOR; and, if changed into CMOS gates, the predetermined value of electrical characteristic will be closer to the optimized value (for example, the area, the delay time or the power consumption will be smaller) so as to change the pass transistor selector into CMOS gate.

Description

Imprint of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 45293 8 A7 B7 V. Description of the Invention (1) and related patents in this patent application: This patent application is the first of the international patent application filed on April 24, 1996 Part of PCT / JP96 / 11〇4 is a succession application, and the above-mentioned international patent application is incorporated herein, and the entire content of its publication will be used as a part of this application. International Patent Application No. PCT / JP96 / 1 104 is US Patent Application No. 08 / 633,053 previously filed on April 16, 1996 and US Patent Application No. 08 / filed on April 17, 1996 A part of No. 633,486 continues to be filed, and US Patent Application No. 08 / 633,055 is incorporated herein, and the entire content of its publication is used as a part of this application. The present invention relates to a logic circuit with a small area, high speed, and low power consumption, which is a combination of a channel transistor circuit and a complementary metal oxide semiconductor (hereinafter referred to as CMOS) circuit. Armed know-how In a channel transistor logic circuit that is one of the logic circuits, one electric body can be equipped with various logic functions. Therefore, the channel transistor logic circuit is cleverly constructed, and all the conventional CMOS circuits are replaced by the channel transistor logic circuit, so as to make it large-scale and greatly reduce the transistors of large integrated circuits (hereinafter referred to as LSI). Many studies have been published aimed at reducing the area and power consumption of LSIs. Among them, a binary decision diagram (Binary Decision Deagram) is created from logic functions, and each node is replaced with a channel input selector of 2 input / output / control input to synthesize into a channel with a desired logic function. Method of transistor circuit. • 4-This paper is suitable for financial purposes g | 目 家家 (CNS) (2ι〇χ297 公; ^ ―-- U-„--- 7 --- installation ------- order ---- --t (Please read the note on the back before filling in this page) 452938 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (2) The binary decision diagram consists of the so-called 1 branch and 0 The two branch nodes of the branch are tree-shaped to represent logical functions with a graph, which has the property of expressing complex logical functions in a concise manner. Therefore, this method consists of using a few transistors to synthesize the desired The logic function of small-channel transistor logic circuits has attracted attention. For example, in the Institute of Electrical and Electronics Engineers (hereinafter referred to as ΙΕΕ) 丨 994 non-standard integrated circuit conference meeting pages 603-606 (hereinafter referred to as Document 1) It has been proposed that a 2-input / output channel transistor selector be composed of only an n-type channel electric field effect transistor. 'If necessary, insert a buffer inverter for shortening the delay time, and synthesize it as desired. Channel transistor logic circuit method. In the past CMOS logic circuit, the performance is poor The number of p-type channel electric field effect transistors must be the same as the number of n-type channel electric field effect transistors. However, in the channel transistor logic circuit synthesized by the method of reference 1, in addition to the buffer inverter, The majority of the circuit is composed only of high-performance n-channel field effect transistors. Therefore, compared with the conventional CMOS logic circuit, it can obtain an area delay time and consume less power. In the IEEE 1995 Low-Power Electronic Equipment Symposium Records on pages 14-15 (hereinafter referred to as Document 2), there have been proposals to make Document 丨 more developers. This method is characterized by a multi-segment binary decision diagram ( The following multi-segment binary decision diagrams are the points for synthesizing the channel transistor logic circuit. The multi-segment binary decision diagram is made by the following steps. (1-1) The binary decision diagram is created from the logic function. (1-2) On the binary decision graph of the graph, the section indicated by the 0 branch or the 1 branch -5- This paper size is applicable to the family size (CNS > M specification (plus magic 97). ': --R J --- ^ ——Install ------ ,, ΐτί ----- Bing, please read the back first Please fill in this page again for the item) 45293 8 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention (3) Although the points are different, the same parts as the other figures are extracted (trees of the same type) ' ΐ Newly created the effect of the node β controlled by the homogeneous partial tree from (1-2). The multi-segment binary decision graph can represent logical functions with fewer nodes than ordinary binary decision graphs. From the literature Xia can use fewer transistors to synthesize a channel transistor logic circuit with the desired logic function. Also, the number of nodes connected in series will be suppressed, so the number of segments of the synthesized channel transistor circuit can be suppressed β can thus synthesize a channel transistor logic circuit with a shorter delay time and a smaller area and lower power consumption than that in Reference 1. It has also been proposed in the Technical Research Report Collection (VLD) 95-11 5, Vol. 95, No. 119, pp. 1-6 (hereinafter referred to as Document 3) to synthesize a channel transistor logic circuit with low power consumption. A method for the purpose β In this method, though, as in Document 2, a channel transistor logic circuit is synthesized from a multi-stage binary decision graph, but it suppresses the buffer inverter for delay time to the minimum required. The limit 'synthesis power consumption can be made smaller by channel transistor logic circuits. In addition, channel transistor circuits are disclosed in Japanese Patent Application Laid-Open No. 1-129611 (published on May 22, 1989), Japanese Patent Application No. 216622 (published on August 30, 1989), and Japanese Patent Application Laid-open No. 1-56219 (1989 Published on October 12, 2014), Japanese Patent Application Laid-Open No. 7-130856 (published on May 19, 1995), etc. Also, the synthesis method of the channel transistor logic circuit is described in Japanese Patent Application Laid-Open No. 7-168874 (published on July 4, 1995) or Japanese Patent Application Laid-open No. 9-6821 (published in January 1, 1997). -6- This paper size applies Chinese National Standard (CMS) Α4 specification (2 丨 0X297 public love) n tj— HI .1 ^ 1 ί Μ--I (please read the note $ on the back before filling this page) 4 5 293 8 A7 B7 V. Description of the invention ι (4) Problems to be solved by the invention The inventors used the methods described in Documents 1, 2, and 3 to make a binary decision diagram for several logical functions to actually synthesize channel transistors. Logic circuit. From the results, it can be seen that for some logic functions, it is possible to synthesize a channel transistor logic circuit with fewer transistors, smaller area, delay time, and lower power consumption than the existing CMOS logic circuits. However, for other logical functions, the area, delay time, and power consumption may increase. For example, when a simple two-input "inverted" (hereinafter referred to as NAND) logic is used to synthesize a channel transistor logic circuit by the methods of documents 1, 2, and 3, six circuits of transistor C1 as shown in Fig. 4A can be obtained. . However, in the CMOS logic circuit, it becomes a simpler circuit than four transistors (C2 in FIG. 4A). In addition, for a 2-input "OR" (hereinafter referred to as NOR) logic, the channel transistor logic circuit becomes a circuit of 6 transistors (C3 in Fig. 4A), and in a CMOS logic circuit, it becomes 4 transistors. Circuit (C4 of Figure 4A). As shown in Figs. 4A to 4C, in the NAND logic and the NOR logic, in addition to the power consumption, a circuit with a CMOS gate in terms of area and delay time has better performance. In this way, the channel transistor selection circuit is not suitable for NAND logic or NOR logic because of its circuit structure, but is suitable for selection logic in which a certain signal is selected by another signal. On the one hand, NAND logic's NOR logic is the basic circuit of a CMOS circuit. Of course, a CMOS circuit can be a logic circuit with better performance. However, in terms of power consumption, NAND logic and NOR logic are also smaller if the channel transistor circuit is used. Β This paper music scale applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) n hl ^ i ^^^ 1 n mi l — I ^^^ 1 m * > 0¾. * T '& (Please read the notes on the back before filling out this page) Employees' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Imprint 452938 Central Standards Bureau of the Ministry of Economic Affairs Consumer Cooperative Cooperative Printed Description of Invention (5 This kind of thing has been ignored in the previous research of channel transistor logic circuits, and channel transistor circuits and CM0S circuits each have their strengths and weaknesses, which represent channel transistor circuits Not all things are better than cm0s circuit. In addition, the channel transistor circuit and CM0s circuit are excellent, because the logic circuit they synthesized is in area, delay time, In terms of the characteristics of power-consumption circuits, which one is considered as a priority, it differs. Also, unlike the era of manually designing logic circuits, logic languages are now used as high-level languages such as hardware description languages (HDL). Therefore, how to implement the logic of the combination of "if, then, otherwise" (that corresponds to selection logic) and ^ J_ (B〇〇lean) algebra commonly used in HDL, is how to implement it with small logic circuits. In this way, no matter what kind of logic or priority is given to the circuit characteristics of area, delay time, and power consumption, to create a logic circuit with excellent circuit characteristics, the channel transistor circuit is used. Impossible, the advantages of both the channel transistor circuit and the CMOS circuit must be skillfully combined to create a so-called channel transistor / CM0S that allows the channel transistor circuit and the CMOS circuit to cooperate with each other in a logic circuit. Coordination logic circuit. If a method such as a channel transistor / CM0s coordination logic circuit with excellent performance can be automatically synthesized by a computer system, the performance is small for creating a small area, and the delay time is also small, and the power consumption is also small. It is of great significance on the excellent LSI chip. It also uses the method described in Reference 2 to synthesize private paper from multiple binary decision diagrams. The Zhang scale is applicable to the Chinese National Standard (CNS > A4 specifications < 210X297 gong (please read the note ^ K on the back before filling out this page). Binding and binding 14 45293 8 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs *. A7 B7 V. Description of the invention (6) As a result of the logic circuit of the Dojo transistor, although the transistor can be reduced, 'there may be a delay in some logic but it is slow. The inventors analyzed it alone. As a result, it is known that the following problem exists. That is, in a channel transistor logic circuit synthesized from a multi-segment binary decision graph, a channel transistor selector can be connected to a channel transistor in the subsequent stage via a buffer inverter. Selector control input circuit. At this time, the buffer inverter and the inverter in the subsequent channel transistor selector are connected in series, so that it is understood that the delay time is slow anyway. That is to say, this method of synthesizing a channel transistor logic circuit from a multi-segment binary decision graph has a severe delay time condition, and the above-mentioned problem of delay time becomes a bottleneck, which may be impractical. The purpose of the present invention is to provide a channel transistor / CMOS coordinated delay circuit 'which is capable of cleverly combining various advantages of a channel transistor circuit and a CMOS circuit, no matter what kind of logic, so that the building becomes Compared with conventional logic circuits composed only of channel transistors or logic circuits composed of only CMOS, they are superior in circuit characteristics such as area, delay time, and power consumption. At the same time, a method for automatically synthesizing the channel transistor / CMOS coordination logic circuit with excellent performance by a computer system is also provided. In addition, another object of the present invention is to provide a channel transistor / CMO S coordination logic circuit and a method for synthesizing the same. The system has the advantages of channel transistor circuits and CMOS circuits for any kind of logic. Ingenious combination so that it can be constructed to solve the previous multi-stage binary decision -9-This paper size applies the Chinese National Standard (CNS), see the grid (2iOX297 mm) --L-„--- M-- Install ------ order ------ ^ (Please read the notes on the back before filling out this page) 452938 A7 B7 Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. The problem of the delay time of the logic circuit synthesized only by the channel transistor ', and it has a small delay time, a small number of transistors, or a delay time, the power consumption and other circuit characteristics are excellent β and the purpose of this month is to provide A clever method of combining a channel transistor circuit and a CMOS circuit, and synthesizing them so that they are more ideal as a logic circuit in terms of area, delay time, power consumption and other circuit characteristics, or a combination of these. Resolving Hand In order to achieve the above-mentioned object, the logic circuit of the ideal form of the present invention (Figure 丨) is a logic circuit including a cloth_0_ processing selection logic, which includes: its gate is controlled by the first input (INI), Between the i-th action potential point (VDD) and the first known point (NP1), the ip-type channel electric field effect transistor (TP1) connected to the source electrodeless path; the gate is provided by the second input ( Controlled by IN2), the 2P-type channel electric field effect transistor (TP2) of the source-drain path is connected between the first action potential point (vdd) and the first node (NP1); the gate is formed by Controlled by the first input (IN1), between the first node (NP1) and the fourth node (NP4), the in-channel electric field effect transistor (TN1) connected to the source-drain path; its gate It is controlled by the second input (IN2), and between the fourth node (NP4) and the second action potential point (GND), the 2n-type channel electric field effect transistor (TN2) connected to the source-drain path ; Its gate is controlled by the first node (NPi), at the first action potential point -10- this paper size common Chinese National Standard (CNS) A4 Regulation "Grid (210X297) > (Please read the note on the back before filling in this page) Binding l. Ordering policy of the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, India 452938 A7 ____B7___ 5. Description of Invention (8) (VDD) and Node 2 (NP2 ), A 3P-type channel electric field effect transistor (TP3) connected to the source-drain path; its gate is controlled by the first node (NP1), and the second node (NP2) and the second action Between the potential point (GND), the 3n-type channel electric field effect transistor (TN3) connected to the source-drain path; its gate is controlled by the second node (NP2), and is entered in the third round (IN3 ) And the third node (NP3), the 5n-type channel electric field effect transistor (TN5) connected to the source-drain path; its gate is controlled by the first node (NP1), at the fourth input (IN4) and the third node (NP3), the 6n-type channel electric field effect transistor (TN6) connected to the source-drain path; its gate is controlled by the third node (NP3). 1 The 4P-type channel electric field effect transistor (TP4) between the active potential point (VDD) and the first output (OUT1), which is connected to the source-drain path; and its gate is controlled by the third node (NP3) Control, between the second and the action potential point (GND) first output (0UT1), a source connected to the drain of 4n-channel type field effect transistor (TN4) of the source path. The logic circuit (FIG. 2) of another ideal form of the present invention is a logic circuit including a Boolean processing selection logic, which includes: its gate is controlled by the tenth input (IN10), and at the first action potential point ( VDD) and the 10th node (NP10), the 10th P-type channel electric field effect transistor (TP10) connected to the source-drain path; its gate is controlled by the 10th input (ΙΝ10), Node 10 (NP1〇) and -11-This paper size applies to China National Standard (CNS) A4 specifications (2 [0 · 〆297 mm) * ^^ 1 Bu =: f ^^^ 1 HI- 1-- S — I--*-I ^ (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs: 2: 2 93 3 A7 B7 V. Description of the invention (9) Second action potential Between the point (GND), the 10n-type channel electric field effect transistor (TN10) connected to the source-drain path; its gate is controlled by the 10th node (NP10), at the 11th input (IN11) and Between the 11th node (NP11), a ιη-type channel electric field effect transistor (TN11) connected to the source-drain path; its gate is input from the 10th input (IN10) Control, between the 12th input (IN12) and the 11th node (NP11), the 12n-type channel electric field effect transistor (TN12) connected to the source-drain path; its gate is controlled by the 11th node (NP11) ) Controlled, between the first action potential point (VDD) and the 12th node (NP12), the 15P-type channel electric field effect transistor (TP15) connected to the source-drain path; its gate is controlled by the Controlled by 11 nodes (NP11), between the 12th node (NP12) and the second action potential point (GND), a 15n-type channel electric field effect transistor (TN15) connected to the source-drain path; its gate The pole is controlled by the 12th node (NP12). Between the 1st action potential point (VDD) and the 10th output (OUT10), a 14P-type channel electric field effect transistor (TP14) connected to the source drain path ); Its gate is controlled by the 12th node (NP12), between the 10th output (〇UT10) and the 13th node (NP13), the I4n-type channel electric field connected to the source drain path Effect transistor (TN14); its gate is controlled by the 13th input (IN 13), at the 1st action potential point (VDD) and the 10th output (OUT10) The 13P-type channel electric field effect transistor (TP13) connected to the source-drain path in between; and -12- This paper size applies to the Chinese standard (CNS) A4 specification (210X297 mm) n IF — — — 1 > n I!--_--If · 1¾-I----- (Read the precautions on the back before filling this page) 452938 Α7 Β7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Explanation of the invention (10) The gate is controlled by the 13th input (IN13), and between the 13th node (NP13) and the 2nd action potential point (Gnd), the Πη type which connects the source drain path Channel electric field effect transistor (TN13) »Another ideal form of the logic circuit of the present invention (Figure 3) is a logic circuit including an m-selection logic, which has: its gate is input from the 20th input (IN20 ) Controlled, between the first action potential point (VDD) and the 20th node (NP20), the 20P-type channel electric field effect transistor (TP20) connected to the source-drain path; its gate is 2 Controlled by 1 input (IN21), between the first action potential point (VDD) and the 20th node (NP20), the source-drain path is connected. 21P-type channel electric field effect transistor (TP21); its gate is controlled by the 20th input (IN20), and the source and drain paths are connected between the 20th node (NP20) and the 24th node (NP24) The 22n-type channel electric field effect transistor (TN20): its gate is controlled by the 21st input (IN21), and it connects the active source between the 24th node (NP24) and the 2nd action potential point (GND) The 21η-type channel electric field effect transistor (TN21) of the pole-drain path; its gate is controlled by the 22nd input (ΙΝ22), between the first action potential point (VDD) and the 22nd node (NP22) The 22P-type channel electric field effect transistor (TP22) connected to the source-drain path; its gate is controlled by the 22nd input (IN22), at the 22nd node (NP22) and the second action potential point ( GND), a 22η-type channel electric field effect transistor (TN22) connected to the source-drain path; -13- This paper size applies to China National Standard (CNS) A4 (2 丨 0X29? Mm) — I- I ...... ―-s- m --I- I― * ULr nn HI m ^ i ((Please read the precautions on the back before you fill out this page) Printed by the Zhuhai Bureau Shellfish Consumer Cooperative 5 293 8 A7 B7 V. Description of the invention (11) The gate is controlled by the 22nd node (NP22), between the 23rd input (IN23) and the 23rd node (NP23) , The 23n-type channel electric field effect transistor (TN23) connected to the source-drain path; its gate is controlled by the 22nd input (IN22), at the 20th node (NP20) and the 23rd node (NP23) Between them, the 24n-type channel electric field effect transistor (TN24) connected to the source-drain path; its gate is controlled by the 23rd node (NP23), at the first action potential point (VDD) and the 20th Between the output (OUT20), the 25P-type channel electric field effect transistor (TP25) connected to the source-drain path; and its gate is controlled by the 23rd node (NP23), and at the 20th output (OUT20) A 25n-type channel electric field effect transistor (TN25) connected to the source-drain path is connected to the second action potential point (GND). In order to automatically synthesize such a logic circuit composed of a channel transistor circuit and a CMOS circuit with a computer system, in the present invention, a binary decision diagram or a multi-segment binary decision diagram is created by a logic function, and it is The nodes are all converted into a channel transistor selector with 2 inputs / outputs / control inputs to make a channel transistor logic circuit. And in this channel transistor logic circuit, one of the two inputs is fixed at a logic constant of 1 or 0 as NAND logic or NOR logic (or "AND" logic ("AND"), "OR" (Hereinafter referred to as “OR” logic) The channel transistor selector that is operated is replaced by a logically equivalent CMOS gate such as NAND, NOR, etc., and the circuit characteristics such as area, delay time, and power consumption are calculated. When the characteristic value of the fixed circuit behind the CMOS gate is closer to the most suitable value, the channel transistor will be -14- This paper is in the standard Chinese National Standard (CNS) A4 (210X297 mm) n--fc. I— ^^ 1 In ·-I-i 1 士 " -〆 «^ 1 Hi l ^ i ^^ 1 II H. ^^ 1 I In n U3 6. (Please read the precautions on the back before filling this page) 452938 Fig. 1 Fig. 2 Fig. 3 A7 B7 V. Description of the invention (12) Replace the body selector with CM_. Trial the above operation for all channel transistor selectors to synthesize the most appropriate channel transistor for the given circuit characteristics / CMOS coordination logic circuit. The most suitable circuit characteristics used for this are, for example, area and delay. Time, or power consumption, or an appropriate combination of these conditions * Another ideal form of the present invention is to make a binary decision circle or a multi-segment binary decision graph from a logical function, and in the nodes of the graph, divide it into 2 branches Only one of the (〇 branches, 1 branches) is a node fixed at a logical constant of 1 or 〇, and transformed into a logical equivalent of the node to 〇1 ^ 〇3 such as NAND, NOR, etc. The node is transformed into a 2-input / output channel transistor selector to synthesize a channel transistor / CMOS coordination logic circuit. Figure XX shows the ideal embodiment of the invention β Another preferred embodiment of the invention Another embodiment of the invention.

FIGS. 4A to 4C are comparison diagrams when a NAND logic & NOR logic is configured with a channel transistor selector and a CMOS gate is configured. Fig. 5 A comparison diagram of a channel transistor / CM0s coordination logic circuit according to Embodiment 1 of the present invention, and a conventional channel transistor logic circuit and a CMOS logic circuit. Fig. 6 · A configuration example of a channel transistor / CMos coordination logic circuit according to Embodiment 1 of the present invention. Figure 7: Computer System for Synthetic Logic Circuits in accordance with Embodiment 2 of the present invention-15- ^^ f Int 1 ^ 1 nn —Lf * A Any (#Please read the notes on the back before filling this page ) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, printed on paper. ___ ____ ** Thousands I ΕΓ I ί MNS 452938 A7 B7 Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs of the People's Republic of China 5. The Invention Description (13) Schematic diagram of the logic circuit synthesis program used. FIG. 8 is a flowchart from synthesis of a logic circuit to manufacturing of a semiconductor integrated circuit according to Embodiment 2 of the present invention. Fig. 9 is a flowchart of a synthesis process of a channel transistor / CMOS coordinated logic circuit according to the second embodiment. Figure 10: A circuit diagram of a CMOS logic circuit synthesized from a logic function of Embodiment 2 by a well-known method. FIG. 11 is an example diagram of a multi-segment binary decision diagram made according to the procedure for making a binary decision diagram of a channel transistor / CMOS coordinated logic circuit synthesis procedure of the present invention according to FIG. 9. Figure 12: Transformation rule diagram of the channel transistor selector. Figure 13: Channel transistor / CMOS coordination logic circuit of the present invention according to Figure 9 of the channel transistor conversion rules, the channel transistor logic circuit circuit diagram made from the multi-stage binary decision diagram of Figure 11 Figures 14A to 14D: When the channel transistor / CMMOS tuning logic circuit is synthesized by the method of the present invention, the figure of the channel transistor selector which is transformed into a CMOS gate and its transformation rule diagram. Fig. 15: In the middle of the CMOS gate allocation procedure of the channel transistor / CM0s coordination logic circuit synthesis procedure of the present invention shown in Fig. 9, the intermediate circuit circuit diagram is shown. Fig. 16: In the middle of the CMOS gate allocation procedure of the channel transistor / CM0s @ tuning logic circuit synthesizing procedure of the present invention shown in Fig. 9, the circuit diagram of the intermediate circuit is shown. (Please read the notes on the back before filling this page)

-1 7V 16 · 4 5 2 9 3 8 Printed A7 B7 by Shellfish Consumer Cooperative of Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (14) Figure 17: Channel transistor / CM0s coordination logic of the present invention in Figure 9 In the circuit synthesis program, the circuit diagram of the channel transistor / CMOS coordination logic circuit synthesized when the area is given the highest priority. Figure 18: Circuit diagram of a logic circuit made from the CMOS gate of Figure 10 by converting a CMOS gate into a channel transistor selector. Fig. 19: In the channel transistor / CM0s coordination logic circuit synthesis program of the present invention shown in Fig. 9 ', the circuit transistor / CMOS coordination logic circuit synthesized when the area is given the highest priority is shown in the figure. Figure 20: P-channel And n-channel two-type transistor transistor circuit diagram. Fig. 21: The result when the channel transistor / CMos coordination logic circuit synthesis program of the present invention changes the value from the area first to the delay time. Figure 22: For 11 different logics, the logic circuit synthesized by the channel transistor / CNt0s coordination logic circuit synthesis program of the present invention, and the CMOS logic circuit and channel transistor logic circuit synthesized by the well-known method in the original, Comparison chart of area and power consumption. FIG. 23 is a flowchart of a synthesis procedure of a channel transistor / CMOS coordination logic circuit according to Embodiment 6 of the present invention.

Figure 24: An example of a binary decision diagram made using the channel transistor / CMOS coordinated logic circuit synthesis program of the present invention shown in Figure 23 Figure D: Figure 25: Example of the channel transistor / CMOS coordinated logic circuit synthesis program of the present invention shown in Figure 23 Channel transistor selector / CM〇S gate change process, -17- This paper is generally Chinese National Standard (CNS) Eight Eggs (2 丨 GX297) 嫠-^^^ 1 u W. · --1 nn ^^^ 1 n · — ^ 1 m. nbt #e, i. ^^^ 1 1. < Please read the notes on the back before filling out this page) 45293 8 A7 ^ —__________ B7 V. Description of the invention (15) ~~-The intermediate circuit circuit diagram is made. FIG. 26 The channel transistor selector / CM0s coordination logic synthesized by the channel transistor / CMOS coordination logic circuit of the present invention shown in FIG. 23 into a chip; the road map is shown in FIG. 27. The logic circuit diagram of the channel transistor synthesized by the decision chart ^ ZMM. Hereinafter, the channel transistor / CM0s coordination logic circuit of the present invention and a method for synthesizing the same will be described in detail with reference to several embodiments shown in the drawings. In the following description, the same reference numerals indicate that they are the same or similar. * ≪ Embodiment 1 > An embodiment of the channel transistor / CMOS coordination logic circuit of the present invention will be described with reference to FIG. 5. A, b, and c in FIG. 5 respectively represent the logic assigned by the following logic function 'when constituted by the channel transistor / CM0s coordination logic circuit of the present invention' and the existing channel transistor logic circuit and CMOS logic Comparison diagram when the circuit is constructed. In the figure, the inverter and the CMos closed door shown by simplified symbols are composed of the transistor circuit in Figure 4.a output = [BX (CXD) '+ AXCXD]' b output = [AX (BXD + BXC ) ,;], c output = [BX (CXD) '+ BXA], in FIG. 5a, the channel transistor / CM0S coordination logic circuit of the present invention is composed of an inverter 150, a channel transistor selector S50, CMOS gate G50 Institute-18- This paper size is applicable to China National Standard (CNS) A4 scale (210X297 mm) -----; ---: --- installation ---- 1-^ Order I ------ Line (Please read the notes on the back before filling this page) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and Consumer Cooperatives 45293 8 A7 ___B7_ V. Description of the circuit (16). On the one hand, in the previous channel transistor logic circuits, inverters 150 and 151 and channel transistor selectors S50 and S51 were required. In addition, in CMOS logic circuits, inverters 152 and 154 and CMOS gate G50 were required. ~ G53. As shown in FIG. 5a, in the conventional channel transistor logic circuit, NAND logic and NOR logic that are not suitable for the channel transistor circuit must also be combined with the channel transistor circuit (S51). In addition, in the conventional CMOS logic circuit, selection logic that is not suitable to be configured by a CMOS circuit must also be configured by a CMOS circuit (G51 to G53). In contrast, in the channel transistor / CMOS coordinated logic circuit of the present invention, the equivalent logic in the assigned logic can be selected to form a circuit with a channel transistor selector (S50) suitable for selecting logic, and The other NAND and NOR logic parts, with their appropriate CMOS gates (G50), make up the circuit. In this way, the channel transistor / CMOS coordinated logic circuit of the present invention can implement the logic 'combining selection logic with NAND logic, NOR logic (or AND logic, OR logic) in a small circuit. Therefore, compared with 14 transistors in a channel transistor logic circuit and 20 transistors in a CMOS circuit, as long as there are only 11 transistors in the channel transistor / CM0s coordination logic circuit of the present invention, Can realize the desired logic function, it is known that it is a small area 'low power consumption and excellent circuit performance. Also, in the channel transistor / CMOS coordinated logic circuit of the present invention, the selector S51 equivalent to the channel transistor logic circuit and the inverter 151 portion can be degenerate into a CMOS closed gate G50, so that the channel transistor can be Zhao's logic circuit is the inverter inside selector S51—selector S51—inverter for buffer-19- This paper size applies to Chinese standards (CNS > A4 specification (210X29? Mm) ------ -„-: --- ^ 1— equipment ------- order ------. Up (please read the precautions on the back before filling out this page) staff consumption of the Central Bureau of Procurement, Ministry of Economic Affairs Cooperative printed 6 293 8 A7 B7 V. Description of the invention (17) The delay time of the phaser 151 is reduced to the delay time with the CMOS gate G50. In addition, the selector S51 of the channel transistor logic circuit can be shortened. The inverter with a longer delay time is removed from the path. Therefore, in the channel transistor / CMOS coordination logic circuit of the present invention, the delay time can be greatly shortened compared to the channel transistor logic circuit. When compared with the CMOS logic circuit, Can shorten the path of G51 ~ G53, 152, 154 part of CMOS logic circuit S50, 150 in the channel transistor / CMOS coordinated logic circuit, so the delay time of the channel transistor / CMOS coordinated logic circuit of the present invention is small. Fig. 6 is the configuration of the channel transistor / CMOS coordinated logic circuit of the present invention in Fig. 5a For example, in Figure 6, cell 1 is the NAND gate (G50) corresponding to the CMOS circuit. * Cell 2 is the channel transistor selector (S50). As shown in Figure 6, the height hi of cell 1 and the height of cell 2 are the same. The height h4 is equal, and the widths h2 and h3 of the power supply lines (VDD and GND) of Unit 1 and the widths h5 and h6 of the power supply lines (VDD and GND) of Unit 2 are equal. The CMOS circuit is combined into a logic circuit, which is actually produced. This is also the same in the following embodiments. Also, in the logic of FIG. 5b, the channel transistor / CMOS coordination logic circuit of the present invention is composed of an inverter 160, The 11 transistors formed by the channel transistor selector S60 and the CMOS gate G60 can form a circuit with the desired logic function. On the one hand, in the channel transistor logic circuit, inverters 160 and 161 and the channel transistor are required Selectors S60, S61, to 14 transistors. And at -20- this paper size applies the Chinese National Standard (CNS) A4 specification (210X297mm) ------.------------------- · ----- Lesson (Please read the precautions on the back before filling this page) 452938 Printed by A7 B7 of the Central Standards Bureau of the Ministry of Economic Affairs and Industrial Cooperatives V. Description of the invention (18) Inverter is required in CMOS logic circuit I62, I64, and CMOS gates G60 to G63 require 20 transistors. That is, in this case, it is known that the performance of the channel transistor / CMOS coordination logic circuit of the present invention is the best. In addition, in the delay time, the channel transistor / CMOS coordination logic circuit of the present invention can degenerate the portion of the selector S61 and the inverter 161 in the channel transistor logic circuit into one CMOS gate G60, so In the selector S61 of the channel transistor logic circuit, the delay time of the inverter selector S61-the buffer inverter 161 can be shortened to only the delay time of the CMOS gate G60. In particular, the selector can be removed The slower inverter in S61 can significantly reduce the delay time compared to the channel transistor logic circuit. And, compared with the CMOS logic circuit, the channel transistor / CM0S coordination logic circuit of the present invention can shorten the path of the G61 ~ G63, 162, and 164 parts in the CMOS logic circuit to S60, 160. Therefore, the channel transistor of the present invention / The delay time of the Cm0s coordination logic circuit is small. Also in FIG. 5c, the channel transistor / CMOS coordination logic circuit of the present invention is composed of an inverter 170, a channel transistor selector S70, and a CMOS gate G70. With 11 transistors, a desired logic function can be formed. The circuit. On the one hand, in the channel transistor logic circuit, inverters 170 and 171 are needed, and the channel transistor selectors S70 and S71 need 14 transistors. In addition, in the CMOS logic circuit, inverters 172, 174, CMOS gates G70 to G73 are required, and 20 transistors are required. That is, in this case, it is also known that the performance of the channel transistor / CMOS coordination logic circuit of the present invention is the best. In terms of delay time, for the same reasons as in Figure 5a and b, the channel transistor of the present invention / CMOS coordination is used. 21-This paper size is applicable to China National Standard (CNS) A4 (210X297). (Please first Read the notes on the back and fill out this page)

H Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs 2 9 3 8 V. Description of the Invention (19) The logic circuit is the smallest "< Embodiment 2 > In the above embodiment, 'a simple logic is used as an example to explain The channel electric crystal Zhao / CMOS coordination logic circuit of the present invention. In this embodiment, the more complex logic is excellent in circuit characteristics such as area, delay time, and power consumption. The high-performance channel transistor / CM0s coordination logic circuit is automatically implemented by the computer system of FIGS. 7 and 8. The method of synthesis is explained. (1) Overall structure of the system In FIG. 8, the designer will describe the specifications of the logic function of the desired semiconductor integrated circuit, and input them into the logic circuit specification 10. In the logic circuit specification 10, a logic function describing a logic function of the circuit is recorded. In addition, it records and stores the characteristics and target values of the circuit such as the area, delay time, and power consumption of the circuit, and records information that prioritizes the characteristics of that circuit. The channel transistor / CM0S coordination logic circuit synthesis program 100 unique to this embodiment is composed of information recorded in the logic circuit specification 10 and referring to the database n to synthesize circuit characteristics such as area, delay time, and power consumption. The target value is a channel transistor / CM0s coordination logic circuit 12 with a logic function of logic circuit specification 10. The automatic configuration program 160 refers to the database u, determines the configuration most suitable for the logic circuit, and creates the configuration data 20. The mask data creation program 170 determines the mask patterns when using the semiconductor integrated circuit technology to make the logic circuits synthesized as described above in accordance with the configuration data 20 to create mask data 21 representing these mask patterns. The semiconductor manufacturing apparatus 180 uses the mask material 21 to manufacture a semiconductor integrated circuit having a desired logic function. ϊ〇〇, 16〇, • 22- This paper applies Chinese National Standards (CNS) A4 * l (210X297 mm) (Please read the precautions on the back before filling this page)

Work and Consumption Cooperation, Du Printing & Printing by the Central Bureau of Standards, Ministry of Economic Affairs > 93 8 A7 _ B7 V. Description of Invention (20) 170 Each program is executed on a different computer. Of course, these programs can also be executed on the same computer. FIG. 7 is a schematic structure of a channel transistor / CMOS coordination logic circuit synthesis program 100 of the present invention and a computer system for executing the program. The computer system 疋 is composed of input devices such as a keyboard i, a central processing unit (cpu) 2, a display device (CRT) 3, a magnetic tape device 4, and a magnetic disk device 5 storing a logic circuit synthesis program 100. The program 100 is composed of a binary decision chart, a manual record of 110, and a channel transistor selector conversion procedure of 120 ′ and a CMOS gate allocation procedure of 13. This program is an instruction given by the designer from the keyboard 1 and inputted to the CPU 2 from the magnetic disk device 5 and executed. The channel transistor / CMOS coordination logic circuit synthesized by the program 100 will be displayed on (11:11, 3, and passed to the automatic configuration program of FIG. 8 through the tape device 4 etc.). The feature of this embodiment is The purpose is to make a binary decision diagram, and find out the part of the channel transistor circuit synthesized by the channel transistor selector that has a better performance when changing to a CMOS circuit. Combination to synthesize a channel transistor / CMOS coordinated logic circuit with better performance than a separate channel transistor or a CMOS single logic circuit. Specifically, one of the two inputs will be It is fixed at a logic constant of 1 or 0, and the channel transistor selector that operates as NAND logic or NOR logic (AND logic or OR logic) is replaced with a CMOS gate such as NAND, NOR, etc., which is equivalent in the late series, and calculates it. The values of circuit characteristics such as area, delay time, and power consumption, such as when the CMOS closed Π is close to the most suitable circuit characteristic value, will be used. (CNS) A4 size (210X25 »7mm) n H ^^ 1 S .-- 1 ^^ 1-11. I ^^ 1 I ^^ 1 I-,-----IWH.-- I 1 i-— ^ i (Please read the precautions on the back before filling in this page) 45293 8 Α7 Β7 V. Description of the invention (21) The operation of switching the transistor selector to a CMOS gate will be replaced by a CMOS circuit The performance will be better, reorganized into a CMOS circuit. Below, the following logic function is taken as an example to illustrate the procedures of this embodiment. Output 1 = BX A '+ CXA + (I'XF_ + D') X (D + ( H + E) X (E + G)) outputs asB '+ GrXF' + DjXtD + iH + E'XCE + G))), and when this logic function is used to synthesize a cmos logic circuit by a conventional method The circuit consisting of G100 ~ G111m as shown in Figure 10 can be obtained. Β Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Printed by Shellfish Consumer Cooperative (2) Binary decision-making chart making manual no. This procedure 110 is made from logic circuit specifications 丨 〇 Meta decision diagram. The delayed circuit specification 10 includes input variables and output variables corresponding to input signals and output signals of a logic circuit to be synthesized, and a logic function representing a logic function of the circuit. When a binary decision graph is created from the above logic function, a graph composed of nodes N100 to N111 as shown in Fig. U can be prepared. In the multi-segment binary decision graph of the graph η, after the nodes N104 to N109 are collectively combined into a multi-segmentation, the number of nodes is reduced from the ordinary binary decision graph. In order to create a binary decision graph with a small number of nodes, the order of the input variables in the graph creation process is very important. However, the input variable order can be created using the well-known binary decision graph creation tool. To decide. (3) Channel transistor selector conversion procedure 120. This procedure is made in accordance with the transformation rules of Fig. 12 and is made by the binary decision diagram making procedure 110. Each node of the meta decision diagram is converted to Tong-24 according to the node type. This paper size is applicable to China National Standards (CNS) Α4 scale (21〇 > < 297mm) (Please read the notes on the back before filling this page) Ding 4 5 2 9 3 8 Central Standards Bureau, Ministry of Economic Affairs Bei Gong Consumer Cooperative Seal A7 B7 V. Description of the invention (22) A transistor selector or inverter, etc., to make a channel transistor logic circuit. If necessary, insert an inverter for buffering. As shown in the node N1 of FIG. 12a, the front ends connected to the 1 branch and the 0 branch are not logical constants 1, and when 0, the 2 inputs / outputs formed by the n-channel field effect transistor TO, T1, and the inverter 10 Corresponds to the channel transistor selector SO. On the control input of the transistor selector SO of this channel, the input variable A assigned to the node corresponding to the binary decision graph is assigned to the input ini selected when its control input is 1, and the node connected to the 1 branch is assigned. Its output. The inO selected when the control input is 0 is assigned to the output of the node connected to the 0 branch. As shown in the node N2 of FIG. 12b, the 1 branch is connected to the logical constant ι, and the 0 branch is connected to the logical constant 0. The output of this node is 1 when the input variable A of the node is 1, and the output when the input variable A is 0. Output 0. That is, as long as the input signal A is connected to the subsequent circuit as it is. Also, as shown in the node N3 * of Fig. 12c, the 1 branch is connected to the logical constant branch when the logical constant 1 is connected to the node. The output of this node is the node's input variable A is 1 and 0 is output, and the input variable A is 0. 1. That is, the input signal A can be connected to the back-end circuit by inverter inversion. By such a transformation, a channel transistor logic circuit having the same logic function as the binary decision graph can be synthesized. When synthesizing the channel transistor logic circuit based on the binary decision diagram of FIG. 11 ', the channel transistor logic circuit composed of the channel transistor selectors S100-S105 and the inverters Π00 to 1105 as shown in FIG. 13 can be synthesized. In this circuit, 1100'1103 and 1105 are buffering inverters. Figure u -25- This paper size applies Chinese National Standard (CNS) A4 specification (210X297). ----: --- r --- 政 ------ 1T ------ d, {Please read the notes on the back before filling this page} 452933 A7 ____B7 V. Description of the invention (23) (谙 Please read the back: first item and then fill in this page) Nodes N102, N103, and N109 in the binary decision diagram are Corresponding to b of the transformation rule of FIG. 12, nodes N106, N107, and N111 are equivalent to c of FIG. The other nodes are equivalent to a in FIG. 12. (4) CM0S gate allocation procedure 130 as shown in Fig. 9 'This procedure is the channel transistor logic circuit created by the channel transistor selector conversion procedure 120. It is considered that the CMOS recombination in area, delay time, consumption The circuit characteristics such as power will be better. As a channel transistor selector of NAND logic, NOR logic (or AND logic, OR logic), it is recombined as a CMOS cabinet. Printed by the Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs. First, from the channel transistor logic circuit, a channel transistor selector corresponding to the transformation diagram of a to d in FIG. 14A is selected. In the channel transistor selector shown in a to d of FIG. 14A, one of the two inputs is fixed at vdD or GND potential, that is, fixed at a logic constant 1 or a logic constant 0, and as NAND logic, Selector for NOR logic (or AND logic, OR logic) action. In process 131, these channel electrical crystal selectors are converted into CMOS gates in accordance with the transformation diagram of Fig. 14A. In the conversion diagram of FIG. 14A, the two inputs of the CMOS circuit shown by simplified symbols: NAND gate (FIG. 14B), 2-input NOR gate (FIG. 14C) 'and inverter (FIG. 14D) The transistors T10-T13, T20 ~ T23, T3 0 ~ T31 are transistor-level circuits. As can be seen from the transformation diagram of 囷 14A, a channel transistor selector is not necessarily transformed into a CMOS gate. Usually, the polarity must be the same, and an inverter is required. Therefore, when the channel transistor selector is converted to a CMOS gate only in accordance with the conversion diagram of FIG. 14A, the original inverter and the converter will be used. This paper standard applies to the Chinese National Standard (CNS) A4. (2 丨 0X297 mm) Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs of the People's Republic of China 46293 8 A7 ------ B7 V. Description of the Invention (24) The inverter is formed to make the polarity uniform. Possibility of 2 lengthy inverters connected in series. That is, to create a channel transistor / CM0s coordination logic circuit with excellent circuit characteristics such as area, delay time, and power consumption, it is necessary to extend and combine the inverters to remove such a wasteful inverter from the circuit. . It is also possible to consider the possibility of transforming the channel transistor selector to a CMOS gate to form a circuit in which the channel transistor selector directly drives a CMOS gate. However, in this case, Although the buffering inverter β is inserted between the transistor selector and the CMOS gate, the above-mentioned inverter extended combination and buffer insertion processing are mutually opposite processings, but these two processings may be performed. Bringing them together at the same time can make it possible to insert a buffered inverter in the place where it is needed, without the presence of a redundant inverter ', and having excellent circuit characteristics such as area, delay time, and power consumption. Crystal / CMOS Coordination Logic Circuit (Process 132) »Next, for the circuit that has been extended and merged with the inverter and the buffer is inserted, calculate the area, delay time, and power consumption of the circuit. The value of the circuit is calculated from the values of these circuit characteristics. The value obtained by converting the circuit obtained after this into the CMOS gate and the value obtained beforehand by converting it into the circuit before the CMOS gate are compared (processing 133). If the value of the circuit converted to the CMOS gate is better, choose the circuit after the conversion to the CMOS gate. If the value of the channel transistor selector is better than that of the CMOS gate, change the circuit back to the circuit before the CMOS gate. In this way, among the CMOS gate and the channel transistor selector ', the one with better value is selected (Process 134). The above-mentioned processing is performed on all channel transistor selectors equivalent to the transformation map of FIG. 14A. Hi ~ 134 -27- This paper size applies the Chinese national standard (CNS > A4 specification (2 丨 0X297 mm) " .---- ----. Install ------ ^ Order ----- line (please read the precautions on the back before filling out this page) 45293 8 A7 B7 Printed by the Bayer Consumer Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs® V. Description of the invention (25)-Later, all channel transistor selectors with better circuit characteristics when changing to ⑽S gate combination will be changed to C_gate combination to make circuit characteristics such as area, delay time, and power consumption. Excellent channel transistor / Cm0s coordination logic circuit. In this method, 'the definition of the value determined by area, delay time, and power consumption can be changed' to control the focus on area, delay time, and power consumption For example, in the value defined by 135 in Figure 9, 'set area priority α, delay time priority is not set, and power consumption priority is low, delay time and power consumption are not considered. , Channel transistor only for reducing area / CMOS coordination logic circuit synthesis. If set to α = 0, / 5-0, r = 1, the channel transistor / CMOS coordination logic circuit β with power consumption as the highest priority will be synthesized. Of course, it can also be It is good to make it into three characteristics. For example, when setting α = 1, 5 = 1, 7 = 1, the area, delay time 'and power consumption are considered, and the synthesis channel transistor / CM0S coordination logic circuit In the following description of this embodiment, from the channel transistor logic circuit of FIG. 13, the area has the highest priority (the value defined by 135 in FIG. 9 is set to α, cold = 0, r = 0), and the channel transistor is synthesized. / cmos method of coordinating logic circuits ”囷 13 The selector S100 in the circuit is equivalent to the transformation diagram a of FIG. 14A, so 'from processing 131' is converted to a CMOS gate to form the intermediate circuit of FIG. 15. The intermediate circuit of FIG. 15 In the channel transistor selector s1, as it is, it will be a form of directly driving the CMOS gate G100, so it must be inserted. -28- This paper standard is generally China National Standard (CNS) A4 size (210X297mm) ) (Please read the notes on the back first (Fill in this page) Binding l · I ^ --- 93 8 A7 B7 Printed by the Employees' Cooperative of the Central Government Bureau of the Ministry of Economic Affairs. 5. Description of the invention (26) Inverter 1108 for buffering. The polarity of the inverter ιι〇8 is the same, and the inverter 1107 must also be inserted. However, the inverter no. 07 is connected in series through the selector S101 and the original inverters Π01 and II 〇2. The long inverters formed are thus removed by the extended merge process of process 132. Inverters 1100 and 1106 are also redundant and can be removed, and a channel transistor / CMOS coordination logic circuit as shown in FIG. 16 can be obtained. When referring to the database η to calculate the circuit area of FIG. 16, the value becomes 992 / zn ?, and the value becomes the same value as the value of the area. On the one hand, the area before the channel transistor selector sl100 was recombined into a CMOS gate was 1164, and the value also became that value. That is, the value is better when converted to a CMOS gate. Therefore, the circuit converted to a CMOS gate will be selected. Among the remaining channel transistor selectors in the circuit of FIG. 16, S104 and S105 are equivalent to the figure. The conversion diagram e of 14A is also converted to a CMOS gate. However, for the channel transistor selector s105, when the circuit is formed by the channel transistor selector, the area is small and the value is good. Therefore, Not changed to CMOS gate. From the above processing, the channel transistor / CMOS coordination logic circuit as shown in Fig. 17 is finally merged. Table 1 is a circuit formed by the logic function of the embodiment 2. For the channel transistor / CMOS coordination logic circuit and the CMOS logic circuit, the channel transistor logic circuit, and the CMOS logic circuit synthesized in accordance with the present invention Compare the logic circuit formed by the channel transistor with its area, delay time, and power consumption. Table 1-^ -------- r--install ------- ^ Order L ----- ^ (Please read the precautions on the back before filling this page) CMOS channel transistor Results of the invention-29- A7 45293 8 _______ B7 V. Description of the invention (27) (Figure 10) Direct conversion (Figure 18) Area priority (Figure 17) Area priority (Figure 19) Power consumption priority (113) Area (" ηή 1380 (1.00) 1984 (1.44) 906 (0.66) 949 (0.69) 1164 (0.84) Delay time (ns) 1.72 (1.00) 2.66 (1.55) 1.61 (0.94) 1.39 (0.81) 1.55 (0.90) Electricity (ji / W / MHz) 347 (1.00) 219 (0.63) 150 (0.43) 183 (0.53) 140 (0.40) As shown in Table 1, when the channel transistor / CMOS coordination logic circuit synthesized using the area of this method is the highest priority Compared with the logic circuit composed of CMOS alone, the area has been successfully reduced by nearly 40%, and the delay time and power consumption have also been reduced to nearly 5% and 60% respectively. In addition, the logic circuit formed separately from the channel transistor ( (Figure 13) During comparison, although the delay time and power consumption are poor, it is known that it can synthesize a channel transistor / CM0s coordination logic circuit with a small desired area. As also described in Embodiment 1, the channel power What the body selector is most proud of is not the NAND logic or the NOR logic, but the so-called selection logic that selects some of the most signals with another signal. In this method, a unitary is made from the given logic function Determine the diagram, and after creating a separate logic circuit of the channel transistor, convert the channel transistor selector that functions as Nand logic, NOR logic (or AND logic, or OR logic) into a CMOS gate for recombination. Logic circuit. Since it is combined with this sub-shore -30- This paper size applies the Chinese National Standard (CNS) A4 specification (2 丨 0 X 297 male f) ------- n 1 ^ 1 —- --I ^^ 1. II— In 1 I -Γ -lgJ * I 1 = II (谙 read the note i on the back side before filling in this page) Central Standards Bureau, Ministry of Economic Affairs, Consumer Cooperatives, Printing Standard Bureau employee consumer cooperative mark 45293 8 A 7 B7 5. Invention description (28) into a logic circuit, so from the assigned logic function, it will be equivalent to selecting the logic part and assigning it to the channel transistor selector. Others Equivalent to NAND logic or NOR logic (or AND Series, OR logic) part allocated to CMOS gate. In this way, each of the channel transistor selector and the CMOS gate can be adapted and suitable, and a channel transistor / CMOS coordinated logic circuit combining the advantages of the channel transistor selector and the CMOS gate can be made. Instead of using the logic circuit synthesis method of the present invention, the channel transistor and the CMOS gate can be made into a logic circuit only by a general combination. For example, it is also possible to use a completely reverse order to this method. After making a separate CMOS logic circuit, find out the part suitable for the channel transistor selector from the CMOS gate of the circuit, and transform the part into the channel transistor selector. Make a circuit composed of a channel transistor and a CMOS gate. However, in CMOS logic circuits, all logic is composed of a combination of NAND logic and NOR logic (or AND logic, OR logic). Therefore, among the assigned logic functions, there are logics suitable for channel transistor selection. There are some parts, but it is difficult to find the corresponding part. In fact, when the CMOS logic circuit (Fig. 10) synthesized by the logic function of this embodiment is replaced with a channel transistor selector, a channel transistor circuit as shown in Fig. 18 can be obtained. In this circuit, one of the two inputs of all channel transistor selectors is fixed at VDD or GND potential, and is used as NAND logic and NOR logic that are not suitable for channel transistor selectors. None of the channel transistor selectors is used as selection logic. Therefore, as shown in Table 1, the circuit of Figure 18 is in the area, late -31-This paper size applies the Chinese National Standard (CNS) A4 specification (2! 0X297 mm)-: ----- ^ J.- -Install ------ r ^ L ----- ^ (Please read the notes on the back before filling out this page) 45293 8 A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs *. V. Description of the Invention (29) All the circuit characteristics of delay time and power consumption are inferior to those of the CMOS single logic circuit (Figure 10) or the channel transistor alone (Figure 13). In this way, it is known that it is difficult to make a logic circuit with clever combination of the advantages of a channel transistor and a CMOS gate from a CMOS logic circuit. In the worst case, in this example, a circuit whose performance is worse than any of a logic circuit composed of a CMOS alone and a circuit composed of a channel transistor alone is made. From the above, it is impossible to just cleverly combine the advantages of the channel transistor selector and the CMOS gate with the usual combination of the CMOS gate and the channel transistor selector. The worst case is This results in a logic circuit with poor circuit characteristics that combines only those shortcomings. That is, it is not possible to synthesize circuits in the order shown in this method to synthesize channel transistors / CMOS coordination logic circuits with clever combinations of the advantages of each channel transistor selector and CMOS gate. < Modification of Embodiment 2 > In Embodiment 2, the channel transistor selector is described by using only an n-type channel electric field effect transistor as an example, but a p-type channel and an n-type channel are used as an example. The channel transistor selector (such as the transistor T200 ~ T203 and the inverter 1200 in FIG. 20) composed of two types of transistors is exactly the same as that in the second embodiment. Channel transistor / CMOS coordination logic circuit. This is exactly the same in the following embodiments. < Embodiment 3 > This embodiment takes the same logic function as in Embodiment 2 as an example, and adopts -32- This paper size applies the Chinese National Standard (CNS) Rule 8 4 "Grid (210X297 cm) C (Please read the precautions on the back before filling this page)-Binding.-Line _ Seal of the Central Laboratories of the Ministry of Economic Affairs, Consumer Cooperatives, Seal 45293 8 A7 _____B7_ V. Description of the Invention (30) The delay time of the second embodiment is different. Priority (In the value of Π5 in Fig. 9, set α = 0, not = 1'r = 0 '. Take the synthetic channel transistor / cmos coordination logic circuit as an example to explain 2. Similar to the second embodiment, the manual is used to make a binary decision diagram. No creates a binary decision diagram, and the channel transistor selector circuit 12o creates the channel transistor logic circuit of FIG. 13. In the channel transistor logic circuit of FIG. 13, the channel transistor selector Si0〇 is first selected. The processing 131 is converted into a CMOS gate. Secondly, the output of the selector 5101 is inserted in the processing 132, and the buffering inverter is inserted to remove the lengthy inverter to obtain the intermediate circuit of FIG. Case 2 is different, the calculated Not the area but the delay time, the value of the delay time becomes the value of this circuit. The delay time of the circuit (Figure π) before the change to the CMOS gate combination is the input f — selector S104-> selector S102 — buffer response Phaser II 〇3 —Inverter in selector S100—Selector S100—The delay time of the path of the buffer inverter 1100. On the one hand, the path corresponding to the circuit changed to the CMOS gate combination (Figure 16) is Shortened to round F — selector s 104 — selector S102 — buffer inverter 1103 — CMOS gate G100, so the delay time is greatly reduced. Therefore, the circuit value changed to the CMOS gate combination is better, and it will be selected in processing 134 Circuit changed to CMOS gate combination "As explained in the item of the problem to be solved by the invention, in the single logic circuit of the channel transistor composed of the binary decision graph, there will be a channel transistor selector via the buffer An inverter is connected to the control input of the channel transistor selector in the subsequent stage (inverter-S100 in S102— 1103—S100 in Figure 13). In this case, the inverter and buffer are used for buffering. -33 of this paragraph-This standard applies to China National Standard (CNS) A4 specification 7 ^ 10X297 mm}---'---- 1--installation ------ ^ order l · ----- 硪(Please read the note on the back before filling in this page) 45293 8 Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of the invention (31) The inverter in the channel transistor selector is connected in series, regardless of How long the delay time will be longer * But 'is already explained in the first embodiment, if the channel transistor in the latter stage is cleverly changed to a CMOS gate combination in this example, the channel transistor selector can be omitted. Slower eyepieces can therefore be used to make logic circuits with shorter delay times. In general, changing the separate logic circuit of a channel transistor to a channel transistor / CMOS coordinated logic circuit can shorten its delay time. Among the remaining channel transistor selectors, S104 and S105 correspond to the conversion diagram of FIG. 14A. In the second embodiment with the highest area, only SiO4 is changed to a CMOS gate, and in this embodiment with the highest delay time, S105 is also converted into a CMOS gate. The reason is that, as in the case of S100, the selector S105 can be converted to a CMOS gate to remove the slower inverter 'in the selector s 105, and the delay time can be further reduced. Through the above operations, a channel transistor / CMOS coordination logic circuit as shown in FIG. 19 is finally obtained. As shown in Table i, this embodiment also synthesizes a channel transistor / CMOS coordinated logic circuit by this method, and successfully reduces the delay time of a logic circuit composed of CMOS alone by nearly 200/0. When compared with the logic circuit formed by the channel transistor, it also successfully reduced the delay time by nearly 10%. < Embodiment 4 > In this embodiment, the difference between the embodiment and the embodiment 2 is that the power consumption is the highest priority (the value of 135 in FIG. 9 is set to α = 0, Ling = 0, γ = ι ) The method of synthesizing a channel transistor / CMOS coordinated logic circuit is described by taking the same logic function as in the second and third embodiments as an example. Same as in Examples 2 and 3, in Binary-34- this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm > (Please read the precautions on the back before filling this page). Pack * 11 45293 8 Α7 Β7 Imprint of the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Description of the invention (32) Decision diagram making procedure 110 creates a binary decision diagram, and passes through the channel transistor selector transformation procedure 120 to create the channel circuit of FIG. 13 In the channel transistor logic circuit of FIG. 13, the selector S 100 is first selected, and after processing 131 and 132, the intermediate circuit of FIG. 16 is obtained. In the second processing 133, and the second and third embodiments, 3 is different, after calculating the power consumption of the circuit, the value of this power consumption becomes the value of the circuit, referring to the database of FIG. 1 to calculate the power consumption of the channel transistor / CMOS coordination logic circuit of FIG. 16 when it becomes 143 VW / MHz. On the one hand, the power consumption of the circuit before conversion to the CMOS gate (Fig. 13) is 140 " W / MHz '. Therefore, it is different from the second and third embodiments in that when the circuit is formed by a channel transistor selector, its value is on Better. That is, the circuit selected in processing 134 is not a circuit after being changed to a CMOS gate, but a circuit composed of a channel transistor selector. It is equivalent to the remaining channel transistor selection of the transformation diagram of FIG. 14A The selectors are S104 and S105, and these two selectors are also different from those in Embodiments 2 and 3. 'When the circuit is formed by a channel transistor selector, the power consumption is small' and the value is better. In this embodiment with the highest priority for power, the channel transistor logic circuit of FIG. 13 is output as it is without changing to a CMOS gate. The reason is that the comparison result of the channel transistor selector and the CMOS gate in FIG. 4A also has The power consumption of the channel transistor selector shown is much smaller than that of the CMOS gate (less than half of the CMOS gate). This is because the channel transistor selector will occupy most of the selector part of the selection circuit and only η-channel electric field effect transistor is used to reduce the poor performance of p-channel electric field effect transistor, so that its performance will not be deteriorated. " 35-This paper is applicable to China Standard (CNS) A4 grid (210X297 public love) ^^ 1 I ^ — ^ 1 I ..... »— > ^ 1 1 ^ 1 — ^ 1 11--¾ In m I n (Read the poem first Note on the back page, please fill in this page again) 45293 8 A7 _____ B7 V. Description of the Invention (33) The total width of the transistor gate in the transistor selector circuit of the suppression channel can reduce its power consumption. ≪ Examples 5 > Printed by the Consumer Affairs Cooperative of the Central Bureau of Standards and Quarantine of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) In the method of synthesizing the channel transistor / CMOS coordination logic circuit of the present invention, it is considered to be converted into a CMOS gate When the circuit performance is better, the channel selector that operates as NAND logic or NOR logic (or AND logic, OR logic) is converted to a CMOS gate, but in fact, whether to change to a CMOS gate, The channel transistor selector is converted into a cMOS gate, and the value defined by the area, delay time, and power consumption of the circuit is calculated by sf to determine whether the value is good. Therefore, this method is also known from the above embodiments 2, 3, and 4. When synthesizing the channel transistor / CM0s coordination logic circuit, the value defined by the area, delay time, and power consumption is added. By changing, the ratio of the channel transistor selector and the CMOS gate can be changed to control various characteristics of the synthesized circuit softly. For example, Figure 2 丨 is a logic function with a larger scale than that of Embodiments 2, 3, and 4 (approximately 1,000 gates converted by CM0s gate) as an example. In the value of 135 in Figure 9, the area priority α and The power consumption priority r changes from 0 to 丨, so that it changes from the area's highest priority to the power consumption's highest priority, and the result of the combined channel transistor / CM0s coordination logic circuit can be seen from the results in Figure 21, As the priority of power consumption increases, the ratio of channel transistors suitable for reducing power consumption will increase, and the channel transistor / CM0s coordination logic circuit that is synthesized as a priority of power consumption will be synthesized. Crystal / CM0s coordination logic circuit-36- The paper size is applicable to China National Standards (CNS) A4 specification (21 × 297 mm) 45293 8

V. Description of the invention (34) In the heart of the Central Standard Bureau of the Ministry of Economic Affairs, the Pui Gong Consumer Cooperative, the characteristics of the synthesized circuit of the control channel transistor selector and the control gate of the CM0S gate. In addition, from this result, it is known that when the logic of ^ = scale constitutes a channel transistor to coordinate the logic circuit, the area, delay time, and power consumption of the three circuits are slightly different. The best balance is the area of the body circuit when the channel is electrically The ratio is approximately 1G to 6G% of the entire circuit. In this method, only when the circuit characteristics such as area, delay time, power consumption and other characteristics of the circuit can be better, will the channel transistor selector be converted into a channel. Therefore, in this method, No matter what kind of logic function, a logic circuit composed of a channel transistor alone or a logic circuit composed of a CMOS gate alone can be synthesized, and a channel transistor / CMOS coordinated logic circuit having superior circuit characteristics is synthesized. For example, FIG. 22 is a channel transistor / CMOS coordination logic circuit synthesized by this method for 12 types of logic (the gate is converted to cm0s, with 1000 ~ 10000 gates) larger than the logic of FIG. 21. The result of comparison between the separate logic circuit of the channel transistor synthesized by the previous method and the CMOS separate logic circuit. From this result, it can be known that, in this method, no matter what kind of logic, a single channel circuit and a CMOS separate logic circuit, which are superior to conventional channel transistors, can be synthesized. Crystal / CMOS coordination logic circuit. < Embodiment 6 > The above embodiment explains the sequence of synthesizing the channel transistor / CM0s coordination logic circuit by the program of FIG. In this embodiment, the method of synthesizing the channel transistor / CMOS coordinated logic circuit by the program of FIG. 23 will be described below. Β and -37- This paper standard is applicable to China National Standard (CNS) A4 specification (21 × 297 mm)- -. „--- Γ— Install ------ ^ Order ----- 婊 (Please read the precautions on the back before filling in this page)

45293 B A7 B7 Shellfish consumer cooperation of Central Standards Bureau of the Ministry of Economic Affairs Du Yinzhuang 5. Description of the invention (35) The same applies to the above-mentioned embodiments 2 to 5. First, a binary decision diagram is created from the binary decision diagram 110 and a binary decision diagram < » What is different from Embodiments 2 to 5 is that from this binary decision diagram, the channel transistor / CMOS coordination logic is directly synthesized by the channel transistor selector / CMOS gate conversion procedure 300 without making a channel transistor logic circuit. "Circuit Point" The following uses the binary decision diagram of Fig. 24 as an example to explain the channel transistor selector / CMOS gate conversion procedure 300. First, the processing 301 'converts the node N301 corresponding to b in Fig. 14A into a CMOS gate (G301, 1300 in Fig. 25) in accordance with the transformation graph' in Fig. 14A. The other nodes N300, N302, and N303 are converted into channel transistor selectors and inverters (S300 and 1301 in Fig. 25) in accordance with the conversion rules in Fig. 12 »The intermediate circuit in Fig. 25 is thus prepared. In the intermediate circuit of FIG. 25, the inverters 1300 and 1301 are long inverters, and are therefore removed by the processing 303. Finally, the circuit of FIG. 26 is synthesized. In the channel transistor / CM0s coordinated delayed circuit synthesis program (circle 9) of Embodiments 2 to 5, the channel transistor logic circuit is first made, and the pair is used as NAND logic or NOR logic (or AND logic, OR logic). Logic) The channel BB body selector of the circuit calculates the value of its circuit defined by the circuit characteristics such as area, delay time, power consumption, etc. If the value is not good, it is converted into a gate. Therefore, a logic circuit with excellent characteristics of the synthesized circuit can be guaranteed in any case. However, the area, delay time, power consumption, etc. of the circuit must be calculated every time. Therefore, there is a disadvantage that it takes some time in circuit synthesis. It can also be seen from FIG. 4A that the channel transistor selector that generally operates as NAND logic or logic (or AND logic or OR logic) is transformed into 38 210x297 ^:: Binding ^ __- line (please first (Read the notes on the back and fill in this page) A7 B7 45293 3 V. Description of the invention (36) The circuit characteristics of the CMOS gate will be better. Therefore, if the channel transistor / CMOS coordinated logic circuit is directly formed from the binary decision diagram without calculating the value in this embodiment, it can be expected to be synthesized into a logic circuit with excellent circuit characteristics. In fact, when the channel transistor logic circuit is synthesized from the binary decision diagram of FIG. 24, a circuit such as 囷 27 can be synthesized, and compared with this circuit, the channel transistor / CMOS coordination logic circuit synthesized by this method ( (Fig. 26) The number of transistors is small, and it is synthesized into an excellent retarder circuit. In this way, a channel transistor / CMOS coordination logic circuit with a clever combination of the advantages of the channel transistor selector and the CMOS gate can also be synthesized according to this method. The effect of the invention is learned from the above embodiments. According to the present invention, no matter what kind of logic the logic circuit is connected to, the combination of the advantages of the channel transistor circuit and the CMOS circuit is clever. A logic circuit composed of a CMOS separate logic circuit and a channel transistor alone is a channel transistor / CMOS coordinated logic circuit that is superior in circuit characteristics such as area, delay time, and power consumption. In addition, by adjusting the values defined by the circuit area, delay time, and power consumption, the area and delay of the synthesized channel transistor / CMOS coordination logic circuit can be softly controlled by changing the ratio of the channel transistor selector to the CMOS gate. Circuit characteristics such as time and power consumption. -39-This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling out this page)

Claims (1)

45293 8 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, and applied for patent scope 1.-a kind of logic _ Road $ is a logic including logic with Boolean processing selection logic: χ! Ι ^ Φί series circuit, which It has a lp-type channel electric field effect transistor whose gate is controlled by the first input, and between the first action potential point and the first node, which is connected to the source-drain path; its gate is controlled by the second Controlled by the input, between the first action potential point and the first node, a 2p-type channel electric field effect transistor connected to the source-drain path; its gate is controlled by the first input at the first node Between the fourth node and the In-channel electric field effect transistor sab · body connected to the source-drain path, its gate is controlled by the second input, and it is electrically connected between the fourth node and the second action. The 2n-type channel electric field effect transistor connected to the source-drain path is connected between the points; the gate is controlled by the first node, and the source is connected between the first action potential point and the second node The 3 |) -type channel electric field effect transistor of the drain path; its gate is formed by the first node Controlled between the second node and the second action potential point, a 311-type channel electric field effect transistor connected to the source-drain path; its gate is controlled by the second node, and is turned on in the third round. The 5n-type channel electric field effect transistor that is connected to the 3rd node and is connected to the source electrodeless path; -40- nn n ^^^ 1 »— ^ nn ^ i In ^» Include (Please read the back first Note ^^ Please fill in this page again> This paper size is in accordance with the standard of China's National Standards (CNS) A4 (2 | 〇 × 297) A8 B8 C8 D8 / 15 293 8 VI. Apply for a patent The pole is controlled by the first node, and is connected between the 4th input and the 3rd node between II-n ί 111-I '-1-II n-(please read the precautions on the back before filling this page) The 6η-type channel electric field effect transistor of the source-drain path m »Its gate is controlled by the third node, and is connected between the source-drain path and the j-th output Channel-type field-effect transistor of the first type; its closed pole is controlled by the third node, and between the first output and the second action potential point, the source-drain path is connected. 4η-type channel electric field effect transistor. 2_ The logic circuit described in the first item of the patent application scope, characterized in that the gate is controlled by the output 'between the first action potential point and the third node' A 5n-type channel electric field effect transistor connected to the source-drain path. 3. A logic circuit characterized by including a logic circuit with Boolean processing selection logic, which has: Controlled by 10 inputs and connected to the source-drain path between the 10th action potential point and the 10th node, the 10ρ-type channel electric field effect transistor; The pole is controlled by the 10th input and the 10n-type channel electric field effect transistor which is connected to the source-drain path between the 10th node and the 2nd action potential point; its gate is controlled by the 10th node Control, between the 11th input and the 11th node 'connecting the source-drain path of the 丨 In-type channel electric field effect electric____ -41-CNS A4 ^ (21 ()) < 297 reads) Α8 Β8 C8 D8 4 5 293 8 6. Scope of patent application Crystal, (please read the note on the back before filling in this note) Its gate is controlled by the 10th input, and between the 12th input and the 11th node, the 12η-type groove connected to the source wave path Channel electric field effect transistor; its gate is controlled by node Π, between the first action potential point and node 12, the 15ρ-type channel electric field effect transistor connected to the source drain path; its gate The pole is controlled by the eleventh node, and the source electrode is connected between the twelfth node and the second action potential point; and the 15n-type channel electric field effect transistor of the pole path; its gate is controlled by the second one Controlled by the node, between the first action potential point and the tenth output, a 14p-type channel electric field effect transistor connected to the source drain path; its gate is controlled by the twelfth node at the tenth output And the 13th node, a 14η-type channel electric field effect transistor connected to the source-drain path; the central government bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed that its gate is controlled by the 13th input. Between the action potential point and the 10th output, the source and drain paths are connected. 13ρ-type channel electric-field-effect transistor whose gate is controlled by the 13th input 'between the 13th node and the second action potential point', which is a 13η-type channel-electric-field-effect transistor connected to the source electrode without a potential path . 4. The logic circuit described in item 3 of the scope of the patent application is characterized by -42- The standard of this paper is not applicable to the national standard (CNS) Α4 this grid (2 丨 0X297) 45293 8 A8 B8 C8 D8 6. Scope of patent application " Preparation: its gate is controlled by the 12th node, between the 1st action potential point and the 11th point, the lip-type channel electric field effect connecting the active electrode non-polar channel Transistors. 5. A logic circuit including a logic circuit with Boolean processing selection logic, which includes: its gate is controlled by the 20th input, and is connected between the first action potential point and the 20th node Source-drain channel of the 20p-type channel electric field effect transistor; its gate is controlled by the 21st input, between the first action potential point and the 20th node, connected to the source-drain channel The 21p-type channel electric field effect transistor whose gate is controlled by the 20th input, and between the 20th node and the 24th node, a 22η-type channel electric field effect transistor connected to the source drain channel: The gate is controlled by the 21st input. Between the 24th node and the second action potential point, the 21n-type channel electric field effect transistor connected to the source drain channel is gated by the 22nd input. Control, between the first action potential point and the 22nd node, the 22ρ-type channel electric field effect transistor connected to the source drain channel; its gate is controlled by the 22nd input, and between the 22nd node and the 22nd node 2 between the action potential point, the 22nd source drain channel Type channel electric field effect transistor; -43- _____ This paper ruler is applicable to China Gujia stringing (CNS) A4 size (210X297 male) ^^ 1 ml ^^^ 1 I n I ^ in 1 ^ 1 ^^ ^ 1 ^ ϋ · n ^ i --aJ ^^^ 1 · (please read the note on the back before filling in this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 452938 Α8 ΒΚ C8 D8 Central of the Ministry of Economic Affairs Printed by the Bureau of Shellfish Consumer Cooperative 6. The scope of the patent application is controlled by the 22nd node, and between the 23rd input and the 23rd node, the 23n-type channel electric field connected to the source drain channel Effect transistor; its gate is controlled by the 22nd input, a 24n-type channel electric field effect transistor which is connected to the source-drain path between the 20th node and the 23rd node; its gate is controlled by Controlled at the 23rd node, a 25ρ-type channel electric field effect transistor connected to the source-drain path between the 丨 action potential point and the 20th output; its gate is controlled by the 23rd node, and Between the 20 output and the second action potential point, a 25η-type channel electric field effect transistor connected to the source-drain path6. The logic circuit described in item 5 of the scope of patent application, characterized in that its gate is controlled by the output, and between the first action potential point and the 23rd node, the first 23ρ-type channel electric field effect transistor. 7. The logic circuit according to any one of items 1 to 6 of the scope of patent application, characterized in that the area ratio of the channel transistor selector is 10 to 60%. 8. The logic circuit as described in any one of the id scope of the patent application, characterized in that there are at least unit 1 and unit 2 on the semiconductor substrate: the unit 1 and unit 2 have a substantially rectangular shape The unit 1 is equipped with the first and second ρ-type channel electric field effect transistors' and _ -44- __ This paper size is applicable to China National Standards (CNS) Α4 wash grid (210X297 mm) 1-ij ^^ 1 t ^^ 1 ^^ 1 II ^^ 1 II— (please read the note f on the back and then write 4) 293 45293 8 A8 B8 C8 D8 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Range 1st and 2nd n-type channel electric field effect transistor; The unit 2 is a 4p type channel electric field effect transistor and 4th, 5th and 6n type n field electric field effect transistor; the unit 1 and Unit 2 has two power lines running horizontally; the vertical heights of the units 1 and 2 are substantially equal; and the vertical heights of the power lines of the units 1 and 2 are substantially equal β 9. A method of synthesizing a logic circuit, which is characterized by: A logic function that regulates the logic circuit and expresses a relationship between a group of input variables representing its group of input signals and an output variable representing at least one of its output signals to synthesize the logic circuit, and the computer system executes The steps include: (a) making a binary decision graph from the above logic function; (b) first changing all the nodes in the binary decision graph to 2 input / output / control input channel transistor selector circuits, Make a channel transistor logic circuit; (e) One of the two inputs is fixed to a channel constant selector of logic constant 丨 or 〇, and replaced with a logically equivalent NAND 'n〇r, AND, OR Wait for 01 ^ 05 to close the door and calculate the circuit characteristics of its area, delay time, and power consumption. For example, when the CMOS gate is replaced, the value of the circuit characteristics is closer to the most suitable. Select MH «^^ 1 · = _ ^^ 1 I.-—I — ^ 1-—l · —. (Please read the note on the back before filling this page) -45- 452938 A8 B8 C8 D8 Apply for a patent Replace the rangefinder with a CMOS gate; ( d) Apply the above step (c) to all channel transistor selectors to optimize the specified circuit characteristics; (e) A logic circuit combining the channel transistor circuits and circuits obtained in the above steps As a logic circuit outputter relative to the above-mentioned logic function "10 'The method of synthesizing a logic circuit as described in item 9 of the patent application park, characterized in that the above-defined circuit characteristic value is the most suitable logic circuit. Refers to the logic circuit whose area is the smallest. 11. The method for synthesizing a logic circuit as described in item 9 of the scope of the patent application, characterized in that the above-defined circuit characteristic value is the most suitable logic circuit, which refers to the logic circuit whose delay time is the smallest. 12. The method of synthesizing a logic circuit as described in item 9 of the scope of the patent application, characterized in that the above-defined circuit characteristic value is the most suitable logic circuit, which refers to the logic circuit whose power consumption is the smallest. Printed by the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives ^ r f --- ^-(please read the notes on the back before filling out this page) 13. Logic circuit synthesis as described in item 9 of the scope of patent application The method is characterized in that the above-defined circuit characteristic value is the most suitable logic circuit, and the combination of area, delay time, and power consumption is the most suitable logic circuit. 14 · A method of synthesizing a logic circuit, characterized in that: a computer system is used to synthesize a logic circuit according to the logic circuit to be standardized, a group of input variables representing the group of input signals of the logic circuit and an output variable representing at least one output signal thereof The logical function of the relationship to the -46 paper standard universal Chinese National Standard (CNS) A4 size (210X297 mm) 4 5 2 9 3 8 ll The method of forming the logic circuit, and the steps performed by the computer system include: ^ 1.-1-[It-i I, I I ...... I—, π (Please read the note on the back first $ Item and fill in this page} (a) Make a binary decision graph from the above logical function; (b) In the node of the binary decision graph, among the 2 branches (0 branch,! Branch), only the i branch is fixed At the node of the edit constant 0 or 1, replace it with a logically equivalent CMOS gate such as NOR, AND, OR; and change the other nodes to 2 input / output / control input channel transistor selection (C) A logic circuit that combines the channel transistor circuit and the cMOS circuit obtained in the above steps as the logic circuit output of the above logic function. 15. —A method of synthesizing logic circuits' Its characteristics To: a logic circuit that puts a logic function that can regulate the relationship between input signals and output signals into a computer system, which includes the following steps: (a) make a binary decision diagram from the logic function; Ministry of Economy Printing (b) Transform all the nodes of this binary decision 为 into 2 inputs / outputs / controls. The input channel transistor selector circuit is used to make the channel transistor logic circuit; (c) the channel transistor is delayed Only a part of the circuit is transformed into a logically equivalent CMOS gate to make a CMOS gate logic circuit; (d) a part of the channel transistor logic circuit made in step (b) is replaced with a part made in step (c) Logic Logic Circuit Logic Circuit Output-47- This paper size is applicable to China National Kneading Rate (CNS) A4 specification (2! 0X297 mm) 45293 8 A8 __________ D8 6. Applicants for patents. 16. -Semiconductor device ( The manufacturing method is characterized in that a method of manufacturing a semiconductor by synthesizing a logic circuit that can implement a logic function that regulates the relationship between the input signal and the output signal from a computer system includes the following steps: (a) from The above logic function is used to make a binary decision graph; (b) All nodes of the binary decision graph are transformed into 2 input / output / input controlled channel transistor selector circuits, and Form a channel transistor delayed circuit; (c) Transform only a part of the above-mentioned channel transistor logic circuit into a logically equivalent CMOS gate to form a CMOS gate logic circuit; (d) The step (b) A part of the channel transistor logic circuit is replaced by the logic circuit output of the CMOS logic circuit made in step (c); (e) According to the output logic circuit, a majority mask pattern for generating the logic circuit is created; (f) The plurality of mask patterns are used to manufacture a semiconductor integrated circuit including the above-mentioned logic circuit. I7. A semiconductor integrated circuit device comprising: a one-channel transistor circuit printed by the Ministry of Economic Affairs, the Central Bureau of Standards, and the Industrial Cooperative Consumer Cooperative, which is provided with a first source-drain path between the first and second nodes. 1 electric field effect transistor, and a second electric field effect transistor having a source-drain path between the third and the second nodes; a multi-input CMOS logic circuit that outputs a control signal; the control signal is input to the first 1Electric field effect transistor gate • 48-This paper uses Chinese National Standard (CNS) A4 (2I0X 297 cm) A8 B8 C8 D8 45293 8 6. The scope of patent application is extremely high. The gate is input to the second electric field effect transistor. 18. A semiconductor integrated circuit device comprising: a channel transistor circuit having a first electric field effect transistor having a source-drain path between a first node and a second node; and 2 second electric field effect transistor with source-drain path between nodes; a multi-input CMOS logic circuit; the output of the multi-input CMOS logic circuit is input to the first node; the control signal is input to the first electric field effect The gate of the transistor, and the reverse signal of the control signal is input to the gate of the second electric field effect transistor Zhao. 19. A semiconductor integrated circuit device comprising: a one-channel transistor circuit having a first electric field effect transistor having a source-drain path between a first and a second node, and a third and the second A second electric field effect transistor with a source-to-electrode path between the nodes; an inverting circuit with the second node connected to its input; a multi-input CMOS logic circuit with the output of the inverting circuit connected to at least one of its inputs The control signal is input to the open electrode of the first electric field effect transistor, and the reverse signal of the control k-break is input to the second electric field effect electric lamp body. ^ Leisure pole 020. As the 17th in the scope of patent application The semiconductor integrated circuit device according to any one of items 19 to 19, wherein the reverse output of the control signal is provided by an inverting circuit ~ ———_______- 49 -__ CNS Α4ΜΛ (210X297 ^ «) ^ --- a i -ί .1 ^^^ 1. ^^^ 1 m · ^ — ^ 1 I- ^ (Please read Note-11 ^ on the back before filling out this page) Printed by Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs ^ 02938 π Scope of patent application 11 Produced by Zhengong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs. 21. The semiconductor integrated circuit device according to any one of claims 17 to 19, including: a channel transistor lattice including the above-mentioned channel transistor circuit; a CMOS lattice including the above-mentioned multi-input CMOS logic Circuit; the above-mentioned channel transistor lattice and the above-mentioned C M 0 S lattice are arranged along the power line, and are wide in a direction perpendicular to the above-mentioned power line of the above-mentioned channel crystal lattice, and perpendicular to the above-mentioned power line of the CMOS lattice. The width is equal. 22. —A logic circuit, which is characterized in that: its gate is controlled by the first input, and between the first action potential point and the first node, the source-drain path is connected. Ip-type channel electric field effect transistor; the gate is controlled by the second input, and the second p-type channel electric field effect transistor that is connected to the source-drain path between the first action potential point and the first node Crystal; its gate is controlled by the first input, and an In-channel electric field effect transistor which is connected to the source-drain path between the first node and the fourth node; its gate is controlled by the second input Controlled by node 4 and The 2n-type channel electric field effect transistor connected to the source-drain path between the action potential points; its gate is controlled by the complementary signal of the signal of the first node, and between the third input and the third node 5n-type trench connected to the source-drain path -____ -50- The paper Lecong Suancai Guanjiaxian (CNS) A4 "(21 () > < 297 public love) III 1 I -i I * I ^^ 1. -I I · —1-I (Please read the precautions on the back before filling out this page) 452938 Α8 Β8 C8 D8 夂, patented electric field effect transistor; its gate is made by No. 1 6n-type channel electric field effect transistor that is connected to the source-drain path between the 4th input and the 3rd node controlled by the node: 1st output connected to the 3rd node; located at the 3rd input or 4th An inverting circuit for processing a signal between an input and a first output; the inverting circuit includes a 4p-type channel electric field effect transistor connected to a source drain path at a first operating potential point, and a second operating potential point The 4n-type channel electric field effect transistor connected to the source electrodeless path, the above-mentioned 4p-type channel electric field effect transistor The source and drain paths of the crystal and the 4n-type channel electric field effect transistor are connected in parallel. 23. A logic circuit characterized in that the gate is controlled by the complementary signal of the 10th input signal, The 笫 1 ^ -type channel electric field effect transistor connected to the source-drain path between the ii input and the eleventh node; its gate is controlled by the tenth input signal, and between the twelfth input and the eleventh node Between them, the 12n-type channel electric field effect transistor connected to the source-drain path; India Ce, Bureau of Quasi-Bureau Consumer Cooperatives — ^ 1 — ^ 1 雩 ^^ 1r1 ^ 1 1 ^ 1 1 ^ 1 m 1 ^ 1 (Please read the precautions on the back before filling this page) Connected to the 12th node of the 1st node above; its gate is controlled by the 12th node, at the 1st action potential point and Between the 10th output, a 14ρ-type channel electric field effect transistor connected to the source-drain path; its gate is controlled by the 13th input, and at the 13th node and the 2nd operating circuit -51-paper size Applicable to China Gujia Standard (CNS) A4 specification (2 丨 〇 < 297 mm) Α8 Β8 C8 D8 4.5 2: 9 3 8) The 13n-type channel electric field effect transistor connected to the source-drain path between the patent application sites; an inverting circuit for processing signals between the 11th input or the 12th input and the above 12th node The inverting circuit has a 15p-type channel electric field effect transistor connected to the source-drain path at the first action potential point, and a 15n-type channel connected to the source-drain path at the second action potential point For the electric field effect transistor, the source and drain paths of the 15p-type channel electric field effect transistor and the 15n-type channel electric field effect transistor are connected in parallel. 24. A logic circuit, characterized in that: the gate is controlled by the 20th input, and the 20ρ-type channel electric field connected to the source drain channel between the first action potential point and the 20th node Effect transistor; its gate is controlled by the 21st input, and between the first action potential point and the 20th node, the second lp-type channel electric field effect transistor connected to the source drain channel; its gate It is controlled by the 20th input. Between the 20th and 24th nodes, the 22η-type channel electric field effect transistor connected to the source-drain channel; its gate is controlled by the 21st input. Between the 24 node and the second action potential point, the gate of the 2U-type channel electric field effect transistor connected to the source-drain channel is controlled by the complementary signal of the 22nd input. Between the nodes, the 23n-type channel connected to the source-drain channel -52- This paper size is applicable to China's national sample rate < CNS Α4 size (210 × 297 mm) (Please read the notes on the back before filling (This page) _Oxygen 45293 8 A8 B8 C8 D8 VI. Patent application electric field effect transistor; its gate is controlled by the 22nd input, and between the 20th node and the 23rd node, it is connected to the source drain channel. 24n-type channel electric field effect transistor; an inverting circuit for processing signals between the 23rd input and the 20th output; the inverting circuit has a 25ρ-type trench connected to the source drain path at the first action potential point Channel electric field effect transistor, and the 25n-type channel electric field effect transistor connected to the source-drain path at the second action potential point, the aforementioned 25ρ-type channel electric field effect transistor and the n-channel electric field effect transistor The source and drain paths are in parallel: Λ: ~ •, mountain ”f f-^^ 1 ^^ 1 tf.:-= I —I ^^ 1 ^^ 1 1 I (Please read the precautions on the back first (Fill in this page again) Printed by the Central Government Bureau of the Ministry of Economic Affairs, Mekong Consumer Cooperatives -53- This paper size is applicable to the Chinese National Standard (CNS) A4 standard (210X297 mm)