JP2000163459A - Method for constituting semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To compose a pass transistor logic circuit which is faster and has a smaller chip area and lower power consumption than a pass transistor logic circuit obtained by mapping from a mere binary decision tree. SOLUTION: The method for constituting a pass transistor logic circuit includes a step for logic composition using CMOS logic composing algorithm, a step for generating binary decision trees each having a variable order from the result of the logic composition in accordance with specified constraints, and a step for obtaining a plurality of pass transistor logic circuits each including >=1 pass transistor by mapping the binary decision trees.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a circuit configuration method for a semiconductor integrated circuit, and more particularly to a circuit configuration method for a pass transistor logic circuit.

[0002]

2. Description of the Related Art A pass transistor logic circuit has attracted attention as a circuit system capable of realizing higher speed, lower power consumption and smaller chip area than conventional CMOS static logic circuits. For articles on pass transistor logic circuits, see, for example, Kuroda and Sakurai, "Low-Power, High-Speed, Post-CMOS Logic with Small Chip Area and Three Times Begins to Spread," Low-Power LSI Technical White Paper-Challenge to 1 milliwatt- 98-104, Nikkei BP, 1994.

However, the logic synthesis method of the pass transistor logic circuit is significantly different from a conventional CMOS static logic circuit. For this reason, various new logic synthesis techniques have been reported for pass transistor logic circuits. Among them, a logic synthesis method using a decision tree is known as a logic synthesis method applicable to a large-scale circuit. In particular, a binary decision tree (Binary Decisio
n Diagram, hereinafter referred to as "BDD". ) Is known.

[0004] References relating to BDD include S.D. Min
ato et al., "Shared Binary Decision Diagram with Att"
ributed Edges for Efficient Boolean Function Manip
ulation ", In Proc. ACM / IEEE DAC., pp. 52-57, 1
990 years. References relating to a logic synthesis method using BDD include K.K. Yano et al., "Top-down pass
-transistor logic design ", IEEE J. Solid-State Cir
cuits, Vol. 31, No. 6, pages 792-803,
There are June 1996 and JP-A-7-168874.

In the logic synthesis method based on BDD, a logic function to be realized as a pass transistor logic circuit is represented by a graph in BDD, and each node of the BDD is replaced by a pair of pass transistors (pair) whose inputs to gates are complementary. This is a technique for realizing a pass transistor logic circuit. The pass transistors to be replaced are two n
MOS, two pMOS, two CMOS transmission gates,
There are various combinations such as a pair of nMOS and pMOS. Of these, only two nMOs are actually used
An S pass transistor and two CMOS transmission gates.

A pass transistor logic circuit obtained by replacing a logic function is a pass transistor or a CM.
The OS transmission gate is connected in series. for that reason,
A buffer (inverter) for signal level recovery is inserted into the pass transistor logic circuit as needed.

In general, in order to obtain a compact pass transistor logic circuit, it is necessary to generate a compact BDD. It is known that the size of BDD (the number of nodes in the graph) greatly affects the number of input variables called a variable order. Here, finding the optimal variable order is known as a difficult problem.
It is said that the variable level is the upper limit (Sawada et al., “Minimization of Binary Decision Diagram Representing Logical Function”, IEICE Transactions, Vol. J76-DI, No. 2, 63.
Pp. 71, February 1993). However, in an actual circuit, it is necessary to handle more variables, and from that point, it is not always feasible to always obtain the minimum value with a normal BDD.

On the other hand, Y. Sasaki et al., "Multi-Level
Pass-Transistor Logic for Low-power ULSIs ", In Pr
oc. IEEE Symp. on Low Power Elec., pp. 14-15,
Multi-Level Pass-Transistor Logic described in 1995 is BD
When technology mapping of cells is performed on the circuit synthesized by D, the same cell having the same signal is shared, and then multi-stage processing is performed. The multi-level BDD can reduce the number of nodes and the number of circuit stages as compared with the normal BDD. However,
Since this targets only a special cell called a Y cell, the unit of multistage is a maximum of two stages, and it is difficult to obtain a great effect.

[0009]

The delay time of a pass transistor logic circuit represented by multi-stage series connection of pass transistors is two times smaller than the number of circuit stages due to rounding of a propagating waveform or the like.
It is proportional to the power. Therefore, it is impossible to synthesize a realistic pass transistor logic circuit for a multivariable circuit by the conventional technology. Even in a circuit that adopts a method of inserting a buffer (inverter) for every fixed number of stages, the absolute lower limit of the delay time is determined by the number of circuit stages because the delay time is proportional to the number of circuit stages. Therefore, the speed of the logic circuit cannot be increased by the configuration method of the pass transistor logic circuit by simply mapping from the decision tree including BDD, which has been used as the conventional technology.

The operating speed of the pass transistor logic circuit is affected by the number of fan-outs from input to output in addition to the maximum number of stages. When a logic function is represented by a single BDD and mapped to a pass transistor logic circuit as in the past, the fan-out on the path increases as the minimum BDD is approached, and wiring capacitance has a serious effect on delay. give.

Further, in order to reduce the area of the pass transistor logic circuit, it is practically difficult to determine a variable order that can form the minimum BDD. Further, even if a minimum BDD can be configured by spending a huge amount of calculation time, a circuit obtained by mapping the minimum BDD cannot be said to be the best circuit including the layout.

In a circuit simply synthesized from BDD, the gate inputs of the pass transistors are all signal lines and their inverted signals. In this case, twice as many signal lines (positive logic and negative logic) as the number of variables are routed over the entire chip, so that the wiring area becomes large.

In order to solve the above-mentioned problem, the present invention provides a BD
An object of the present invention is to synthesize a pass transistor logic circuit with a higher speed, a smaller chip area, and lower power consumption than a pass transistor logic circuit obtained by mapping from D.

[0014]

SUMMARY OF THE INVENTION A method according to the present invention is a method for constructing a pass transistor logic circuit.
Performing logic synthesis using an OS logic synthesis algorithm; generating a plurality of binary decision trees each having a variable order from a result of the logic synthesis according to a predetermined constraint; Mapping the tree to obtain a plurality of pass transistor logic circuits, each including one or more pass transistors, thereby achieving said object.

[0015] The step of generating the binary decision tree includes the step of selecting whether to divide into a plurality of binary decision trees or to construct a single binary decision tree according to the constraint condition. Generating the binary decision tree accordingly.

[0016] The variable order of each of the plurality of binary decision trees may be one or more, and the plurality of binary decision trees may independently have the variable order.
It may be possible to share part of the variable order.

By connecting an output of one of the plurality of pass transistor logic circuits to a gate input of the pass transistor included in another of the plurality of pass transistor logic circuits, The method may further include assembling the pass transistor logic circuit.

The step of combining the plurality of pass transistor logic circuits may include a step of inserting a buffer circuit into a wiring connected to a gate input of the pass transistor.

A semiconductor integrated circuit according to the present invention includes a pass transistor logic circuit constructed by the above method, thereby achieving the above object.

The operation will be described below.

According to the present invention, a plurality of binary decision trees each having a variable order are generated from a result of logic synthesis according to a predetermined constraint condition, thereby obtaining a binary decision tree from a single binary decision tree. A circuit with higher speed, smaller chip area, and lower power consumption than the pass transistor logic circuit can be obtained.

In addition, the step of generating a binary decision tree includes:
Reduce the number of pass transistor logic circuits obtained by mapping a binary decision tree by including the step of choosing between splitting into multiple binary decision trees or building a single binary decision tree according to constraints be able to.

Further, each of the plurality of binary decision trees has at least one kind of variable order, and the plurality of binary decision trees can independently have the variable order, and share a part of the variable order. This makes it possible to obtain a compact binary decision tree with a small number of variables.

Further, one output of the plurality of pass transistor logic circuits is connected to a gate input of a pass transistor included in another one of the plurality of pass transistor logic circuits, and a plurality of pass transistor logic circuits are connected. By combining the circuits, a single pass transistor logic circuit can be obtained from a plurality of binary decision trees.

Further, by inserting a buffer circuit into a wiring connected to the gate input of the pass transistor, the voltage level of a signal transmitted in the pass transistor logic circuit can be recovered.

Further, since the semiconductor integrated circuit includes the pass transistor logic circuit constructed by the above-described method, it is possible to achieve high speed, small chip area, and low power consumption.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention utilizes the output or intermediate state of a logic synthesis process when constructing a pass transistor logic circuit configured by mapping from a BDD, thereby reducing the conventional simple BDD. An object of the present invention is to provide a circuit configuration method capable of realizing a circuit with lower power consumption, higher speed, and smaller chip area than a pass transistor logic circuit obtained by mapping.

First, the outline of the circuit configuration method of the present invention will be described.

First, CMOS logic synthesis processing is performed on a given logical expression by computer processing. Extracting elements that may be configured independently in the state of a synthesized circuit output or in the middle of synthesis, and constructing a function as a separate BDD based on constraints and cost for those parts, or A part that should be constructed as one BDD is selected. At this time, there is no problem if the order of the variables of the BDD is the same or different between the functions. In this way, what was conventionally expressed as a single BDD is expressed as one or more BDDs and mapped to a pass transistor logic circuit.

Finally, the BDDs of the logical functions divided under certain constraints and costs are combined into one. This processing is performed by adding a variable treated as an intermediate variable to the gate input of the node of the BDD labeled with another BDD.
Is processed by connecting the output of. When the output of a certain pass transistor logic circuit is input to the gate of another pass transistor, the original signal and its inverted signal using one inverter are used. However, in this case, a large through current occurs in the inverter due to the wiring capacitance, and therefore, a circuit using two inverters is used.

Next, a circuit design flow according to the circuit configuration method of the present invention will be described.

FIG. 1 shows a design flow of a pass transistor logic circuit according to the present invention.

First, a designer describes the logic of a target circuit. HDL is currently the mainstream language used for logic description.

Next, using the described logic as an input file, the logic is synthesized using a normal CMOS logic synthesis tool.

Next, a divided BDD is generated from the result of synthesis by the CMOS logic synthesis tool in consideration of constraints and cost functions (objective function, evaluation function). Divided B
The generation of the DD is performed according to the following procedure. Elements that can be configured independently are extracted from a circuit that has already been combined or a circuit that is being combined. Based on the extracted elements, based on the above-described constraints and costs, a part where a function is constructed as a different BDD and a part where a function is constructed as a single BDD are selected. At the time of selection, the variable order of the BDD may be the same or different between the functions.

Next, the generated plurality of divided BDDs
Are respectively mapped to pass transistor logic circuits. Further, the output of each pass transistor logic circuit corresponding to the divided BDD is connected to the gate input of another pass transistor logic circuit. By repeating such connection of the pass transistor logic circuit, the entire circuit is put together.

As a result, a small area,
A low power consumption and high speed pass transistor logic circuit is generated.

An embodiment of the present invention will be described below with reference to FIGS.

FIG. 2 shows a configuration of a pass transistor logic circuit using BDD by a conventional method.

For example, consider the case where the logical formula F = abcd + abef + abfg + hij + xyz (1) is synthesized.

According to the conventional method, logic synthesis for a CMOS logic circuit is performed by computer processing from a target logical equation. For example, when the above-described logical expression (1) is subjected to a process called factoring, which is one of the CMOS multi-stage logic synthesis techniques, the following output is obtained.

F = ab (cd + (e + g) f) + hij + xyz (2) FIG. 2A shows the function (2) expressed by a single BDD. According to the conventional method, logic synthesis is performed by mapping a single BDD expressing the entire logic function to a pass transistor logic circuit.

FIG. 2 (b) shows the BD shown in FIG. 2 (a).
The result of mapping D to the pass transistor logic circuit is shown. In FIG. 2B, the pass transistor logic circuit is configured by an nMOS transistor.

In the circuit shown in FIG. 2B, F is an output of a function. One of the signals to each gate of the pair of nMOS transistors constituting the circuit has a positive logic and the other has a negative logic. For example, x is input to one of the nMOS transistor pairs, and xb is input to the other. Where xb
Is the inverter output of x.

As described above, according to the conventional configuration method of the pass transistor logic circuit, a single BDD is constructed from the logical expression subjected to the factoring process, and the circuit is configured by mapping the single BDD. On the other hand, according to the method of the present invention, a plurality of BDDs are calculated from the logical expression subjected to the factoring process in consideration of predetermined constraints and costs.
And construct a pass transistor logic circuit from the plurality of BDDs. Here, the constraint means, for example, how many nsec. It refers to conditions such as the following design. In addition, the cost here refers to conditions relating to, for example, a chip area and power consumption.

FIG. 3 shows a configuration of a pass transistor logic circuit using BDD according to the method of the present invention.

As in the case shown in FIG. 2, consider the case where the logical expression (1) F = abcd + abef + abfg + hij + xyz is synthesized. First, F (ab) (cd + (e + g) f) + hij + xyz is obtained from the formula (1) by the factoring process.

Next, a BDD is constructed from the logical expression (2) in consideration of predetermined restrictions and costs. The following is the logical expression (2)
Will be described below.

First, ab (cd + (e + g) f) + hi
From j + xyz, based on a given constraint, a single BDD
Is constructed or divided into a plurality of BDDs. For example, ab (cd + (e + g) f) + hij + x
When a single predetermined BDD is constructed from yz, if it is determined that the constraint on the delay time is not satisfied, a plurality of B
The choice to split into DDs is made.

Next, in consideration of the restrictions and the cost, ab
Divide (cd + (e + g) f) + hij + xyz.
For example, ab (cd + (e + g) f) + hij + xyz
Is divided into ab (cd + (e + g) f) and hij + xyz.

Next, a selection is made as to whether a single BDD is constructed or divided into a plurality of BDDs from each of the equations obtained by the division. For example, ab (cd + (e + g)
If f) and hij + xyz satisfy predetermined constraints and costs, respectively, no further division is performed. If a predetermined BDD is not satisfied when a single BDD is constructed from the divided equations, the division is repeated until the BDDs are satisfied.

The BDD thus obtained is mapped to a pass transistor logic circuit. FIG. 3A shows that the logical expression (1) is expressed as ab (cd + (e + g) f) and hij + xyz.
Are represented by two BDDs respectively corresponding to FIG. 3B shows a result of mapping each of the two BDDs shown in FIG. 3A to a pass transistor logic circuit. In FIG. 3B,
The pass transistor logic circuit is composed of nMOS transistors.

When a plurality of pass transistor logic circuits are obtained by mapping a plurality of BDDs, it is necessary to connect a plurality of circuits. In FIG. 3B, a portion N is a pair of pass transistors newly provided for connecting the circuits obtained from the two BDDs. A portion for generating a gate input signal of a transistor of another function from an output of a certain function [the hatched portion in FIG.
(B) N portion] can be realized by generating an inverted signal by an inverter.

The number of stages of the pass transistor logic circuit constructed by the conventional method shown in FIG. 3 is g, e, d,
There are 12 stages of c, b, a, j, i, h, z, y, x. On the other hand, the number of stages of the pass transistor logic circuit obtained by the present invention is g, e, d, c, b, a and N
And 7 sections. As described above, according to the present invention, the number of stages of the pass transistor logic circuit can be reduced by almost half.

FIG. 4 shows a circuit for connecting the output of one pass transistor logic circuit to the gate of a pass transistor of another pass transistor logic circuit.

The circuit shown in FIG. 4A is a circuit using one inverter, and the circuit shown in FIG. 4B is a circuit using two inverters. If the wiring length of the signal line input to the gate is long, the delay time,
It is effective to use two inverters in order to eliminate the increase in the through current due to the rounding of the waveform.

As described above, instead of configuring the pass transistor logic circuit from a single BDD as in the prior art, a
By dividing into D, the number of stages of the pass transistor logic circuit can be greatly reduced.

In the above embodiment, the nMO
An example in which an S transistor is used has been described.
The present invention can be similarly applied to a configuration using another transistor.

[0059]

According to the present invention, at least the following effects can be obtained.

First, the operation speed of the pass transistor logic circuit can be increased. That is, the delay time can be reduced by reducing the maximum number of stages for an arbitrary circuit. In addition, by expressing a circuit with a plurality of BDDs, the number of fanouts can be reduced and the effect of wiring capacitance on delay can be reduced. Furthermore, by selecting the BDD configuration as a compact part and grouping it in an area in the chip for each unit,
The wiring length can be reduced by reducing the wiring layout, and the floating capacitance of the wiring can be reduced.

Next, the area of the chip on which the pass transistor logic circuit is mounted can be reduced. That is, the wiring area can be reduced by reducing the wiring length and the wiring length of the circuit. In addition, by expressing a circuit with a plurality of BDDs, the number of nodes of the BDD can be greatly reduced as compared with expressing a circuit with a single BDD. Thus, the number of transistors included in the circuit can be reduced, and the circuit area can be reduced.
Further, the output of the function represented by a certain BDD is
By using the D input for the gate, the locality of the wiring can be increased and the wiring area can be reduced as compared with the logic synthesis using a single BDD in which only a normal signal line is input to the gate.

Finally, the power consumption of the chip on which the pass transistor logic circuit is mounted can be reduced. This is realized because the load capacity can be reduced by reducing the number of transistors included in the circuit and the wiring region. Further, as the chip area decreases, the wiring length becomes shorter even over the entire chip, which also leads to reduction in power consumption.

[Brief description of the drawings]

FIG. 1 is a diagram showing a design flow of a circuit according to the present invention.

FIG. 2 is a diagram showing a configuration of a pass transistor logic circuit using BDD according to a conventional method.

FIG. 3 is a diagram showing a configuration of a pass transistor logic circuit using BDD according to the method of the present invention.

FIG. 4 is a diagram showing a circuit that connects an output of a certain pass transistor logic circuit to a gate of a pass transistor of another pass transistor logic circuit;

[Explanation of symbols]

a, b, c, d, e, f, g, h, i, j, x, y, z
Variable input ab, bb, cb, db, eb, fb, gb, hb, i
b, jb, xb, yb, zb Inverter input F output G Gate input Gnd Ground N Pass transistor pair

Claims (6)

[Claims] 1. A method for configuring a pass transistor logic circuit, comprising: performing logic synthesis using a CMOS logic synthesis algorithm; and determining a variable order from a result of the logic synthesis according to a predetermined constraint condition. A method comprising: generating a plurality of binary decision trees having: and mapping the plurality of binary decision trees to obtain a plurality of pass transistor logic circuits each including one or more pass transistors. 2. The step of generating the binary decision tree includes: selecting whether to divide into a plurality of binary decision trees or construct a single binary decision tree according to the constraint condition; Generating the binary decision tree in response to a result. 3. The variable order of each of the plurality of binary decision trees is one or more, and the plurality of binary decision trees can independently have the variable order. It is possible to share some,
The method of claim 1. 4. The method according to claim 1, wherein an output of one of the plurality of pass transistor logic circuits is connected to a gate input of the pass transistor included in another of the plurality of pass transistor logic circuits. The method of claim 1, further comprising the step of combining a plurality of pass transistor logic circuits. 5. The method of claim 4, wherein the step of combining the plurality of pass transistor logic circuits includes the step of inserting a buffer circuit into a wire connected to a gate input of the pass transistor. 6. A semiconductor integrated circuit including a pass transistor logic circuit configured by the method according to claim 1.