JP3625973B2 - Logic circuit, logic circuit synthesis method, semiconductor device manufacturing method, and semiconductor integrated circuit device - Google Patents

Description

図５のａでは、本発明のパストランジスタ／ＣＭＯＳ協調論理回路では、インバータＩ５０、パストランジスタセレクタＳ５０、ＣＭＯＳゲートＧ５０から構成される回路になる。一方、従来のパストランジスタ論理回路では、インバータＩ５０、Ｉ５１、パストランジスタセレクタＳ５０、Ｓ５１が必要である。また、ＣＭＯＳ論理回路では、インバータＩ５２、Ｉ５４、ＣＭＯＳゲートＧ５０〜Ｇ５３が必要になる。図５のａに示されるように、従来のパストランジスタ論理回路では、パストランジスタ回路に適していないＮＡＮＤ論理、ＮＯＲ論理もパストランジスタ回路で組まなければならない（Ｓ５１）。また、従来のＣＭＯＳ論理回路では、ＣＭＯＳ回路で構成するのに適していないセレクタ論理もＣＭＯＳ回路で構成しなければならない（Ｇ５１〜Ｇ５３）。これに対し、本発明のパストランジスタ／ＣＭＯＳ協調論理回路では、与えられた論理の中で、セレクタ論理に相当する部分はセレクタ論理に適したパストランジスタセレクタ（Ｓ５０）で回路を組み、それ以外のＮＡＮＤ、ＮＯＲ論理部分はそれに適したＣＭＯＳゲート（Ｇ５０）で回路を組むことが可能である。このように本発明のストランジスタ／ＣＭＯＳ協調論理回路は、セレクタ論理とＮＡＮＤ論理、ＮＯＲ論理（ＡＮＤ論理あるいはＯＲ論理）が組み合わさった論理をコンパクトな回路で実現できる。このため、パストランジスタ論理回路ではトランジスタが１４個、ＣＭＯＳ論理回路ではトランジスタが２０個必要であるのに対し、本発明のパストランジスタ／ＣＭＯＳ協調論理回路ではトランジスタ１１個で目的の論理機能を実現でき、小面積、低消費電力の性能の優れた回路であることがわかる。さらに、本発明のパストランジスタ／ＣＭＯＳ協調論理回路では、パストランジスタ論理回路のセレクタＳ５１、インバータＩ５１に相当する部分を一つのＣＭＯＳゲートＧ５０に縮約することができるため、パストランジスタ論理回路で、セレクタＳ５１内のインバータ→セレクタＳ５１→バッファ用インバータＩ５１でかかる遅延時間を、ＣＭＯＳゲートＧ５０だけの遅延時間に短縮することができる。さらに、パストランジスタ論理回路のセレクタＳ５１内の遅延時間の遅いインバータを経路から取り除くことができるので、本発明のパストランジスタ／ＣＭＯＳ協調論理回路は、パストランジスタ論理回路に比べて遅延時間を大幅に小さくすることができる。また、ＣＭＯＳ論理回路と比較しても、ＣＭＯＳ論理回路のＧ５１〜Ｇ５３、Ｉ５２、Ｉ５４の部分の経路を、本発明のパストランジスタ／ＣＭＯＳ協調論理回路ではＳ５０、Ｉ５０に短縮できるので、本発明のパストランジスタ／ＣＭＯＳ協調論理回路の方が遅延時間が小さい。この図５のａに示す本発明のパストランジスタ／ＣＭＯＳ協調論理回路のレイアウト例を図６に示す。この図６では、セル１がＣＭＯＳ回路のＮＡＮＤゲート（Ｇ５０）に相当し、セル２がパストランジスタセレクタ（Ｓ５０）に相当する。この図６に示すように、セル１の高さｈ１とセル２の高さｈ４、さらに、セル１の電源線（ＶＤＤおよびＧＮＤ）の幅であるｈ２およびｈ３と、セル２の電源線（ＶＤＤおよびＧＮＤ）の幅であるｈ５およびｈ６を等しくすることにより、はじめて、パストランジスタ回路とＣＭＯＳ回路を一つの回路に組み合わせた論理回路を実際に製作することが可能になる。このことは以下の実施例でも同様である。
【００２８】
また、図５のｂの論理では、本発明のパストランジスタ／ＣＭＯＳ協調論理回路では、インバータＩ６０、パストランジスタセレクタＳ６０、ＣＭＯＳゲートＧ６０から構成されるトランジスタ１１個で目的の論理機能を持った回路を構成できる。一方、パストランジスタ論理回路では、インバータＩ６０およびＩ６１、パストランジスタセレクタＳ６０、Ｓ６１が必要であり、トランジスタが１４個必要である。また、ＣＭＯＳ論理回路では、インバータＩ６２、Ｉ６４、ＣＭＯＳゲートＧ６０〜Ｇ６３が必要で、トランジスタが２０個必要である。つまり、この場合も、本発明のパストランジスタ／ＣＭＯＳ協調論理回路が一番性能が良いことがわかる。また、遅延時間についても、本発明のパストランジスタ／ＣＭＯＳ協調論理回路では、パストランジスタ論理回路のセレクタＳ６１、インバータＩ６１に相当する部分を一つのＣＭＯＳゲートＧ６０に縮約できるため、パストランジスタ論理回路のセレクタＳ６１内のインバータ→セレクタＳ６１→バッファ用インバータＩ６１でかかる遅延時間を、ＣＭＯＳゲートＧ５０だけの遅延時間に短縮することができ、特に、セレクタＳ６１内の遅いインバータを取り除くことができるので、パストランジスタ論理回路よりも遅延時間を大幅に小さくすることができる。また、ＣＭＯＳ論理回路と比較しても、ＣＭＯＳ論理回路のＧ６１〜Ｇ６３、Ｉ６２、Ｉ６４の部分の経路を、本発明のパストランジスタ／ＣＭＯＳ協調論理回路ではＳ６０、Ｉ６０に短縮できるので、本発明のパストランジスタ／ＣＭＯＳ協調論理回路の方が遅延時間が小さい。
【００２９】
また、図５のｃでは、本発明のパストランジスタ／ＣＭＯＳ協調論理回路では、インバータＩ７０、パストランジスタセレクタＳ７０、ＣＭＯＳゲートＧ７０から構成されるトランジスタ１１個で目的の論理機能を持った回路を構成できる。一方、パストランジスタ論理回路では、インバータＩ７０およびＩ７１、パストランジスタセレクタＳ７０、Ｓ７１が必要であり、トランジスタが１４個必要である。また、ＣＭＯＳ論理回路では、インバータＩ７２、Ｉ７４、ＣＭＯＳゲートＧ７０〜Ｇ７３が必要で、トランジスタが２０個必要である。つまり、この場合も、本発明のパストランジスタ／ＣＭＯＳ協調論理回路が一番性能が良いことがわかる。遅延時間についても図５のａ、ｂと同様の理由で本発明のパストランジスタ／ＣＭＯＳ協調論理回路が一番小さい。
【００３０】
＜実施例２＞
以上の実施例では簡単な論理を例にとって本発明のパストランジスタ／ＣＭＯＳ協調論理回路を説明した。本実施例では、より複雑な論理に対して、面積、遅延時間、消費電力等の回路特性の優れた高性能なパストランジスタ／ＣＭＯＳ協調論理回路を、図７および図８に示す計算機システムにより自動合成する方法を説明する。
【００３１】
（１）システムの全体構成
図８において、設計者は目的とする半導体集積回路の論理機能の仕様を記述した論理回路仕様１０を入力する。論理回路仕様１０には回路の論理機能を記述した論理関数が記述されている。その他に、その回路の面積、遅延時間、消費電力等の回路特性の目標値と、さらにどの回路特性を優先させるかといった情報も記述されている。本実施例に特有のパストランジスタ／ＣＭＯＳ協調論理回路合成プログラム１００は、論理回路仕様１０に記載されている情報から、ライブラリ１１を参照して、面積、遅延時間、消費電力等の回路特性の目標値を満たすように、論理回路仕様１０の論理機能を持ったパストランジスタ／ＣＭＯＳ協調論理回路１２を合成する。自動レイアウトプログラム１６０はライブラリ１１を参照して、この論理回路に最適なレイアウトを決定し、レイアウトデータ２０を作成する。マスクデータ作成プログラム１７０は、レイアウトデータ２０に従って、上記合成された論理回路を半導体集積回路技術を使用して生成するための複数のマスクパターンを決め、それらのマスクパターンを表すマスクデータ２１を生成する。半導体製造装置１８０は、マスクデータ２１を用いて目的の論理機能を持った半導体集積回路を製造する。１００、１６０、１７０の各プログラムは、それぞれに割り当てられた異なる計算機上で実行される。もちろん、これらのプログラムを同じ計算機上で実行させることもできる。
【００３２】
図７は、本発明のパストランジスタ／ＣＭＯＳ協調論理回路合成プログラム１００の概略構造とこのプログラムを実行するための計算機システムを示す。この計算機システムは、入力装置、例えば、キーボード１、中央処理装置（ＣＰＵ）２、表示装置（ＣＲＴ）３、磁気テープ装置４および論理回路合成プログラム１００を格納する磁気ディスク装置５からなる。プログラム１００は、二分決定グラフ作成ルーチン１１０、パストランジスタセレクタマッピングルーチン１２０、ＣＭＯＳゲート割り当てルーチン１３０から構成される。このプログラムは、設計者がキーボード１から指示を与えることにより、磁気ディスク装置５からＣＰＵ２にロードされて、実行される。プログラム１００により合成されたパストランジスタ／ＣＭＯＳ協調論理回路はＣＲＴ３上に表示され、磁気テープ装置４等を経由して図８の自動レイアウトプログラム１６０に渡される。
【００３３】
本実施例では、二分決定グラフを作って、パストランジスタセレクタをマッピングして合成したパストランジスタ回路の中で、ＣＭＯＳ回路に変更した方が性能が良くなる部分を見つけ出してその部分をＣＭＯＳ回路で組み直して、従来のパストランジスタ単独の論理回路あるいはＣＭＯＳ単独の論理回路より性能の優れたパストランジスタ／ＣＭＯＳ協調論理回路を合成する点に特徴がある。具体的には、２本の入力のいずれか一方の入力が、論理定数１あるいは０に固定され、ＮＡＮＤ論理あるいはＮＯＲ論理（ＡＮＤ論理あるいはＯＲ論理）として動作しているパストランジスタセレクタを、論理的に等価なＮＡＮＤ、ＮＯＲ等のＣＭＯＳゲートに置き換え、面積、遅延時間、消費電力等の回路特性の値を計算して、ＣＭＯＳゲートに置き換えた方が所定の回路特性の値がより最適に近ければ、パストランジスタセレクタをＣＭＯＳゲートに置き換えるという操作により、ＣＭＯＳ回路にした方が性能が良くなる部分をＣＭＯＳ回路で組み直す。以下、次の論理関数を例にして本実施例のそれぞれのルーチンについて説明する。
【００３４】
ｏｕｔ１ ＝ Ｂ ＊ Ａ ＋ Ｃ ＊ Ａ ＋ （Ｉ ＊ Ｆ ＋ Ｄ） ＊ （Ｄ ＋ （Ｈ ＋ Ｅ） ＊ （Ｅ ＋ Ｇ））
ｏｕｔ２ ＝ Ｂ ＋ （（Ｉ ＊ Ｆ ＋ Ｄ） ＊ （Ｄ ＋ （Ｈ ＋ Ｅ） ＊ （Ｅ ＋ Ｇ）））
なお、この論理関数から、従来からある既存の公知の方法でＣＭＯＳ論理回路を合成すると、図１０のＧ１００〜Ｇ１１１から構成される回路が得られる。
【００３５】
（２）二分決定グラフ作成ルーチン１１０
このルーチン１１０は、論理回路仕様１０から二分決定グラフを生成する。論理回路仕様１０には、合成する論理回路の入力信号と出力信号に対応する入力変数と出力変数と、その回路の論理機能を表した論理関数が含まれる。
【００３６】
上に示した論理関数から二分決定グラフを作成すると、図１１のノードＮ１００〜Ｎ１１１から構成されるグラフが作成される。この図１１の多段二分決定グラフでは、ノードＮ１０４〜Ｎ１０９を共通化して括り出して多段化することにより、普通の二分決定グラフよりノード数を削減している。なお、ノード数の少ないサイズの小さい二分決定グラフを作成するためには、グラフを作成する際の入力変数順序が大変重要な意味を持つが、この入力変数順序は既存の公知の二分決定グラフ作成ツールを使用して決定できる。
【００３７】
（３）パストランジスタセレクタマッピングルーチン１２０
このルーチンは、図１２のマッピングルールに従い、二分決定グラフ作成ルーチン１１０で作成された二分決定グラフの各々のノードを、ノードの種類に応じてパストランジスタセレクタあるいはインバータ等にマッピングしてパストランジスタ論理回路を生成する。さらに、必要に応じてバッファ用のインバータを挿入する。
【００３８】
図１２のａに示すノードＮ１のように、１枝および０枝がつながっている先が論理定数１、０ではない場合には、ｎチャネル電界効果トランジスタＴ０，Ｔ１およびインバータＩ０から構成される２入力１出力のパストランジスタセレクタＳ０を対応させる。このパストランジスタセレクタＳ０の制御入力には、二分決定グラフのノードに対応する入力変数Ａを割り当て、その制御入力が１の時に選択される入力ｉｎ１には、１枝につながっているノードの出力を割り当てる。制御入力が０の時に選択される入力ｉｎ０には、０枝につながっているノードの出力を割り当てる。
【００３９】
図１２のｂのノードＮ２のように、１枝が論理定数１に接続され、０枝が論理定数０に接続されている場合には、このノードの出力は、そのノードの入力変数Ａが１の時は１が出力され、また入力変数Ａが０の時は０が出力される。つまり、入力信号Ａをそのまま後段の回路に接続すればよい。
【００４０】
また、図１２のｃに示すノードＮ３のように、１枝が論理定数０に接続され、０枝が論理定数１に接続されている場合には、このノードの出力は、ノードの入力変数Ａが１の時は０が出力され、入力変数Ａが０の時は１が出力される。つまり、入力信号Ａをインバータによって反転させ後段の回路に接続すればよい。
【００４１】
このようにマッピングすることにより二分決定グラフと同じ論理機能を持ったパストランジスタ論理回路が合成される。図１１の二分決定グラフからパストランジスタ論理回路を合成すると、図１３に示す、パストランジスタセレクタＳ１００〜Ｓ１０５、インバータＩ１００〜Ｉ１０５から構成されるパストランジスタ論理回路が合成される。この回路で、Ｉ１００、Ｉ１０３、Ｉ１０５はバッファ用インバータである。図１１の二分決定グラフでは、ノードＮ１０２、Ｎ１０３、Ｎ１０９が図１２のマッピングルールのｂに該当し、ノードＮ１０６、Ｎ１０７、Ｎ１１１は図１２のｃに該当する。その他のノードは、図１２のａに該当する。
【００４２】
（４）ＣＭＯＳゲート割り当てルーチン１３０
このルーチンでは、パストランジスタセレクタマッピングルーチン１２０で生成されたパストランジスタ論理回路の中で、ＣＭＯＳゲートで組み直した方が面積、遅延時間、消費電力等の回路特性が良くなると考えられる、ＮＡＮＤ論理、ＮＯＲ論理（あるいはＡＮＤ論理、ＯＲ論理）として動作しているパストランジスタセレクタをＣＭＯＳゲートで組み直す。
【００４３】
まず、パストランジスタ論理回路のうち、図１４のａ〜ｄの変換パターンに該当するパストランジスタセレクタを選択する。この図１４のａ〜ｄに示すパストランジスタセレクタは、２本の入力のいずれか一方の入力がＶＤＤあるいはＧＮＤ電位に固定されて、つまり論理定数１あるいは論理定数０に固定されている、ＮＡＮＤ論理、ＮＯＲ論理（あるいはＡＮＤ論理、ＯＲ論理）として動作しているセレクタである。処理１３１では、これらのパストランジスタセレクタを、図１４の変換パターンに従ってＣＭＯＳゲートに変換する。なお、図１４の変換パターンで簡単化した記号で示したＣＭＯＳ回路の２入力ＮＡＮＤゲート、２入力ＮＯＲゲートおよびインバータは、それぞれトランジスタＴ１０〜Ｔ１３、Ｔ２０〜Ｔ２３、Ｔ３０〜３１のトランジスタレベルの回路から構成される。
【００４４】
図１４の変換パターンからわかるように、一つのパストランジスタセレクタは必ずしも一つのＣＭＯＳゲートに変換するされるわけではなく、通常、極性合わせためのインバータが必要になる。このため、図１４の変換パターンに従って、パストランジスタセレクタをＣＭＯＳゲートに変換しただけでは、元から存在するインバータと、変換によって生じた極性合わせのためのインバータが２個直列に接続された冗長なインバータが生じてしまう可能性がある。つまり、面積、遅延時間、消費電力等の回路特性の優れたパストランジスタ／ＣＭＯＳ協調論理回路を生成するためには、インバータ伝搬を行って、このような無駄なインバータを回路から取り除く必要がある。また、パストランジスタセレクタをＣＭＯＳゲートに変換することによって、パストランジスタセレクタが、ＣＭＯＳゲートを直接駆動する形の回路が生じる可能性も考えられるが、この場合には、パストランジスタセレクタとＣＭＯＳゲートの間にバッファ用インバータを挿入する必要がある。以上のインバータ伝搬とバッファ挿入処理は互いに相反する処理であるが、この二つの処理をひとまとめにして同時に行うことによって、必要なところにはバッファ用のインバータが挿入され、しかも冗長なインバータは存在しない、面積、遅延時間、消費電力等の回路特性の優れたパストランジスタ／ＣＭＯＳ協調論理回路を作ることが可能になる（処理１３２）。
【００４５】
次に、インバータ伝搬およびバッファ挿入が終わった回路に対して、回路の面積、遅延時間、消費電力を計算する。これらの回路特性の値から、この回路のコストを算出する。こうして求められた、ＣＭＯＳゲートに変換した後の回路のコストと、あらかじめ求めておいたＣＭＯＳゲートに変換する前の回路のコストを比較する（処理１３３）。ＣＭＯＳゲートに変換した回路の方がコストが良ければＣＭＯＳゲートに変換した回路を選択し、ＣＭＯＳゲートよりパストランジスタセレクタの方がコストが良ければ回路をＣＭＯＳゲートに変換する前の回路に戻す。このようにして、ＣＭＯＳゲートとパストランジスタセレクタのうちでよりコストが良い方を選択する（処理１３４）。以上の処理１３１〜１３４を図１４の変換パターンに該当するすべてのパストランジスタセレクタに対して行って、ＣＭＯＳゲートで組み直した方が回路特性が良くなるすべてのパストランジスタセレクタをＣＭＯＳゲートで組み直して、面積、遅延時間、消費電力等の回路特性の優れたパストランジスタ／ＣＭＯＳ協調論理回路を作成する。
【００４６】
本方法では、面積、遅延時間、消費電力から決定されるコストの定義を変更することで、面積、遅延時間、消費電力のどれに重点をおいてを、回路を合成するかを制御することが可能である。例えば、図９の１３５で定義されるコストで、面積優先度α、遅延時間優先度β、消費電力優先度γを、α＝１、β＝０、γ＝０に設定すると、遅延時間と消費電力は考慮されずに、ただ面積だけを小さくするようにして、パストランジスタ／ＣＭＯＳ協調論理回路の合成が行われる。また、α＝０、β＝０、γ＝１に設定すれば、消費電力を最優先にしたパストランジスタ／ＣＭＯＳ協調論理回路が合成される。もちろん、三つの回路特性をすべてが良くなるように合成することも可能であり、α＝１、β＝１、γ＝１に設定すれば、面積も遅延時間も消費電力も考慮してパストランジスタ／ＣＭＯＳ協調論理回路が合成される。
【００４７】
本実施例では以下に、図１３のパストランジスタ論理回路から、面積最優先（図９の１３５で定義されるコストでα＝１、β＝０、γ＝０に設定）で、パストランジスタ／ＣＭＯＳ協調論理回路を合成する方法を説明する。図１３の回路で、セレクタＳ１００は図１４の変換パターンのａに該当するので、処理１３１によってＣＭＯＳゲートに変換され、図１５の中間回路が作成される。図１５の中間回路では、パストランジスタセレクタＳ１０１が、そのままではＣＭＯＳゲートＧ１００を直接駆動する形になるため、バッファ用インバータＩ１０８が挿入される。また、このインバータＩ１０８の極性合わせのために、インバータＩ１０７も挿入される。しかし、このインバータＩ１０７はセレクタＳ１０１をはさんで、元からあったインバータＩ１０１およびＩ１０２と２個直列に接続された形の冗長なインバータであるので、処理１３２のインバータ伝搬処理によって取り除かれる。また、インバータＩ１００、Ｉ１０６も冗長であるので取り除くことができ、図１６のパストランジスタ／ＣＭＯＳ協調論理回路が得られる。この図１６の回路の面積をライブラリ１１を参照して計算すると、９９２μ になり、コストもこの面積の値と同じ値になる。一方、パストランジスタセレクタＳ１００をＣＭＯＳゲートに組み直す前の面積は、１１６４μ であり、コストもこの値になる。つまり、ＣＭＯＳゲートに変換した方がコストが良く、ＣＭＯＳゲートに変換した回路が選択される。図１６の回路の残りのパストランジスタセレクタのうち、Ｓ１０４とＳ１０５は、図１４の変換パターンのｃに該当するので、同様にＣＭＯＳゲートに変換されるが、パストランジスタセレクタＳ１０５については、パストランジスタセレクタで回路を構成した方が面積が小さく、コストも良いため、ＣＭＯＳゲートには組み直されない。以上の処理により、最終的には図１７のパストランジスタ／ＣＭＯＳ協調論理回路が合成される。
【００４８】
表１は、実施例２の論理関数から本発明によって合成されたパストランジスタ／ＣＭＯＳ協調論理回路と、ＣＭＯＳ論理回路、パストランジスタ論理回路、およびＣＭＯＳ論理回路をパストランジスタセレクタに置き換えて作成された論理回路の、面積、遅延時間、消費電力を比較した表である。
【００４９】
【表１】

【００５０】
表１に示すように、本方法で面積最優先で合成したパストランジスタ／ＣＭＯＳ協調論理回路は、ＣＭＯＳ単独で構成した論理回路（図１０）より、面積を４０％近く削減することに成功しており、遅延時間および消費電力についても、それぞれ５％と６０％近く削減できている。また、パストランジスタ単独で構成した論理回路（図１３）と比較しても、遅延時間と消費電力では劣るものの、目的とする面積の小さいパストランジスタ／ＣＭＯＳ協調論理回路が合成できていることがわかる。
【００５１】
実施例１でも述べたように、パストランジスタセレクタが最も得意とするのは、ＮＡＮＤ論理やＮＯＲ論理ではなく、複数ある何かの信号を他の信号で選択するというセレクタ論理である。本方法では、与えられた論理関数から二分決定グラフを作り、パストランジスタ単独で構成した論理回路を作ってから、その論理回路で、ＮＡＮＤ論理、ＮＯＲ論理（あるいはＡＮＤ論理、ＯＲ論理）として機能しているパストランジスタセレクタをＣＭＯＳゲートに変換して論理回路を組み直す。このような手順で論理回路を合成することにより、与えられた論理関数のなかで、セレクタ論理に相当する部分にはパストランジスタセレクタを割り当て、それ以外のＮＡＮＤ論理や、ＮＯＲ論理（あるいはＡＮＤ論理、ＯＲ論理）に相当する部分にはＣＭＯＳゲートを割り当てることが可能になる。このようにして、パストランジスタセレクタとＣＭＯＳゲートを、それぞれに適した部分に上手に使い分けることにより、パストランジスタセレクタとＣＭＯＳゲートの両方の長所をうまく組み合わせたパストランジスタ／ＣＭＯＳ協調論理回路を生成する。
【００５２】
本発明の論理回路合成方法を使用しなくても、パストランジスタとＣＭＯＳゲートをただ組み合わせただけの論理回路を作ることは可能である。例えば、本方法とは全く逆の手順で、ＣＭＯＳ単独の論理回路を作ってから、その回路のＣＭＯＳゲートの中でパストランジスタセレクタに適している部分を見つけて、その部分をパストランジスタセレクタに変換して、パストランジスタとＣＭＯＳゲートを組み合わせた回路を作ることもできる。しかし、ＣＭＯＳ論理回路では、すべての論理がＮＡＮＤ論理とＮＯＲ論理（あるいはＡＮＤ論理、ＯＲ論理）の組み合わせで構成されているため、与えられた論理関数にパストランジスタセレクタに適したセレクタ論理部分が存在したとしても、それに対応する部分を見つけだすことは困難である。実際、本実施例の論理関数から合成したＣＭＯＳ論理回路（図１０）をパストランジスタセレクタに置き換えてみると、図１８に示すパストランジスタ回路が得られる。この回路では、すべてのパストランジスタセレクタが、２本の入力のいずれか一方の入力がＶＤＤあるいはＧＮＤ電位に固定されており、パストランジスタセレクタには適してないＮＡＮＤ論理、ＮＯＲ論理として使用されている。セレクタ論理として使用されているパストランジスタセレクタは一つとして存在しない。このため、表１に示すように、図１８の回路は、ＣＭＯＳ単独の論理回路（図１０）や、パストランジスタ単独で構成した論理回路（図１３）のいずれよりも、面積、遅延時間、消費電力のすべての回路特性において劣っている。このように、ＣＭＯＳ論理回路からは、パストランジスタとＣＭＯＳゲートの長所をうまく組み合わせた論理回路を作成することは困難であり、最悪の場合には、この例のように、ＣＭＯＳ単独で構成した論理回路、パストランジスタ単独で構成した論理回路のどちらよりも性能の劣った回路ができてしまうことがわかる。
【００５３】
以上からわかるように、ただ単にＣＭＯＳゲートとパストランジスタセレクタを組み合わせただけでは、パストランジスタセレクタとＣＭＯＳゲートのそれぞれの長所をうまく組み合せることは不可能であり、最悪の場合にはそれらの短所だけが組み合わされた回路特性の劣った論理回路ができてしまう。つまり、本方法に示した手順で回路を合成することによってはじめて、パストランジスタセレクタとＣＭＯＳゲートのそれぞれの長所をうまく組み合せたパストランジスタ／ＣＭＯＳ協調論理回路を合成することが可能になる。
【００５４】
＜実施例２の変形例＞
実施例２では、パストランジスタセレクタをｎチャネル電界効果トランジスタだけで構成した例を説明したが、ｐチャネル、ｎチャネルの両方のタイプのトランジスタで構成したパストランジスタセレクタ（例えば図２０に示したトランジスタＴ２００〜Ｔ２０３、インバータＩ２００から構成されるセレクタ）でも、実施例２と全く同様にして、本方法により、面積の小さいパストランジスタ／ＣＭＯＳ協調論理回路を作ることが可能である。このことは、以下の実施例でも全く同様である
＜実施例３＞
本実施例では、実施例２と同じ論理関数を例にとって、実施例２と違って遅延時間を最優先（図９の１３５のコストでα＝０、β＝１、γ＝０に設定）にしてパストランジスタ／ＣＭＯＳ協調論理回路を合成した例を説明する。実施例２と同様に、二分決定グラフ作成ルーチン１１０で二分決定グラフが作られ、パストランジスタマッピングルーチン１２０により、図１３のパストランジスタ論理回路が作られる。図１３のパストランジスタ論理回路で、まずパストランジスタセレクタＳ１００が選択され、処理１３１によりＣＭＯＳゲートに変換される。次に、処理１３２により、セレクタＳ１０１の出力にバッファ用インバータが挿入され、冗長なインバータが取り除かれて、図１６の中間回路が得られる。処理１３５では、実施例２の場合と違って、面積ではなく回路の遅延時間が計算され、遅延時間の値がこの回路のコストになる。ＣＭＯＳゲートに組み直す前の回路（図１３）の遅延時間は、入力Ｆ→セレクタＳ１０４→セレクタＳ１０２→バッファ用インバータＩ１０３→セレクタＳ１００内のインバータ→セレクタＳ１００→バッファ用インバータＩ１００の経路の遅延時間である。一方、ＣＭＯＳゲートで組み直した回路（図１６）で対応する経路は、入力Ｆ→セレクタＳ１０４→セレクタＳ１０２→バッファ用インバータＩ１０３→ＣＭＯＳゲートＧ１００に短縮されるので、遅延時間は大幅に小さくなる。このため、ＣＭＯＳゲートで組み直した回路の方がコストが良いので、処理１３４ではＣＭＯＳゲートで組み直した回路が選択される。
【００５５】
発明の解決すべき課題の項で説明したように、多段二分決定グラフから構成されるパストランジスタ単独の論理回路では、あるパストランジスタセレクタがバッファ用インバータを介して、後段のパストランジスタセレクタの制御入力に接続される構成の回路ができる（図１３のＳ１０２→Ｉ１０３→Ｓ１００内のインバータ→Ｓ１００）。この場合、バッファ用インバータと後段のパストランジスタセレクタ内のインバータが直列に接続されるので遅延時間がどうしても遅くなってしまう。しかし、実施例１で既に説明したように、この例のように後段のパストランジスタセレクタをうまくＣＭＯＳゲートで組み直すことができれば、パストランジスタセレクタ内の遅いインバータを省略することができるので、遅延時間の小さい論理回路を作ることが可能になる。一般に、パストランジスタ単独の論理回路をパストランジスタ／ＣＭＯＳ協調論理回路に組み直すことにより遅延時間を小さくすることができる。
【００５６】
残りのパストランジスタセレクタのうち、図１４の変換パターンに相当するのはＳ１０４とＳ１０５である。面積最優先の実施例２ではＳ１０４のみがＣＭＯＳゲートで組み直されたが、遅延時間最優先の本実施例では、Ｓ１０５もＣＭＯＳゲートに変換される。理由は、Ｓ１００の場合と同様に、セレクタＳ１０５をＣＭＯＳゲートに変換することによりセレクタＳ１０５内の遅いインバータを取り除くことができ、遅延時間をさらに削減できるからである。以上の操作により、最終的には図１９のパストランジスタ／ＣＭＯＳ協調論理回路が得られる。表１に示すように、本実施例でも、本方法でパストランジスタ／ＣＭＯＳ協調論理回路を合成することにより、ＣＭＯＳ単独で構成した論理回路（図１０）より、遅延時間を２０％近く削減することに成功している。また、パストランジスタ単独で構成した論理回路（図１３）と比較しても、遅延時間を１０％近く小さくすることに成功している。
【００５７】
＜実施例４＞
本実施例では、実施例２、３と異なり、消費電力を最優先（図９の１３５のコストでα＝０、β＝１、γ＝０に設定）にしてパストランジスタ／ＣＭＯＳ協調論理回路を合成する方法を、実施例２、３と同じ論理関数を例にして説明する。実施例２、３と同様に、二分決定グラフ作成ルーチン１１０で二分決定グラフが作られ、パストランジスタセレクタマッピングルーチン１２０を経て、図１３のパストランジスタ論理回路が作られる。図１３のパストランジスタ論理回路で、まずセレクタＳ１００選択され、処理１３１、処理１３２を経て、図１６の中間回路が得られる。次の処理１３３では、実施例２、３と違って、回路の消費電力が計算され、消費電力の値が回路のコストになる。図１６のパストランジスタ／ＣＭＯＳ協調論理回路の消費電力をライブラリ１１を参照して計算すると、１４３μＷ／ＭＨｚになる。一方、ＣＭＯＳゲートに変換する前の回路（図１３）の消費電力は、１４０μＷ／ＭＨｚであるので、実施例２、３の場合と違って、パストランジスタセレクタで回路を構成した方がコストが良い。つまり、処理１３４で選択されるのはＣＭＯＳゲートで組み直した回路ではなく、パストランジスタセレクタで構成した回路になる。図１４の変換パターンに該当する残りのパストランジスタセレクタはＳ１０４、Ｓ１０５であるが、実施例２、３と違って、この２つのセレクタについても、パストランジスタセレクタで構成した回路の方が消費電力が小さく、コストが良い。このため、消費電力最優先の本実施例では、図１３のパストランジスタ論理回路は、ＣＭＯＳゲートに全く組み直されることなくそのまま出力される。
【００５８】
この理由は、図４のパストランジスタセレクタとＣＭＯＳゲートの比較結果にも示したように、パストランジスタセレクタの消費電力はＣＭＯＳゲートよりも大幅に小さいからである（ＣＭＯＳゲートの半分以下）。これは、パストランジスタセレクタでは、セレクタ回路の大半を占めるセレクタ部分をｎチャネル電界効果トランジスタだけで構成して、より性能の劣るｐチャネル電界効果トランジスタの数を削減することにより、性能を劣化させることなくパストランジスタセレクタ回路内のトランジスタのゲート幅の合計を押さえること可能であり、このため、消費電力を小さくできるからである。
【００５９】
＜実施例５＞
本発明のパストランジスタ／ＣＭＯＳ協調論理回路の合成方法では、ＣＭＯＳゲートに変換した方が回路の性能が良くなると考えられる、ＮＡＮＤ論理やＮＯＲ論理（あるいはＡＮＤ論理、ＯＲ論理）として動作しているパストランジスタセレクタを、ＣＭＯＳゲートに変換するのであるが、実際にＣＭＯＳゲートに変換するかどうかは、パストランジスタセレクタをＣＭＯＳゲートに変換して、回路の面積、遅延時間、消費電力から定義されるコストを計算してコストが良くなるかどうかで判断する。このため、本方法では、以上の実施例２、３、４からわかるように、パストランジスタ／ＣＭＯＳ協調論理回路を合成する際の、面積、遅延時間、電力で定義されるコストを変更することで、パストランジスタセレクタとＣＭＯＳゲートの割合を変化させて、合成される回路の諸特性を柔軟に制御することが可能である。例えば、図２１は、実施例２、３、４よりも大規模な論理関数（ＣＭＯＳゲート換算で約１０００ゲート）を例にして、図９の１３５のコストで面積優先度αと電力優先度γを０から１の間で変化させることにより、面積最優先から消費電力最優先まで変化させて、パストランジスタ／ＣＭＯＳ協調論理回路を合成した結果である。図２１の結果からわかるように、消費電力の優先度が増加するに従って、消費電力を削減するのに適したパストランジスタの割合が増加し、消費電力優先のパストランジスタ／ＣＭＯＳ協調論理回路が合成されていることがわかる。このように、本方法で合成されるパストランジスタ／ＣＭＯＳ協調論理回路では、パストランジスタセレクタとＣＭＯＳゲートの割合を制御することによって、合成される回路の特性を容易にコントロールすることが可能である。また、この結果から、実際の大規模な論理でパストランジスタ／ＣＭＯＳ協調論理回路を組んだ場合に、面積、遅延時間、消費電力の三つの回路特性が最もバランスが良いのは、パストランジスタ回路の面積比率が回路全体の１０〜６０％程度の場合であることが初めて明らかになった。
【００６０】
本方法では、 実際に回路の面積、遅延時間、消費電力等の回路特性が良くなる場合だけ、パストランジスタセレクタをＣＭＯＳゲートに変換する。このため、本方法では、どんな論理関数に対しても常にパストランジスタ単独で構成した論理回路、あるいはＣＭＯＳゲート単独で構成した論理回路よりも回路特性の優れたパストランジスタ／ＣＭＯＳ協調論理回路を合成することが可能である。例えば、図２２は、図２１の論理よりさらに大規模な１２種類の論理（ＣＭＯＳゲート換算で１０００〜１００００ゲート）に対して、本方法で合成したパストランジスタ／ＣＭＯＳ協調論理回路と、従来の方法で合成したパストランジスタ単独の論理回路を、ＣＭＯＳ単独の論理回路を基準にして比較した結果である。この結果からわかるように、本方法では、どんな論理に対しても、従来のパストランジスタ単独の論理回路およびＣＭＯＳ単独の論理回路よりも常に面積と消費電力の両方が優れたパストランジスタ／ＣＭＯＳ協調論理回路を合成することが可能であることがわかる。
【００６１】
＜実施例６＞
以上の実施例では、図９のプログラムによって、パストランジスタ／ＣＭＯＳ協調論理回路を合成する手順を示した。本実施例では以下に、図２３に示すプログラムによってパストランジスタ／ＣＭＯＳ協調論理回路を合成する方法を説明する。これまでの実施例２〜５と同様に、まず二分決定グラフ作成ルーチン１１０によって二分決定グラフが作られる。実施例２〜５と違うのは、この二分決定グラフから、パストランジスタセレクタ／ＣＭＯＳゲートマッピングルーチン３００により、パストランジスタ論理回路を経由せずに、直接パストランジスタ／ＣＭＯＳ協調論理回路を合成する点である。以下、図２４の二分決定グラフを例にしてこのパストランジスタセレクタ／ＣＭＯＳゲートマッピングルーチン３００を説明する。まず処理３０１によって、ノードＮ３０１は図１４のｂに該当するので、図１４の変換パターンに従って、ＣＭＯＳゲートにマッピングされる（図２５のＧ３０１、Ｉ３００）。その他のノードＮ３００、Ｎ３０２、Ｎ３０３は図１２のマッピングルールに従ってパストランジスタセレクタおよびインバータにマッピングされる（図２５のＳ３００、Ｉ３０１）。このようにして図２５の中間回路が生成される。図２５の中間回路で、インバータＩ３００とＩ３０１は冗長なインバータであるので、処理３０２により除去され、最終的には図２６の回路が合成される。
【００６２】
実施例２〜５のパストランジスタ／ＣＭＯＳ協調論理回路合成プログラム（図９）では、一度パストランジスタ論理回路を作ってから、ＮＡＮＤ論理やＮＯＲ論理（あるいはＡＮＤ論理、ＯＲ論理）として動作しているパストランジスタセレクタを、回路の面積、遅延時間、消費電力等の回路特性から定義されるコストを計算して、コストが良くなればＣＭＯＳゲートに変換する。このため、どんな場合でも、回路特性の優れた論理回路を合成できることが保証される。しかし、毎回、回路の面積、遅延時間、消費電力等を計算する必要があるため、回路の合成に多少時間がかかるという欠点がある。また、図４からわかるように、たいていの場合、ＮＡＮＤ論理やＮＯＲ論理（あるいはＡＮＤ論理、ＯＲ論理）として動作しているパストランジスタセレクタは、ＣＭＯＳゲートに変換した方が合成される回路の特性は良くなる。このため、本実施例のように、コストを計算せずに、二分決定グラフから直接、パストランジスタ／ＣＭＯＳ協調論理回路を作成しても、そこそこ回路特性の優れた論理回路が合成できることが期待できる。実際、図２４の二分決定グラフからパストランジスタ論理回路を合成すると図２７の回路が合成されるが、この回路と比べてみると、本方法で合成されたパストランジスタ／ＣＭＯＳ協調論理回路（図２５）の方がトランジスタ数が少なく、優れた論理回路が合成できていることがわかる。このように、本方法によっても、パストランジスタセレクタとＣＭＯＳゲートの長所をうまく組み合わせたパストランジスタ／ＣＭＯＳ協調論理回路を合成することが可能である。
【００６３】
【発明の効果】
以上に示した実施例からわかるように、本発明によれば、与えられた論理回路仕様がどんな論理であっても、パストランジスタ回路とＣＭＯＳ回路の両方の長所をうまく組み合わせることにより、従来のＣＭＯＳ単独で構成した論理回路およびパストランジスタ単独で構成した論理回路よりも、面積、遅延時間、消費電力等の回路特性の優れたパストランジスタ／ＣＭＯＳ協調論理回路を合成することが可能になる。
【００６４】
また、回路の面積、遅延時間、消費電力から定義されるコストを調整することにより、パストランジスタセレクタとＣＭＯＳゲートの割合を変化させて、合成されるパストランジスタ／ＣＭＯＳ協調論理回路の面積、遅延時間、消費電力等の回路特性を柔軟にコントロールすることが可能になる。
【図面の簡単な説明】
【図１】本発明の望ましい実施形態。
【図２】本発明の他の望ましい実施形態。
【図３】本発明の他の望ましい実施形態。
【図４】パストランジスタセレクタでＮＡＮＤ論理およびＮＯＲ論理を構成した場合と、ＣＭＯＳゲートで構成した場合の比較の図。
【図５】本発明の第１の実施例によるパストランジスタ／ＣＭＯＳ協調論理回路と、従来のパストランジスタ論理回路およびＣＭＯＳ論理回路を比較した図。
【図６】本発明の第１の実施例によるパストランジスタ／ＣＭＯＳ協調論理回路のレイアウト例。
【図７】本発明の第２の実施例による、論理回路を合成するための計算機システムとそこに使用される論理回路合成プログラムの概略構成図。
【図８】本発明の第２の実施例による、論理回路の合成から半導体集積回路の製造までのフローチャート。
【図９】実施例２のパストランジスタ／ＣＭＯＳ協調論理回路合成プログラムのフロチャート。
【図１０】実施例２の論理関数から既存の公知の方法で合成されたＣＭＯＳ論理回路の回路図。
【図１１】図９の本発明のパストランジスタ／ＣＭＯＳ協調論理回路合成プログラムの二分決定グラフ作成ルーチンによって作成される多段二分決定グラフの例を示す図。
【図１２】パストランジスタセレクタのマッピングルールを示す図。
【図１３】図９の本発明のパストランジスタ／ＣＭＯＳ協調論理回路合成プログラムのパストランジスタマッピングルーチンによって、図１１の多段二分決定グラフから作成されるパストランジスタ論理回路の回路図。
【図１４】本発明の方法でパストランジスタ／ＣＭＯＳ協調論理回路を合成する際に、ＣＭＯＳゲートに変換されるパストランジスタセレクタのパターンと、その変換ルールを示す図。
【図１５】図９の本発明のパストランジスタ／ＣＭＯＳ協調論理回路合成プログラムのＣＭＯＳゲート割り当てルーチンの途中で作成される中間回路の回路図。
【図１６】図９の本発明のパストランジスタ／ＣＭＯＳ協調論理回路合成プログラムのＣＭＯＳゲート割り当てルーチンの途中で作成される中間回路の回路図。
【図１７】図９の本発明のパストランジスタ／ＣＭＯＳ協調論理回路合成プログラムで面積最優先に設定した時に合成されるパストランジスタ／ＣＭＯＳ協調論理回路の回路図。
【図１８】図１０のＣＭＯＳ論理回路からＣＭＯＳゲートをパストランジスタセレクタに変換して作成される論理回路の回路図。
【図１９】図９の本発明のパストランジスタ／ＣＭＯＳ協調論理回路合成プログラムで遅延時間最優先に設定した時に合成されるパストランジスタ／ＣＭＯＳ協調論理回路の回路図。
【図２０】ｐチャネルとｎチャネルの両方のタイプのトランジスタで構成したパストランジスタセレクタの回路図。
【図２１】本発明のパストランジスタ／ＣＭＯＳ協調論理回路合成プログラムで、コストを面積最優先から遅延時間最優先まで変化させた時の結果。
【図２２】１２種類の異なった論理に対して、本発明のパストランジスタ／ＣＭＯＳ協調論理回路合成プログラムで合成される論理回路と、既存の公知の方法で合成したＣＭＯＳ論理回路およびパストランジスタ論理回路との、面積と消費電力を比較した図。
【図２３】本発明の第６の実施例によるパストランジスタ／ＣＭＯＳ協調論理回路の合成プログラムのフロチャート。
【図２４】図２３の本発明のパストランジスタ／ＣＭＯＳ協調論理回路合成プログラムにより作成される二分決定グラフの例を示す図。
【図２５】図２３の本発明のパストランジスタ／ＣＭＯＳ協調論理回路合成プログラムのパストランジスタセレクタ／ＣＭＯＳゲートマッピングルーチンの途中で作成される中間回路の回路図。
【図２６】図２３の本発明のパストランジスタ／ＣＭＯＳ協調論理回路合成プログラムにより合成されるパストランジスタ／ＣＭＯＳ協調論理回路の回路図。
【図２７】図２４の二分決定グラフから合成されるパストランジスタ論理回路の回路図。[0001]
[Field of the Invention]
The present invention relates to a small area, high speed, low power consumption logic circuit combining a pass transistor circuit and a CMOS circuit, and from a logical function, a small area, high speed, low power consumption combining a pass transistor circuit and a CMOS circuit. The present invention relates to a method for synthesizing a logic circuit.
[0002]
[Prior art]
In a pass transistor logic circuit which is one of logic circuits, one transistor can have various logic functions. For this reason, the pass transistor logic circuit is well constructed, and all the conventional CMOS logic circuits are replaced with the pass transistor logic circuit, thereby greatly reducing the number of LSI transistors on one scale and reducing the size of the LSI. Many studies aiming at area reduction and low power consumption have been published. In it, a binary decision diagram is created from the logic function, and each node is replaced with a two-input, one-output, one-control-input pass transistor selector, and a pass transistor logic having a target logic function. There is a method of synthesizing a circuit. The binary decision graph is a logical expression of a logical function by a binary tree of nodes having two branches called a 1-branch and a 0-branch, and has the property that a complex logical function can be expressed concisely. Therefore, this method is attracting attention as a method for synthesizing a compact pass transistor logic circuit having a target logic function with a small number of transistors.
[0003]
For example, Proceeding of IEEE 1994 Custom Integrated Circuits Conference, pp. In 603-606 (hereinafter referred to as Document 1), a two-input one-output pass transistor selector is composed of only an n-channel field effect transistor, and a buffer inverter for reducing the delay time is inserted as necessary. A method of synthesizing a target pass transistor logic circuit has been proposed. Conventional CMOS logic circuits require as many p-channel field effect transistors as inferior performance as n-channel field effect transistors. However, in the pass transistor logic circuit synthesized by the method of Document 1, most of the circuit other than the buffer inverter can be configured only by high-performance n-channel field effect transistors. Therefore, it is possible to obtain a circuit with excellent performance and smaller area, delay time and power consumption than the conventional CMOS logic circuit.
[0004]
Also, IEEE Symposium on Low Power Electronics, 1995, pp. 14-15 (hereinafter referred to as Document 2) proposes a method in which Document 1 is further developed. This method is characterized in that a pass transistor logic circuit is synthesized from a multistage binary decision graph (hereinafter referred to as a multistage binary decision graph). The multistage binary decision graph is created by the following procedure.
[0005]
(1-1) Create a binary decision graph from a logical function.
[0006]
(1-2) On the created binary decision graph, the nodes pointed to by 0 branch or 1 branch are different, but the other graphs with the same shape (isomorphic subtree) are extracted and controlled by the isomorphic subtree. Create a new node.
[0007]
Due to the effect of (1-2), a multistage binary decision graph can express a logical function with fewer nodes than an ordinary binary decision graph. Therefore, it is possible to synthesize a pass transistor logic circuit having a target logic function with fewer transistors than in Document 1. In addition, since the number of nodes connected in series is also suppressed, the number of pass transistor circuits to be combined is suppressed. For this reason, it is possible to synthesize a pass transistor logic circuit having a smaller delay time than that of Document 1 and also having a smaller area and power consumption.
[0008]
In addition, IEICE technical report VLD95-115, Vol. 95, no. 119, pp. 91-96 (hereinafter referred to as Document 3) proposes a method for synthesizing a pass transistor logic circuit with low power consumption. In this method, the pass transistor logic circuit is synthesized from the multistage binary decision graph as in the literature 2, but the pass transistor logic circuit with lower power consumption can be obtained by narrowing down the buffer inverter for improving the delay time to the minimum necessary. Can be synthesized.
[0009]
The pass transistor circuit is described in JP-A-1-129611, JP-A-1-216622, JP-A-1-256219, JP-A-7-130856, and the like.
[0010]
Furthermore, other methods for synthesizing the pass transistor logic circuit are described in Japanese Patent Application Laid-Open No. 7-168874 and Japanese Patent Application No. 8-97132.
[0011]
[Problems to be solved by the invention]
The present inventors actually synthesized a pass transistor logic circuit by creating binary decision graphs for several logic functions by the methods described in Documents 1, 2, and 3. As a result, for a certain logic function, it was possible to synthesize a pass transistor logic circuit having a smaller number of transistors, smaller area, delay time, and power consumption than a conventional CMOS logic circuit. However, for other logical functions, it has been found that the area, delay time, and power consumption may increase.
[0012]
For example, when a simple two-input NAND logic is synthesized by a pass transistor logic circuit according to the methods of Documents 1, 2, and 3, a circuit of six transistors C1 in FIG. However, the CMOS logic circuit is a simpler circuit (C2 in FIG. 4) having four transistors. Also for the 2-input NOR logic, the pass transistor logic circuit is a circuit with 6 transistors (C3 in FIG. 4), but the CMOS logic circuit is a circuit with 4 transistors (C4 in FIG. 4).
[0013]
As shown in FIG. 4, in the NAND logic and the NOR logic, regarding the area and delay time other than the power consumption, the performance is better when the circuit is configured with CMOS gates. As described above, the pass transistor selector circuit is suitable for the selector logic that selects a plurality of signals with other signals, instead of NAND logic or NOR logic, because of its circuit structure. On the other hand, NAND logic and NOR logic are basic circuits of a CMOS circuit, and it can be said that it is natural to assemble a logic circuit having better performance in the CMOS circuit. However, regarding the power consumption, the pass transistor circuit can be made smaller even in the NAND logic and the NOR logic.
[0014]
This has been overlooked in research on conventional pass transistor logic circuits, but both pass transistor circuits and CMOS circuits are good and bad at each, and pass transistor circuits are superior to CMOS circuits in all cases. It shows that it is not. Moreover, which of the pass transistor circuit and the CMOS circuit is superior depends on which of the circuit characteristics of area, delay time, and power consumption is given priority in the synthesized logic circuit.
[0015]
Unlike the era of manually designing logic circuits, logic circuits are now designed in high-level languages such as HDL (Hardware Description Language), so if the else often used in HDL. In other words, it is very important how a logic that combines Boolean algebra and selector logic) can be realized with a compact logic circuit.
[0016]
In this way, it is impossible to create a logic circuit with excellent circuit characteristics for any logic, and regardless of the circuit characteristics of area, delay time, and power consumption. It is necessary to create a pass transistor / CMOS cooperative logic circuit in which the advantages of both the pass transistor circuit and the CMOS circuit are combined well, that is, the pass transistor circuit and the CMOS circuit cooperate well in one logic circuit. . Also, providing a method for automatically synthesizing such a high-performance pass transistor / CMOS cooperative logic circuit in a computer system is an LSI with a small area, a small delay time, and a small power consumption. To make a chip, it has a very important meaning.
[0017]
Furthermore, when the pass transistor logic circuit was synthesized from the multistage binary decision graph by the method described in Reference Document 2, it was possible to further reduce the number of transistors. However, depending on the logic, the delay time was delayed. There was a case. When the inventors analyzed this independently, it was found that there were the following problems. That is, in the pass transistor logic circuit synthesized from the multistage binary decision graph, a circuit having a configuration in which a certain pass transistor selector is connected to the control input of the subsequent pass transistor selector through the buffer inverter can be formed. In this case, since the buffer inverter and the inverter in the subsequent pass transistor selector are connected in series, the delay time is inevitably delayed. In other words, this method of synthesizing a pass transistor logic circuit from a multistage binary decision graph may be impractical when the delay time condition is severe and the above delay time problem becomes a bottleneck. found.
[0018]
The object of the present invention is to combine the advantages of a pass transistor circuit and a CMOS circuit with respect to any kind of logic, so that a logic circuit constituted only by a conventional pass transistor or a logic circuit constituted only by a CMOS is provided. Provides a pass transistor / CMOS cooperative logic circuit with excellent circuit characteristics such as area, delay time, and power consumption, and at the same time, automatically synthesizes such a high-performance pass transistor / CMOS cooperative logic circuit with a computer system. Is to provide a way to do.
[0019]
Another object of the present invention is to synthesize a logic composed of only a pass transistor from a conventional multistage binary decision graph by properly combining the advantages of a pass transistor circuit and a CMOS circuit for any kind of logic. The present invention provides a pass transistor / CMOS cooperative logic circuit that solves the problem of circuit delay time, has a small delay time and a small number of transistors, has excellent circuit characteristics such as area, delay time, and power consumption, and a synthesis method thereof. That is.
[0020]
Another object of the present invention is to provide a method for synthesizing a logic circuit that is more desirable in terms of area, circuit characteristics such as delay time, power consumption, etc., or a combination thereof by combining a pass transistor circuit and a CMOS circuit. It is.
[0021]
[Means for Solving the Problems]
In order to achieve the above object, in a preferred embodiment of the present invention,
A first p-channel field effect transistor (TP1) whose gate is controlled by the first input (IN1) and whose source / drain path is connected between the first operating potential point (VDD) and the first node (NP1). )When,
A second p-channel field effect transistor (TP2) whose gate is controlled by the second input (IN2) and whose source / drain path is connected between the first operating potential point (VDD) and the first node (NP1). )When,
A first n-channel field effect transistor (TN1) having a gate controlled by a first input (IN1) and having a source / drain path connected between the first node (NP1) and the fourth node (NP4);
A second n-channel field effect transistor (TN2) whose gate is controlled by the second input (IN2) and whose source / drain path is connected between the fourth node (NP4) and the second operating potential point (GND). )When,
A third p-channel field effect transistor (TP3) whose gate is controlled by the first node (NP1) and whose source / drain path is connected between the first operating potential point (VDD) and the second node (NP2) When,
A third n-channel field effect transistor (TN3) whose gate is controlled by the first node (NP1) and whose source / drain path is connected between the second node (NP2) and the second operating potential point (GND) When,
A fifth n-channel field effect transistor (TN5) having a gate controlled by the second node (NP1) and having a source / drain path connected between the third input (IN3) and the third node (NP3);
A sixth n-channel field effect transistor (TN6) having a gate controlled by the first node (NP1) and having a source / drain path connected between the fourth input (IN4) and the third node (NP3);
A fourth p-channel field effect transistor (TP4) whose gate is controlled by the third node (NP3) and whose source-drain path is connected between the first operating potential point (VDD) and the first output (OUT1) When,
A fourth n-channel field effect transistor (TN4) whose gate is controlled by the third node (NP3) and whose source / drain path is connected between the first output (OUT1) and the second operating potential point (GND); 1 is a logic circuit (FIG. 1) including selector logic with Boolean processing.
[0022]
In another desirable aspect of the present invention, the gate is controlled by the tenth input (IN10), and the source / drain path is connected between the first operating potential point (VDD) and the tenth node (NP10). A tenth p-channel field effect transistor (TP10);
A tenth n-channel field effect transistor (TN10) whose gate is controlled by the tenth input (IN10) and whose source / drain path is connected between the tenth node (NP10) and the second operating potential point (GND). )When,
An eleventh n-channel field effect transistor (TN11) whose gate is controlled by the tenth node (NP10) and whose source / drain path is connected between the eleventh input (IN11) and the eleventh node (NP11);
A twelfth n-channel field effect transistor (TN12) whose gate is controlled by the tenth input (IN10) and whose source / drain path is connected between the twelfth input (IN12) and the eleventh node (NP11); ,
A fifteenth p-channel field effect transistor (TP15) whose gate is controlled by the eleventh node (NP11) and whose source / drain path is connected between the first operating potential point (VDD) and the twelfth node (NP12). When,
A fifteenth n-channel field effect transistor (TN15) whose gate is controlled by the eleventh node (NP11) and whose source / drain path is connected between the twelfth node (NP12) and the second operating potential point (GND). When,
A fourteenth p-channel field effect transistor (TP14) whose gate is controlled by the twelfth node (NP12) and whose source / drain path is connected between the first operating potential point (VDD) and the tenth output (OUT10). )When,
A fourteenth n-channel field effect transistor (TN14) whose gate is controlled by the twelfth node (NP12) and whose source / drain path is connected between the tenth output (OUT10) and the thirteenth node (NP13);
A thirteenth p-channel field effect transistor whose gate is controlled by the thirteenth input (IN13) and whose source / drain path is connected between the first operating potential point (VDD) and the tenth output (OUT10). TP13)
A thirteenth n-channel field effect transistor (TN13) whose gate is controlled by a thirteenth input (IN13) and whose source / drain path is connected between the tenth output (OUT10) and the second operating potential point (GND). 2) is a logic circuit (FIG. 2) including selector logic with Boolean processing.
[0023]
In another desirable aspect of the present invention, the gate is controlled by the 20th input (IN20), and the source / drain path is connected between the first operating potential point (VDD) and the 20th node (NP20). A twentieth p-channel field effect transistor (TP20);
A twenty-first p-channel field effect transistor (TP21) whose gate is controlled by a twenty-first input (IN21) and whose source / drain path is connected between the first operating potential point (VDD) and the twentieth node (NP20). )When,
A twentieth n-channel field effect transistor (TN20) having a gate controlled by a twentieth input (IN20) and having a source-drain path connected between the twentieth node (NP20) and the twenty-fourth node (NP24);
A twenty-first n-channel field effect transistor (TN21) whose gate is controlled by a twenty-first input (IN21) and whose source / drain path is connected between the twenty-fourth node (NP24) and the second operating potential point (GND). )When,
A twenty-second p-channel field effect transistor (TP22) whose gate is controlled by the twenty-second input (IN22) and whose source / drain path is connected between the first operating potential point (VDD) and the twenty-second node (NP22). )When,
A twenty-second n-channel field effect transistor (TN22) whose gate is controlled by a twenty-second input (IN22) and whose source / drain path is connected between the twenty-second node (NP22) and the second operating potential point (GND). )When,
A twenty-third n-channel field effect transistor (TN23) whose gate is controlled by the twenty-second node (NP22) and whose source-drain path is connected between the twenty-third input (IN23) and the twenty-third node (NP23);
A twenty-fourth n-channel field effect transistor (TN24) whose gate is controlled by a twenty-second input (IN22) and whose source-drain path is connected between the twentieth node (NP20) and the twenty-third node (NP23); ,
A twenty-fifth p-channel field effect transistor (TP25) whose gate is controlled by the twenty-third node (NP23) and whose source / drain path is connected between the first operating potential point (VDD) and the twentieth output (OUT20). When,
A twenty-fifth n-channel field effect transistor (TN25) whose gate is controlled by the twenty-third node (NP23) and whose source / drain path is connected between the twentieth output (OUT20) and the second operating potential point (GND). ) Including a selector logic with Boolean processing (FIG. 3).
[0024]
In order to automatically synthesize a logic circuit combining such a pass transistor circuit and a CMOS circuit by a computer system, in the present invention, a binary decision graph or a multistage binary decision graph is created from a logic function, and all of its nodes are input as two. A pass transistor logic circuit is created by mapping to a pass transistor selector with one output and one control input. In the pass transistor logic circuit, one of the two inputs is fixed to a logical constant 1 or 0, and the pass transistor operates as NAND logic or NOR logic (or AND logic, OR logic). If the selector is replaced with a logically equivalent CMOS gate such as NAND, NOR, etc., and the circuit characteristic values such as area, delay time, power consumption, etc. are calculated and replaced with the CMOS gate, the predetermined circuit characteristic value is obtained. If closer to optimal, the pass transistor selector is replaced with a CMOS gate. The above operation is tried for all the pass transistor selectors to synthesize a pass transistor / CMOS cooperative logic circuit in which predetermined circuit characteristics are optimum. As circuit characteristics used for such optimization, for example, area, delay time, power consumption, or an appropriate combination thereof is used.
[0025]
In another desirable aspect of the present invention, a binary decision graph or a multistage binary decision graph is created from a logical function, and only one of two branches (0 branch, 1 branch) among the nodes of the graph is created. However, a CMOS gate such as NAND or NOR which is logically equivalent to the node is mapped to a node which is fixed to the logical constant 1 or 0. Further, a pass transistor selector with two inputs and one output is mapped to other nodes to synthesize a pass transistor / CMOS cooperative logic circuit.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the pass transistor / CMOS cooperative logic circuit of the present invention and the synthesis method thereof will be described in more detail with reference to some embodiments shown in the drawings. In the following, the same reference numerals represent the same or similar items.
[0027]
<Example 1>
An embodiment of the pass transistor / CMOS cooperative logic circuit of the present invention will be described with reference to FIG. 5A, 5B, and 5C, the logics given by the following logic functions are constituted by the pass transistor / CMOS cooperative logic circuit of the present invention and the conventional pass transistor logic circuit and CMOS logic circuit, respectively. It is the figure which compared the case where it did. Note that the inverter and the CMOS gate indicated by the simplified symbols in FIG. 5 are composed of the transistor circuit shown in FIG.

In FIG. 5a, the pass transistor / CMOS cooperative logic circuit of the present invention is a circuit composed of an inverter I50, a pass transistor selector S50, and a CMOS gate G50. On the other hand, in the conventional pass transistor logic circuit, inverters I50 and I51 and pass transistor selectors S50 and S51 are required. In the CMOS logic circuit, inverters I52 and I54 and CMOS gates G50 to G53 are required. As shown in FIG. 5a, in the conventional pass transistor logic circuit, NAND logic and NOR logic that are not suitable for the pass transistor circuit must also be assembled in the pass transistor circuit (S51). Further, in the conventional CMOS logic circuit, the selector logic that is not suitable for the CMOS circuit must also be configured by the CMOS circuit (G51 to G53). On the other hand, in the pass transistor / CMOS cooperative logic circuit of the present invention, in the given logic, the portion corresponding to the selector logic is composed of the pass transistor selector (S50) suitable for the selector logic, and the rest NAND and NOR logic parts can be configured with a CMOS gate (G50) suitable for the NAND and NOR logic parts. As described above, the transistor / CMOS cooperative logic circuit of the present invention can realize a logic in which selector logic, NAND logic, and NOR logic (AND logic or OR logic) are combined with a compact circuit. For this reason, the pass transistor logic circuit requires 14 transistors and the CMOS logic circuit requires 20 transistors, whereas the pass transistor / CMOS cooperative logic circuit of the present invention can achieve the desired logic function with 11 transistors. It can be seen that the circuit has excellent performance with a small area and low power consumption. Furthermore, in the pass transistor / CMOS cooperative logic circuit of the present invention, the portion corresponding to the selector S51 and the inverter I51 of the pass transistor logic circuit can be reduced to one CMOS gate G50. The delay time required for the inverter in S51 → the selector S51 → the buffer inverter I51 can be shortened to the delay time of only the CMOS gate G50. Furthermore, since the inverter having a slow delay time in the selector S51 of the pass transistor logic circuit can be removed from the path, the pass transistor / CMOS cooperative logic circuit of the present invention has a significantly smaller delay time than the pass transistor logic circuit. can do. Compared with the CMOS logic circuit, the paths of the G51 to G53, I52, and I54 portions of the CMOS logic circuit can be shortened to S50 and I50 in the pass transistor / CMOS cooperative logic circuit of the present invention. The delay time is smaller in the pass transistor / CMOS cooperative logic circuit. FIG. 6 shows a layout example of the pass transistor / CMOS cooperative logic circuit of the present invention shown in FIG. In FIG. 6, cell 1 corresponds to a NAND gate (G50) of the CMOS circuit, and cell 2 corresponds to a pass transistor selector (S50). As shown in FIG. 6, the height h1 of the cell 1, the height h4 of the cell 2, h2 and h3 which are the widths of the power supply lines (VDD and GND) of the cell 1, and the power supply line (VDD) of the cell 2 In addition, by making h5 and h6, which are the widths of (GND) and GND, equal, it is possible to actually manufacture a logic circuit in which a pass transistor circuit and a CMOS circuit are combined into one circuit. The same applies to the following embodiments.
[0028]
Further, in the logic of FIG. 5b, the pass transistor / CMOS cooperative logic circuit of the present invention has a circuit having an intended logic function with 11 transistors composed of the inverter I60, the pass transistor selector S60, and the CMOS gate G60. Can be configured. On the other hand, in the pass transistor logic circuit, inverters I60 and I61 and pass transistor selectors S60 and S61 are required, and 14 transistors are required. In the CMOS logic circuit, inverters I62 and I64 and CMOS gates G60 to G63 are required, and 20 transistors are required. That is, in this case as well, it can be seen that the pass transistor / CMOS cooperative logic circuit of the present invention has the best performance. As for the delay time, in the pass transistor / CMOS cooperative logic circuit of the present invention, the portion corresponding to the selector S61 and the inverter I61 of the pass transistor logic circuit can be reduced to one CMOS gate G60. The delay time of the inverter in the selector S61 → the selector S61 → the buffer inverter I61 can be shortened to the delay time of only the CMOS gate G50, and in particular, the slow inverter in the selector S61 can be removed, so that the pass transistor The delay time can be significantly reduced as compared with the logic circuit. Compared with the CMOS logic circuit, the paths of the G61 to G63, I62, and I64 portions of the CMOS logic circuit can be shortened to S60 and I60 in the pass transistor / CMOS cooperative logic circuit of the present invention. The delay time is smaller in the pass transistor / CMOS cooperative logic circuit.
[0029]
Further, in FIG. 5c, in the pass transistor / CMOS cooperative logic circuit of the present invention, a circuit having a target logic function can be configured by 11 transistors including the inverter I70, the pass transistor selector S70, and the CMOS gate G70. . On the other hand, in the pass transistor logic circuit, inverters I70 and I71 and pass transistor selectors S70 and S71 are required, and 14 transistors are required. In the CMOS logic circuit, inverters I72 and I74 and CMOS gates G70 to G73 are required, and 20 transistors are required. That is, in this case as well, it can be seen that the pass transistor / CMOS cooperative logic circuit of the present invention has the best performance. Regarding the delay time, the pass transistor / CMOS cooperative logic circuit of the present invention is the smallest for the same reason as in FIGS.
[0030]
<Example 2>
In the above embodiment, the pass transistor / CMOS cooperative logic circuit of the present invention has been described by taking simple logic as an example. In this embodiment, a high-performance pass transistor / CMOS cooperative logic circuit having excellent circuit characteristics such as area, delay time, power consumption, etc. is automatically processed by a computer system shown in FIGS. A method of synthesis will be described.
[0031]
(1) Overall system configuration
In FIG. 8, the designer inputs a logic circuit specification 10 describing the specification of the logic function of the target semiconductor integrated circuit. The logic circuit specification 10 describes a logic function that describes the logic function of the circuit. In addition, target values of circuit characteristics such as the circuit area, delay time, and power consumption, and information on which circuit characteristics to prioritize are also described. The pass transistor / CMOS cooperative logic circuit synthesis program 100 unique to the present embodiment refers to the library 11 from the information described in the logic circuit specification 10, and targets for circuit characteristics such as area, delay time, and power consumption. The pass transistor / CMOS cooperative logic circuit 12 having the logic function of the logic circuit specification 10 is synthesized so as to satisfy the value. The automatic layout program 160 refers to the library 11 to determine an optimal layout for this logic circuit, and creates layout data 20. The mask data creation program 170 determines a plurality of mask patterns for generating the synthesized logic circuit using the semiconductor integrated circuit technology according to the layout data 20, and generates mask data 21 representing these mask patterns. . The semiconductor manufacturing apparatus 180 uses the mask data 21 to manufacture a semiconductor integrated circuit having a target logic function. The programs 100, 160, and 170 are executed on different computers assigned to the respective programs. Of course, these programs can be executed on the same computer.
[0032]
FIG. 7 shows a schematic structure of the pass transistor / CMOS cooperative logic circuit synthesis program 100 of the present invention and a computer system for executing this program. This computer system comprises an input device, for example, a keyboard 1, a central processing unit (CPU) 2, a display device (CRT) 3, a magnetic tape device 4, and a magnetic disk device 5 for storing a logic circuit synthesis program 100. The program 100 includes a binary decision graph creation routine 110, a pass transistor selector mapping routine 120, and a CMOS gate assignment routine 130. This program is loaded from the magnetic disk device 5 to the CPU 2 and executed when the designer gives an instruction from the keyboard 1. The pass transistor / CMOS cooperative logic circuit synthesized by the program 100 is displayed on the CRT 3 and transferred to the automatic layout program 160 of FIG. 8 via the magnetic tape device 4 and the like.
[0033]
In this embodiment, a binary decision graph is created, and a portion of the pass transistor circuit that is synthesized by mapping the pass transistor selector is found to have better performance when changed to the CMOS circuit, and the portion is reassembled with the CMOS circuit. Thus, the present invention is characterized in that a pass transistor / CMOS cooperative logic circuit having higher performance than a conventional logic circuit of a single pass transistor or a CMOS single logic circuit is synthesized. Specifically, one of the two inputs is fixed to a logical constant 1 or 0, and a pass transistor selector operating as NAND logic or NOR logic (AND logic or OR logic) is logically If the values of circuit characteristics such as area, delay time and power consumption are calculated and replaced with CMOS gates such as NAND and NOR equivalent to By replacing the pass transistor selector with a CMOS gate, the CMOS circuit re-assembles the portion where the performance is better when the CMOS circuit is used. Hereinafter, each routine of the present embodiment will be described by taking the following logical function as an example.
[0034]
out1 = B * A + C * A + (I * F + D) * (D + (H + E) * (E + G))
out2 = B + ((I * F + D) * (D + (H + E) * (E + G)))
When a CMOS logic circuit is synthesized from this logic function by an existing known method, a circuit composed of G100 to G111 in FIG. 10 is obtained.
[0035]
(2) Binary decision graph creation routine 110
This routine 110 generates a binary decision graph from the logic circuit specification 10. The logic circuit specification 10 includes an input variable and an output variable corresponding to an input signal and an output signal of a logic circuit to be combined, and a logic function representing a logic function of the circuit.
[0036]
When a binary decision graph is created from the logical function shown above, a graph composed of the nodes N100 to N111 in FIG. 11 is created. In the multistage binary decision graph of FIG. 11, the nodes N104 to N109 are shared and bundled to be multistaged, so that the number of nodes is reduced from that of the normal binary decision graph. In order to create a small binary decision graph with a small number of nodes, the order of the input variables when creating the graph is very important, but this input variable order is used to create an existing known binary decision graph. Can be determined using tools.
[0037]
(3) Pass transistor selector mapping routine 120
In accordance with the mapping rule of FIG. 12, this routine maps each node of the binary decision graph created by the binary decision graph creation routine 110 to a pass transistor selector, an inverter, or the like according to the type of node, thereby passing the pass transistor logic circuit. Is generated. Furthermore, a buffer inverter is inserted as necessary.
[0038]
When the destination where the 1 branch and the 0 branch are connected is not the logical constant 1 or 0 as in the node N1 shown in FIG. 12a, 2 composed of n-channel field effect transistors T0 and T1 and an inverter I0. The pass transistor selector S0 with input 1 output is made to correspond. The input variable A corresponding to the node of the binary decision graph is assigned to the control input of the pass transistor selector S0, and the output of the node connected to one branch is input to the input in1 selected when the control input is 1. assign. The output of the node connected to the 0 branch is assigned to the input in0 selected when the control input is 0.
[0039]
When the one branch is connected to the logical constant 1 and the zero branch is connected to the logical constant 0 as in the node N2 in FIG. 12b, the output of this node is that the input variable A of the node is 1. When the input variable A is 0, 0 is output. That is, the input signal A may be connected to the subsequent circuit as it is.
[0040]
When one branch is connected to the logical constant 0 and the 0 branch is connected to the logical constant 1 as in the node N3 shown in FIG. 12c, the output of this node is the input variable A of the node. When 0 is 1, 0 is output, and when the input variable A is 0, 1 is output. That is, the input signal A may be inverted by an inverter and connected to a subsequent circuit.
[0041]
By mapping in this way, a pass transistor logic circuit having the same logic function as the binary decision graph is synthesized. When the pass transistor logic circuit is synthesized from the binary decision graph of FIG. 11, the pass transistor logic circuit including the pass transistor selectors S100 to S105 and the inverters I100 to I105 shown in FIG. 13 is synthesized. In this circuit, I100, I103, and I105 are buffer inverters. In the binary decision graph of FIG. 11, nodes N102, N103, and N109 correspond to b of the mapping rule of FIG. 12, and nodes N106, N107, and N111 correspond to c of FIG. The other nodes correspond to a in FIG.
[0042]
(4) CMOS gate allocation routine 130
In this routine, among the pass transistor logic circuits generated in the pass transistor selector mapping routine 120, it is considered that the circuit characteristics such as area, delay time, power consumption, etc. are improved by reassembling with the CMOS gate. A pass transistor selector operating as logic (or AND logic, OR logic) is reassembled with a CMOS gate.
[0043]
First, a pass transistor selector corresponding to the conversion patterns a to d in FIG. 14 is selected from the pass transistor logic circuit. In the pass transistor selector shown in FIGS. 14A to 14D, either one of the two inputs is fixed to the VDD or GND potential, that is, the NAND logic in which the logic constant 1 or the logic constant 0 is fixed. , A selector operating as NOR logic (or AND logic, OR logic). In process 131, these pass transistor selectors are converted into CMOS gates according to the conversion pattern of FIG. Note that the 2-input NAND gate, 2-input NOR gate, and inverter of the CMOS circuit indicated by the simplified symbols in the conversion pattern of FIG. 14 are derived from the transistor level circuits of the transistors T10 to T13, T20 to T23, and T30 to 31, respectively. Composed.
[0044]
As can be seen from the conversion pattern of FIG. 14, one pass transistor selector is not necessarily converted into one CMOS gate, and an inverter for adjusting the polarity is usually required. Therefore, according to the conversion pattern of FIG. 14, only by converting the pass transistor selector into a CMOS gate, a redundant inverter in which two inverters for the polarity adjustment generated by the conversion and two inverters connected in series are connected in series. May occur. That is, in order to generate a pass transistor / CMOS cooperative logic circuit having excellent circuit characteristics such as area, delay time, and power consumption, it is necessary to perform inverter propagation and remove such a useless inverter from the circuit. In addition, there is a possibility that a circuit in which the pass transistor selector directly drives the CMOS gate may be generated by converting the pass transistor selector to the CMOS gate. In this case, however, the circuit between the pass transistor selector and the CMOS gate may be generated. It is necessary to insert an inverter for buffer. The above inverter propagation and buffer insertion processing are mutually contradictory processes, but by performing these two processes together, a buffer inverter is inserted where necessary, and there is no redundant inverter. It is possible to make a pass transistor / CMOS cooperative logic circuit having excellent circuit characteristics such as area, delay time, and power consumption (process 132).
[0045]
Next, the circuit area, delay time, and power consumption are calculated for the circuit for which inverter propagation and buffer insertion have been completed. The cost of this circuit is calculated from these circuit characteristic values. The cost of the circuit after conversion to the CMOS gate obtained in this way is compared with the cost of the circuit before conversion to the CMOS gate obtained in advance (processing 133). If the cost of the circuit converted to the CMOS gate is better, the circuit converted to the CMOS gate is selected. If the cost of the pass transistor selector is better than that of the CMOS gate, the circuit is returned to the circuit before the conversion to the CMOS gate. In this way, the more costly one of the CMOS gate and the pass transistor selector is selected (process 134). The above processes 131 to 134 are performed on all the pass transistor selectors corresponding to the conversion pattern of FIG. 14, and all the pass transistor selectors whose circuit characteristics are improved by reassembling with CMOS gates are recombined with CMOS gates. A pass transistor / CMOS cooperative logic circuit having excellent circuit characteristics such as area, delay time, and power consumption is created.
[0046]
In this method, by changing the definition of cost determined from area, delay time, and power consumption, it is possible to control whether to synthesize a circuit with emphasis on area, delay time, or power consumption. Is possible. For example, if the area priority α, delay time priority β, and power consumption priority γ are set to α = 1, β = 0, and γ = 0 at the cost defined by 135 in FIG. The power transistor is not considered, and the pass transistor / CMOS cooperative logic circuit is synthesized by reducing only the area. Further, if α = 0, β = 0, and γ = 1, a pass transistor / CMOS cooperative logic circuit with the highest priority on power consumption is synthesized. Of course, it is also possible to synthesize all three circuit characteristics so as to improve all. If α = 1, β = 1, and γ = 1, the pass transistor is considered in consideration of area, delay time, and power consumption. / CMOS cooperative logic circuit is synthesized.
[0047]
In the present embodiment, from the pass transistor logic circuit of FIG. 13, the area transistor is first given the highest priority (set at α = 1, β = 0, and γ = 0 at the cost defined by 135 in FIG. 9). A method for synthesizing the cooperative logic circuit will be described. In the circuit of FIG. 13, the selector S100 corresponds to a in the conversion pattern of FIG. 14, so that it is converted into a CMOS gate by processing 131, and the intermediate circuit of FIG. 15 is created. In the intermediate circuit of FIG. 15, since the pass transistor selector S101 directly drives the CMOS gate G100 as it is, the buffer inverter I108 is inserted. In addition, an inverter I107 is also inserted for polarity adjustment of the inverter I108. However, this inverter I107 is a redundant inverter in the form of two inverters I101 and I102 that are originally connected across the selector S101, and is thus removed by the inverter propagation process of the process 132. Further, the inverters I100 and I106 are redundant and can be removed, and the pass transistor / CMOS cooperative logic circuit of FIG. 16 is obtained. When the area of the circuit of FIG. 16 is calculated with reference to the library 11, it becomes 992μ, and the cost is also the same as this area value. On the other hand, the area before reassembling the pass transistor selector S100 to the CMOS gate is 1164 μm, and the cost is also this value. That is, it is more costly to convert to a CMOS gate, and a circuit converted to a CMOS gate is selected. Of the remaining pass transistor selectors in the circuit of FIG. 16, S104 and S105 correspond to the conversion pattern c of FIG. 14, and thus are similarly converted to CMOS gates. However, for the pass transistor selector S105, the pass transistor selector Since the circuit is smaller in area and cost is better, it is not reassembled into a CMOS gate. Through the above processing, the pass transistor / CMOS cooperative logic circuit of FIG. 17 is finally synthesized.
[0048]
Table 1 shows the logic created by replacing the pass transistor / CMOS cooperative logic circuit synthesized by the present invention from the logic function of the second embodiment, the CMOS logic circuit, the pass transistor logic circuit, and the CMOS logic circuit with a pass transistor selector. It is the table | surface which compared the area, delay time, and power consumption of a circuit.
[0049]
[Table 1]

[0050]
As shown in Table 1, the pass transistor / CMOS cooperative logic circuit synthesized with the area first priority by this method succeeded in reducing the area by nearly 40% compared to the logic circuit (FIG. 10) constituted by the CMOS alone. In addition, the delay time and power consumption can be reduced by nearly 5% and 60%, respectively. Further, it can be seen that a pass transistor / CMOS cooperative logic circuit having a small target area can be synthesized, although the delay time and power consumption are inferior to those of a logic circuit composed of a pass transistor alone (FIG. 13). .
[0051]
As described in the first embodiment, the pass transistor selector is most good at selector logic that selects a plurality of signals with other signals, not NAND logic or NOR logic. In this method, a binary decision graph is created from a given logic function, a logic circuit composed of only pass transistors is created, and the logic circuit functions as NAND logic, NOR logic (or AND logic, OR logic). The pass transistor selector is converted to a CMOS gate to reassemble the logic circuit. By synthesizing the logic circuit in such a procedure, a pass transistor selector is assigned to a portion corresponding to the selector logic in the given logic function, and other NAND logic, NOR logic (or AND logic, A CMOS gate can be assigned to a portion corresponding to (OR logic). In this way, by properly using the pass transistor selector and the CMOS gate appropriately for the respective parts, a pass transistor / CMOS cooperative logic circuit that successfully combines the advantages of both the pass transistor selector and the CMOS gate is generated.
[0052]
Even without using the logic circuit synthesis method of the present invention, it is possible to make a logic circuit that is simply a combination of a pass transistor and a CMOS gate. For example, after making a CMOS logic circuit in the reverse procedure of this method, find a part suitable for the pass transistor selector in the CMOS gate of the circuit, and convert that part into a pass transistor selector. Thus, a circuit combining a pass transistor and a CMOS gate can be formed. However, in a CMOS logic circuit, all logic is composed of a combination of NAND logic and NOR logic (or AND logic, OR logic), so there is a selector logic part suitable for a pass transistor selector in a given logic function. Even so, it is difficult to find the corresponding part. In fact, when the CMOS logic circuit (FIG. 10) synthesized from the logic function of this embodiment is replaced with a pass transistor selector, the pass transistor circuit shown in FIG. 18 is obtained. In this circuit, all pass transistor selectors are used as NAND logic or NOR logic, which is not suitable for a pass transistor selector, with either one of the two inputs fixed at VDD or GND potential. . There is no single pass transistor selector used as the selector logic. Therefore, as shown in Table 1, the circuit of FIG. 18 has a larger area, delay time, and consumption than the CMOS alone logic circuit (FIG. 10) and the logic circuit constituted by the pass transistor alone (FIG. 13). Inferior in all circuit characteristics of power. Thus, it is difficult to create a logic circuit that successfully combines the advantages of a pass transistor and a CMOS gate from a CMOS logic circuit, and in the worst case, a logic composed of a CMOS alone as in this example. It can be seen that a circuit with inferior performance compared to either a circuit or a logic circuit composed of a pass transistor alone can be produced.
[0053]
As can be seen from the above, it is impossible to combine the advantages of the pass transistor selector and the CMOS gate by simply combining the CMOS gate and the pass transistor selector. As a result, a logic circuit with inferior circuit characteristics is formed. That is, it is possible to synthesize a pass transistor / CMOS cooperative logic circuit that combines the advantages of the pass transistor selector and the CMOS gate only by synthesizing the circuit according to the procedure shown in the present method.
[0054]
<Modification of Example 2>
In the second embodiment, the example in which the pass transistor selector is configured only by the n-channel field effect transistor has been described. However, the pass transistor selector configured by both p-channel and n-channel transistors (for example, the transistor T200 illustrated in FIG. 20). In the same manner as in the second embodiment, it is possible to make a pass transistor / CMOS cooperative logic circuit with a small area by using this method. The same applies to the following examples.
<Example 3>
In this embodiment, taking the same logical function as that of the second embodiment as an example, unlike the second embodiment, the delay time is given the highest priority (set α = 0, β = 1, γ = 0 at the cost of 135 in FIG. 9). An example of synthesizing a pass transistor / CMOS cooperative logic circuit will be described. As in the second embodiment, a binary decision graph is created by the binary decision graph creation routine 110, and the pass transistor logic circuit of FIG. 13 is created by the pass transistor mapping routine 120. In the pass transistor logic circuit of FIG. 13, the pass transistor selector S100 is first selected and converted to a CMOS gate by processing 131. Next, by processing 132, a buffer inverter is inserted into the output of the selector S101, redundant inverters are removed, and the intermediate circuit of FIG. 16 is obtained. In the process 135, unlike the case of the second embodiment, not the area but the delay time of the circuit is calculated, and the delay time value becomes the cost of this circuit. The delay time of the circuit (FIG. 13) before reassembly into the CMOS gate is the delay time of the path of input F → selector S104 → selector S102 → buffer inverter I103 → inverter in selector S100 → selector S100 → buffer inverter I100. . On the other hand, the corresponding path in the circuit reassembled with the CMOS gate (FIG. 16) is shortened from the input F → the selector S104 → the selector S102 → the buffer inverter I103 → the CMOS gate G100, so that the delay time is significantly reduced. For this reason, since a circuit reassembled with a CMOS gate is more costly, a circuit reassembled with a CMOS gate is selected in step 134.
[0055]
As described in the section of the problem to be solved by the invention, in a logic circuit with a single pass transistor composed of a multistage binary decision graph, a certain pass transistor selector is connected to a control input of a subsequent pass transistor selector via a buffer inverter. (The inverter in S102 → I103 → S100 in FIG. 13 → S100). In this case, since the buffer inverter and the inverter in the subsequent pass transistor selector are connected in series, the delay time is inevitably delayed. However, as already described in the first embodiment, if the succeeding pass transistor selector can be reassembled with a CMOS gate as in this example, the slow inverter in the pass transistor selector can be omitted. It becomes possible to make a small logic circuit. Generally, the delay time can be reduced by reassembling the logic circuit of the pass transistor alone to the pass transistor / CMOS cooperative logic circuit.
[0056]
Of the remaining pass transistor selectors, S104 and S105 correspond to the conversion pattern of FIG. In Example 2 where the area has the highest priority, only S104 is reassembled with the CMOS gate, but in this example where the delay time has the highest priority, S105 is also converted to the CMOS gate. The reason is that, as in the case of S100, by converting the selector S105 into a CMOS gate, the slow inverter in the selector S105 can be removed, and the delay time can be further reduced. By the above operation, the pass transistor / CMOS cooperative logic circuit of FIG. 19 is finally obtained. As shown in Table 1, also in this embodiment, by synthesizing the pass transistor / CMOS cooperative logic circuit by this method, the delay time is reduced by almost 20% compared with the logic circuit (FIG. 10) constituted by the CMOS alone. Has succeeded. Also, compared with a logic circuit (FIG. 13) configured by a single pass transistor, the delay time has been reduced by nearly 10%.
[0057]
<Example 4>
In the present embodiment, unlike the second and third embodiments, the pass transistor / CMOS cooperative logic circuit is configured with the power consumption as the highest priority (set α = 0, β = 1, γ = 0 at the cost of 135 in FIG. 9). A method of synthesizing will be described using the same logical function as in the second and third embodiments as an example. As in the second and third embodiments, a binary decision graph is created by the binary decision graph creation routine 110, and the pass transistor selector mapping routine 120 is passed through the pass transistor logic circuit of FIG. In the pass transistor logic circuit of FIG. 13, first, the selector S100 is selected, and after the processing 131 and processing 132, the intermediate circuit of FIG. 16 is obtained. In the next process 133, unlike the second and third embodiments, the power consumption of the circuit is calculated, and the value of the power consumption becomes the cost of the circuit. When the power consumption of the pass transistor / CMOS cooperative logic circuit of FIG. 16 is calculated with reference to the library 11, it is 143 μW / MHz. On the other hand, the power consumption of the circuit before conversion to the CMOS gate (FIG. 13) is 140 μW / MHz, and unlike the second and third embodiments, it is better to configure the circuit with a pass transistor selector. . In other words, what is selected in the process 134 is not a circuit reassembled with CMOS gates, but a circuit composed of pass transistor selectors. The remaining pass transistor selectors corresponding to the conversion pattern of FIG. 14 are S104 and S105. However, unlike the second and third embodiments, the power consumption of these two selectors is also higher in the circuit constituted by the pass transistor selectors. Small and good cost. For this reason, in this embodiment in which power consumption has the highest priority, the pass transistor logic circuit of FIG. 13 is output as it is without being reassembled into a CMOS gate.
[0058]
This is because the power consumption of the pass transistor selector is significantly smaller than that of the CMOS gate as shown in the comparison result between the pass transistor selector and the CMOS gate in FIG. 4 (less than half of the CMOS gate). This is because, in the pass transistor selector, the selector portion that occupies most of the selector circuit is composed of only n-channel field effect transistors, and the number of p-channel field effect transistors with lower performance is reduced, thereby degrading the performance. This is because it is possible to suppress the total gate width of the transistors in the pass transistor selector circuit and to reduce power consumption.
[0059]
<Example 5>
In the method of synthesizing the pass transistor / CMOS cooperative logic circuit of the present invention, the path operating as NAND logic or NOR logic (or AND logic, OR logic) is considered that the performance of the circuit is better when converted to the CMOS gate. The transistor selector is converted into a CMOS gate, but whether or not it is actually converted into a CMOS gate is determined by converting the pass transistor selector into a CMOS gate and reducing the cost defined by the circuit area, delay time, and power consumption. Judge by calculating whether the cost will improve. For this reason, in this method, as can be seen from the above-described Embodiments 2, 3, and 4, the cost defined by the area, delay time, and power when the pass transistor / CMOS cooperative logic circuit is synthesized is changed. By changing the ratio of the pass transistor selector and the CMOS gate, it is possible to flexibly control various characteristics of the synthesized circuit. For example, FIG. 21 exemplifies a logical function (approximately 1000 gates in terms of CMOS gate) larger than those in the second, third, and fourth embodiments, and area priority α and power priority γ at the cost of 135 in FIG. This is a result of synthesizing the pass transistor / CMOS cooperative logic circuit by changing the value from 0 to 1 to change the power from the highest priority to the highest power consumption. As can be seen from the results of FIG. 21, as the power consumption priority increases, the proportion of pass transistors suitable for reducing power consumption increases, and a power transistor priority CMOS transistor is synthesized. You can see that Thus, in the pass transistor / CMOS cooperative logic circuit synthesized by this method, the characteristics of the synthesized circuit can be easily controlled by controlling the ratio of the pass transistor selector and the CMOS gate. Also, from this result, when the pass transistor / CMOS cooperative logic circuit is assembled with actual large-scale logic, the three circuit characteristics of area, delay time, and power consumption have the best balance. It became clear for the first time that the area ratio was about 10 to 60% of the entire circuit.
[0060]
In this method, the pass transistor selector is converted into a CMOS gate only when the circuit characteristics such as the circuit area, delay time, and power consumption are actually improved. For this reason, this method synthesizes a logic circuit always composed of only a pass transistor for any logic function, or a pass transistor / CMOS cooperative logic circuit having better circuit characteristics than a logic circuit composed of only a CMOS gate. It is possible. For example, FIG. 22 shows a pass transistor / CMOS cooperative logic circuit synthesized by this method for 12 types of logic (1000 to 10,000 gates in terms of CMOS gate) larger than the logic of FIG. This is a result of comparing the logic circuit of the pass transistor synthesized in the above with reference to the logic circuit of the CMOS alone. As can be seen from this result, in this method, for any logic, the pass transistor / CMOS cooperative logic always has both area and power consumption superior to those of the conventional logic circuit of the pass transistor alone and the logic circuit of the CMOS alone. It can be seen that the circuit can be synthesized.
[0061]
<Example 6>
In the above embodiment, the procedure for synthesizing the pass transistor / CMOS cooperative logic circuit by the program of FIG. 9 has been shown. In this embodiment, a method of synthesizing a pass transistor / CMOS cooperative logic circuit by the program shown in FIG. 23 will be described below. As in the previous Examples 2 to 5, a binary decision graph is first created by the binary decision graph creation routine 110. The difference from the second to fifth embodiments is that the pass transistor / CMOS cooperative logic circuit is directly synthesized from the binary decision graph by the pass transistor selector / CMOS gate mapping routine 300 without going through the pass transistor logic circuit. is there. The pass transistor selector / CMOS gate mapping routine 300 will be described below using the binary decision graph of FIG. 24 as an example. First, by the processing 301, the node N301 corresponds to b in FIG. 14, and is mapped to the CMOS gate according to the conversion pattern in FIG. 14 (G301 and I300 in FIG. 25). The other nodes N300, N302, and N303 are mapped to the pass transistor selector and inverter according to the mapping rule of FIG. 12 (S300 and I301 of FIG. 25). In this way, the intermediate circuit of FIG. 25 is generated. In the intermediate circuit of FIG. 25, since the inverters I300 and I301 are redundant inverters, they are removed by the processing 302, and finally the circuit of FIG. 26 is synthesized.
[0062]
In the pass transistor / CMOS cooperative logic circuit synthesis program (FIGS. 9A and 9B) according to the second to fifth embodiments, a pass transistor circuit is once created and then operated as NAND logic, NOR logic (or AND logic, OR logic). The transistor selector calculates a cost defined from circuit characteristics such as circuit area, delay time, power consumption, etc., and converts the cost into a CMOS gate if the cost is improved. For this reason, in any case, it is guaranteed that a logic circuit having excellent circuit characteristics can be synthesized. However, since it is necessary to calculate the circuit area, delay time, power consumption, and the like every time, there is a drawback that it takes some time to synthesize the circuit. In addition, as can be seen from FIG. 4, in most cases, the characteristics of the circuit synthesized when the pass transistor selector operating as NAND logic or NOR logic (or AND logic or OR logic) is converted into a CMOS gate is as follows. Get better. For this reason, even if a pass transistor / CMOS cooperative logic circuit is created directly from the binary decision graph without calculating the cost as in this embodiment, it can be expected that a logic circuit with excellent circuit characteristics can be synthesized. . In fact, when the pass transistor logic circuit is synthesized from the binary decision graph of FIG. 24, the circuit of FIG. 27 is synthesized. Compared with this circuit, the pass transistor / CMOS cooperative logic circuit synthesized by this method (FIG. 25). ) Has fewer transistors and it can be seen that an excellent logic circuit can be synthesized. As described above, this method can also synthesize a pass transistor / CMOS cooperative logic circuit that successfully combines the advantages of a pass transistor selector and a CMOS gate.
[0063]
【The invention's effect】
As can be seen from the embodiments shown above, according to the present invention, no matter what logic a given logic circuit specification is, by combining the advantages of both a pass transistor circuit and a CMOS circuit, It is possible to synthesize a pass transistor / CMOS cooperative logic circuit having excellent circuit characteristics such as area, delay time, and power consumption, as compared to a logic circuit constituted solely and a logic circuit constituted solely by a pass transistor.
[0064]
Further, by adjusting the cost defined by the circuit area, delay time, and power consumption, the ratio of the pass transistor selector and the CMOS gate is changed, and the area and delay time of the synthesized pass transistor / CMOS cooperative logic circuit are changed. Circuit characteristics such as power consumption can be flexibly controlled.
[Brief description of the drawings]
FIG. 1 is a preferred embodiment of the present invention.
FIG. 2 is another preferred embodiment of the present invention.
FIG. 3 is another preferred embodiment of the present invention.
FIG. 4 is a diagram showing a comparison between a case where NAND logic and NOR logic are configured by a pass transistor selector and a case where it is configured by a CMOS gate.
FIG. 5 is a diagram comparing a pass transistor / CMOS cooperative logic circuit according to a first embodiment of the present invention, a conventional pass transistor logic circuit, and a CMOS logic circuit.
FIG. 6 is a layout example of a pass transistor / CMOS cooperative logic circuit according to the first embodiment of the present invention.
FIG. 7 is a schematic configuration diagram of a computer system for synthesizing logic circuits and a logic circuit synthesizing program used therein according to the second embodiment of the present invention.
FIG. 8 is a flowchart from synthesis of a logic circuit to manufacture of a semiconductor integrated circuit according to the second embodiment of the present invention;
9 is a flowchart of a pass transistor / CMOS cooperative logic circuit synthesis program according to Embodiment 2. FIG.
10 is a circuit diagram of a CMOS logic circuit synthesized from the logic function of Embodiment 2 by an existing known method; FIG.
11 is a diagram showing an example of a multistage binary decision graph created by a binary decision graph creation routine of the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention shown in FIG. 9;
FIG. 12 is a diagram showing a mapping rule for a pass transistor selector.
13 is a circuit diagram of a pass transistor logic circuit created from the multistage binary decision graph of FIG. 11 by the pass transistor mapping routine of the pass transistor / CMOS cooperative logic circuit synthesis program of FIG. 9 of the present invention.
FIG. 14 is a diagram showing a pass transistor selector pattern converted to a CMOS gate and a conversion rule thereof when a pass transistor / CMOS cooperative logic circuit is synthesized by the method of the present invention.
15 is a circuit diagram of an intermediate circuit created during the CMOS gate assignment routine of the pass transistor / CMOS cooperative logic circuit synthesis program of FIG. 9 according to the present invention.
16 is a circuit diagram of an intermediate circuit created during the CMOS gate assignment routine of the pass transistor / CMOS cooperative logic circuit synthesis program of FIG. 9 according to the present invention.
17 is a circuit diagram of a pass transistor / CMOS cooperative logic circuit synthesized when the area priority is set by the pass transistor / CMOS cooperative logic circuit synthesis program of FIG. 9 of the present invention.
18 is a circuit diagram of a logic circuit created by converting a CMOS gate into a pass transistor selector from the CMOS logic circuit of FIG.
19 is a circuit diagram of a pass transistor / CMOS cooperative logic circuit synthesized when the delay time is set to have the highest priority in the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention shown in FIG. 9;
FIG. 20 is a circuit diagram of a pass transistor selector composed of both p-channel and n-channel transistors.
FIG. 21 shows the result when the cost is changed from the area top priority to the delay time top priority in the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention.
FIG. 22 shows a logic circuit synthesized by the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention for 12 different types of logic, and a CMOS logic circuit and a pass transistor logic circuit synthesized by an existing known method. Figure comparing the area and power consumption.
FIG. 23 is a flowchart of a synthesis program of the pass transistor / CMOS cooperative logic circuit according to the sixth embodiment of the present invention;
24 is a diagram showing an example of a binary decision graph created by the pass transistor / CMOS cooperative logic circuit synthesis program of FIG. 23 according to the present invention.
25 is a circuit diagram of an intermediate circuit created during the pass transistor selector / CMOS gate mapping routine of the pass transistor / CMOS cooperative logic circuit synthesis program of FIG. 23 according to the present invention.
FIG. 26 is a circuit diagram of a pass transistor / CMOS cooperative logic circuit synthesized by the pass transistor / CMOS cooperative logic circuit synthesis program of FIG. 23 according to the present invention;
27 is a circuit diagram of a pass transistor logic circuit synthesized from the binary decision graph of FIG. 24. FIG.

Claims (33)

A first p-channel field effect transistor having a gate controlled by a first input and having a source-drain path connected between the first operating potential point and the first node;
A second p-channel field effect transistor having a gate controlled by a second input and having a source-drain path connected between the first operating potential point and the first node;
A first n-channel field effect transistor having a gate controlled by a first input and having a source-drain path connected between the first node and the fourth node;
A second n-channel field effect transistor having a gate controlled by a second input and having a source-drain path connected between the fourth node and the second operating potential point;
A third p-channel field effect transistor having a gate controlled by the first node and having a source / drain path connected between the first operating potential point and the second node;
A third n-channel field effect transistor having a gate controlled by the first node and having a source / drain path connected between the second node and the second operating potential point;
A fifth n-channel field effect transistor having a gate controlled by the second node and having a source-drain path connected between the third input and the third node;
A sixth n-channel field effect transistor having a gate controlled by the first node and a source-drain path connected between the fourth input and the third node;
A fourth p-channel field effect transistor having a gate controlled by a third node and having a source-drain path connected between the first operating potential point and the first output;
Including a Boolean selector logic comprising a fourth n-channel field effect transistor having a gate controlled by a third node and having a source-drain path connected between the first output and the second operating potential point. A logic circuit characterized by 2. The logic circuit according to claim 1, further comprising a fifth p-channel field effect transistor having a gate controlled by an output and having a source / drain path connected between the first operating potential point and the third node. A tenth p-channel field effect transistor having a gate controlled by the tenth input and having a source / drain path connected between the first operating potential point and the tenth node;
A tenth n-channel field effect transistor having a gate controlled by a tenth input and having a source / drain path connected between the tenth node and the second operating potential point;
An eleventh n-channel field effect transistor having a gate controlled by the tenth node and having a source / drain path connected between the eleventh input and the eleventh node;
A twelfth n-channel field effect transistor having a gate controlled by the tenth input and having a source drain path connected between the twelfth input and the eleventh node;
A fifteenth p-channel field effect transistor having a gate controlled by the eleventh node and having a source / drain path connected between the first operating potential point and the twelfth node;
A fifteenth n-channel field effect transistor having a gate controlled by the eleventh node and having a source / drain path connected between the twelfth node and the second operating potential point;
A fourteenth p-channel field effect transistor whose gate is controlled by the twelfth node and whose source / drain path is connected between the first operating potential point and the tenth output;
A fourteenth n-channel field effect transistor having a gate controlled by a twelfth node and a source / drain path connected between the tenth output and the thirteenth node;
A thirteenth p-channel field effect transistor having a gate controlled by a thirteenth input and having a source / drain path connected between the first operating potential point and the tenth output;
Including a Boolean selector logic comprising a thirteenth n-channel field effect transistor having a gate controlled by a thirteenth input and having a source drain path connected between the thirteenth node and the second operating potential point. Characteristic logic circuit. 4. The logic of claim 3, further comprising an eleventh p-channel field effect transistor having a gate controlled by the twelfth node and having a source drain path connected between the first operating potential point and the eleventh node. circuit. A twentieth p-channel field effect transistor having a gate controlled by a twentieth input and having a source / drain path connected between the first operating potential point and the twentieth node;
A twenty-first p-channel field effect transistor having a gate controlled by a twenty-first input and having a source-drain path connected between the first operating potential point and the twentieth node;
A twentieth n-channel field effect transistor having a gate controlled by a twentieth input and having a source-drain path connected between the twentieth and twenty-fourth nodes;
A twenty-first n-channel field effect transistor having a gate controlled by a twenty-first input and having a source-drain path connected between the twenty-fourth node and a second operating potential point;
A twenty-second p-channel field effect transistor having a gate controlled by a twenty-second input and having a source-drain path connected between the first operating potential point and the twenty-second node;
A twenty-second n-channel field effect transistor having a gate controlled by a twenty-second input and having a source-drain path connected between the twenty-second node and a second operating potential point;
A twenty-third n-channel field effect transistor whose gate is controlled by the twenty-second node and whose source-drain path is connected between the twenty-third input and the twenty-third node;
A twenty-fourth n-channel field effect transistor having a gate controlled by a twenty-second input and a source-drain path connected between the twentieth and twenty-third nodes;
A twenty-fifth p-channel field effect transistor whose gate is controlled by the twenty-third node and whose source-drain path is connected between the first operating potential point and the twentieth output;
Boolean selector logic comprising a 25th n-channel field effect transistor with its gate controlled by the 23rd node and having a source drain path connected between the twentieth output and the second operating potential point. A logic circuit characterized by 6. The logic circuit according to claim 5, further comprising a 23rd p-channel field effect transistor having a gate controlled by an output and having a source / drain path connected between the first operating potential point and the 23rd node. The logic circuit according to any one of claims 1 to 6,
A logic circuit, wherein an area ratio of a pass transistor selector is 10 to 60%. The logic circuit according to any one of claims 1 and 2,
Having at least cell 1 and cell 2 on a semiconductor substrate;
Cells 1 and 2 have a substantially rectangular shape;
The cell 1 has first and second p-channel field effect transistors and first and second n-channel field effect transistors,
The cell 2 has a fourth p-channel field effect transistor and fourth, fifth, and sixth n-channel field effect transistors,
Cell 1 and Cell 2 have two power lines running in the horizontal direction, and the vertical heights of Cell 1 and Cell 2 are substantially equal,
A logic circuit characterized in that the vertical heights of the power lines of the cell 1 and the cell 2 are substantially equal. A computer system based on a logic function that defines a relationship between a group of input variables representing a group of input signals of the logic circuit to be synthesized and an output variable representing at least one output signal of the logic circuit. A method of synthesizing a logic circuit to be synthesized by the method having the following steps executed by the computer system.
(A) Create a binary decision graph from a logical function;
(B) All the nodes of the binary decision graph are temporarily replaced with pass transistor selector circuits of two inputs, one output and one control input to create a pass transistor logic circuit;
(C) One of the two inputs is replaced with a logically equivalent CMOS gate such as NAND, NOR, AND, OR, etc., in which the pass transistor selector whose logical constant is fixed to 1 or 0 is used. If the values of circuit characteristics such as delay time and power consumption are calculated and replaced with a CMOS gate, the value of the predetermined circuit characteristics is closer to the optimum, the pass transistor selector is replaced with a CMOS gate,
(D) Applying step (c) above to all pass transistor selectors to optimize predetermined circuit characteristics;
(E) A logic circuit formed by combining the pass transistor circuit and the CMOS circuit obtained in the above steps is output as a logic circuit for the logic function. The logic circuit synthesis method according to claim 9, wherein the logic circuit having the optimum value of the predetermined circuit characteristic is a logic circuit having a minimum area. 10. The logic circuit synthesis method according to claim 9, wherein the logic circuit having the optimum value of the predetermined circuit characteristic is a logic circuit having a minimum delay time. The logic circuit synthesis method according to claim 9, wherein the logic circuit having the optimum value of the predetermined circuit characteristic is a logic circuit with minimum power consumption. 10. The logic circuit synthesis method according to claim 9, wherein the logic circuit having the optimum value of the predetermined circuit characteristic is a logic circuit having an optimum combination of area, delay time, and power consumption. A computer system based on a logic function that defines a relationship between a group of input variables representing a group of input signals of the logic circuit to be synthesized and an output variable representing at least one output signal of the logic circuit. A method of synthesizing a logic circuit to be synthesized by the method having the following steps executed by the computer system.
(A) Create a binary decision graph from a logical function;
(B) Among the nodes of the binary decision graph, a node in which only one of two branches (0 branch, 1 trick) is fixed to logical constant 1 or 0 is logically equivalent to that node. Replace with CMOS gates such as NAND, NOR, AND, OR, etc., and replace the other nodes with pass transistor selector circuits with two inputs, one output and one control input
(C) A logic circuit formed by combining the pass transistor circuit obtained in the above steps and a CMOS circuit is output as a logic circuit for the logic function. A method of synthesizing by a computer system a logic circuit that performs a logic function that defines a relationship between an input signal and an output signal,
(A) Create a binary decision graph from the above logical function,
(B) All the nodes of the binary decision graph are converted into pass transistor selector circuits having two inputs, one output and one control input to create a pass transistor logic circuit;
(C) Convert only a part of the pass transistor logic circuit to a logically equivalent CMOS gate to create a CMOS gate logic circuit;
(D) A logic circuit in which a part of the pass transistor logic circuit created in step (b) is replaced with the CMOS logic circuit created in step (c) is output.
A method of synthesizing a logic circuit having each step. A method of manufacturing a semiconductor device by synthesizing a logic circuit that executes a logic function defining a relationship between an input signal and an output signal by a computer system,
(A) Create a binary decision graph from the above logical function,
(B) All the nodes of the binary decision graph are converted into pass transistor selector circuits with two inputs, one output and one control input to create a pass transistor logic circuit;
(C) Convert only a part of the pass transistor logic circuit to a logically equivalent CMOS gate to create a CMOS gate logic circuit;
(D) outputting a logic circuit obtained by replacing a part of the pass transistor logic circuit created in step (b) with the CMOS logic circuit created in step (c);
(E) generating a plurality of mask patterns for generating the logic circuit based on the output logic circuit;
(F) A semiconductor integrated circuit including the logic circuit is manufactured using the plurality of mask patterns.
A method of manufacturing a semiconductor device having each step. A first p-channel field effect transistor having a gate controlled by a first input and having a source-drain path connected between the first operating potential point and the first node;
A second p-channel field effect transistor having a gate controlled by a second input and having a source-drain path connected between the first operating potential point and the first node;
A first n-channel field effect transistor having a gate controlled by a first input and having a source-drain path connected between the first node and the fourth node;
A second n-channel field effect transistor having a gate controlled by a second input and having a source-drain path connected between the fourth node and the second operating potential point;
A fifth n-channel field effect transistor whose gate is controlled by a complementary signal of the signal at the first node and whose source-drain path is connected between the third input and the third node;
A sixth n-channel field effect transistor having a gate controlled by a signal at the first node and a source / drain path connected between the fourth input and the third node;
A first output connected to the third node;
Having an inverter circuit for processing the signal between the third input or the fourth input and the first output;
The inverter circuit includes a fourth p-channel field effect transistor having a source / drain path connected to a first operating potential point, and a fourth n-channel field effect transistor having a source / drain path connected to a second operating potential point. And a logic circuit in which source and drain paths of the fourth p-channel field effect transistor and the fourth n-channel field effect transistor are connected in series. An eleventh n-channel field effect transistor having a gate controlled by a complementary signal of the tenth input signal and having a source / drain path connected between the eleventh input and the eleventh node;
A twelfth n-channel field effect transistor having a gate controlled by a signal of the tenth input and having a source / drain path connected between the twelfth input and the eleventh node;
A twelfth node connected to the eleventh node;
A fourteenth p-channel field effect transistor whose gate is controlled by the twelfth node and whose source / drain path is connected between the first operating potential point and the tenth output;
A thirteenth n-channel field effect transistor having a gate controlled by a thirteenth input and having a source / drain path connected between the thirteenth node and the second operating potential point;
An inverter circuit for processing a signal between the eleventh input or the twelfth input and the twelfth node;
The inverter circuit includes a fifteenth p-channel field effect transistor having a source / drain path connected to a first operating potential point, and a fifteenth n-channel field effect transistor having a source / drain path connected to a second operating potential point. And a logic circuit in which source and drain paths of the fifteenth p-channel field effect transistor and the fifteenth n-channel field effect transistor are connected in series. A twentieth p-channel field effect transistor having a gate controlled by a twentieth input and having a source / drain path connected between the first operating potential point and the twentieth node;
A twenty-first p-channel field effect transistor having a gate controlled by a twenty-first input and having a source-drain path connected between the first operating potential point and the twentieth node;
A twentieth n-channel field effect transistor having a gate controlled by a twentieth input and having a source-drain path connected between the twentieth and twenty-fourth nodes;
A twenty-first n-channel field effect transistor having a gate controlled by a twenty-first input and having a source-drain path connected between the twenty-fourth node and a second operating potential point;
A twenty-third n-channel field effect transistor whose gate is controlled by a complementary signal of the twenty-second input and whose source-drain path is connected between the twenty-third input and the twenty-third node;
A twenty-fourth n-channel field effect transistor having a gate controlled by a twenty-second input and a source-drain path connected between the twentieth and twenty-third nodes;
An inverter circuit for processing a signal between the 23rd input and the 20th output;
The inverter circuit includes a 25th p-channel field effect transistor having a source / drain path connected to a first operating potential point, and a 25th n-channel field effect having a source / drain path connected to a second operating potential point. A logic circuit including a transistor, wherein source and drain paths of the 25th p-channel field effect transistor and the 25th n-channel field effect transistor are connected in series. The logic circuit according to any one of claims 3 to 4,
Having at least cell 1 and cell 2 on a semiconductor substrate;
Cells 1 and 2 have a substantially rectangular shape;
The cell 1 has thirteenth and fourteenth p-channel field effect transistors and thirteenth and fourteenth n-channel field effect transistors,
Cell 2 has a fifteenth p-channel field effect transistor and eleventh, twelfth and fifteenth n-channel field effect transistors,
Cell 1 and Cell 2 have two power lines running in the horizontal direction, and the vertical heights of Cell 1 and Cell 2 are substantially equal,
A logic circuit characterized in that the vertical heights of the power lines of the cell 1 and the cell 2 are substantially equal. The logic circuit according to any one of claims 5 to 6,
Having at least cell 1 and cell 2 on a semiconductor substrate;
Cells 1 and 2 have a substantially rectangular shape;
The cell 1 has 20th and 21st p-channel field effect transistors and 20th and 21st n-channel field effect transistors,
The cell 2 has a 25th p-channel field effect transistor and 23rd, 24th and 25th n-channel field effect transistors,
Cell 1 and Cell 2 have two power lines running in the horizontal direction, and the vertical heights of Cell 1 and Cell 2 are substantially equal,
A logic circuit characterized in that the vertical heights of the power lines of the cell 1 and the cell 2 are substantially equal. A pass transistor having a first field effect transistor having a source / drain path between a first node and a second node, and a second field effect transistor having a source / drain path between a third node and the second node. Circuit,
A multi-input CMOS logic circuit that outputs a control signal ;
An inverter circuit for generating an inverted signal of the control signal,
The control signal is input to the gate of the first field effect transistor, the inverted signal of the control signal generated by the inverter circuit is input to the gate of the second field effect transistor ,
The multi-input CMOS logic circuit is disposed in a first cell, the pass transistor circuit and the inverter circuit are disposed in a second cell,
The semiconductor integrated circuit device, wherein the first cell and the second cell are arranged along a power supply wiring for supplying power to the pass transistor circuit, the multi-input CMOS logic circuit, and the inverter circuit. In claim 22,
The multi-input CMOS logic circuit includes first and second input nodes, first and second p-channel field effect transistors, and first and second n-channel field effect transistors,
The first p-channel field effect transistor is connected in series with the first n-channel field effect transistor;
The second p-channel field effect transistor is connected in series with the second n-channel field effect transistor;
The first input node is connected to the gate of the first p-channel field effect transistor and the gate of the first n-channel field effect transistor;
The semiconductor integrated circuit device, wherein the second input node is connected to a gate of the second p-channel field effect transistor and a gate of the second n-channel field effect transistor. In either claim 22 or claim 23,
A semiconductor integrated circuit device, wherein a width in a direction perpendicular to the power supply wiring of the first cell is equal to a width in a direction perpendicular to the power supply wiring of the second cell. In claim 24,
The inverter circuit includes a semiconductor integrated circuit device which is constituted by the first 3p-channel field effect transistor and the 3n-channel field effect transistor. A pass transistor having a first field effect transistor having a source / drain path between a first node and a second node, and a second field effect transistor having a source / drain path between a third node and the second node. Circuit,
A multi-input CMOS logic circuit ;
An inverter circuit,
The output of the multi-input CMOS logic circuit is input to the first node,
A control signal is input to the gate of the first field effect transistor, an inverted signal of the control signal generated by the inverter circuit is input to the gate of the second field effect transistor,
The multi-input CMOS logic circuit is disposed in a first cell, the pass transistor circuit and the inverter circuit are disposed in a second cell,
The semiconductor integrated circuit device, wherein the first cell and the second cell are arranged along a power supply wiring for supplying power to the pass transistor circuit, the multi-input CMOS logic circuit, and the inverter circuit. In claim 26,
The multi-input CMOS logic circuit includes first and second input nodes, first and second p-channel field effect transistors, and first and second n-channel field effect transistors,
The first p-channel field effect transistor is connected in series with the first n-channel field effect transistor;
The second p-channel field effect transistor is connected in series with the second n-channel field effect transistor;
The first input node is connected to the gate of the first p-channel field effect transistor and the gate of the first n-channel field effect transistor;
The semiconductor integrated circuit device, wherein the second input node is connected to a gate of the second p-channel field effect transistor and a gate of the first n-channel field effect transistor. In claim 26 or claim 27,
The first cell of the power supply lines and the vertical width and the upper Symbol second cell the power supply wires and vertical width are equal the semiconductor integrated circuit device. In claim 28,
The inverter circuit includes a semiconductor integrated circuit device which is constituted by the first 3p-channel field effect transistor and the 3n-channel field effect transistor. A pass transistor having a first field effect transistor having a source / drain path between a first node and a second node, and a second field effect transistor having a source / drain path between a third node and the second node. Circuit,
A first inverter circuit having the second node connected to its input;
A multi-input CMOS logic circuit in which the output of the first inverter circuit is connected to at least one input thereof ;
A second inverter circuit,
A control signal is input to the gate of the first field effect transistor, an inverted signal of the control signal generated by the second inverter circuit is input to the gate of the second field effect transistor,
The multi-input CMOS logic circuit is disposed in a first cell, the pass transistor circuit and the second inverter circuit are disposed in a second cell,
The semiconductor integrated circuit device, wherein the first cell and the second cell are arranged along a power supply wiring for supplying power to the pass transistor circuit, the multi-input CMOS logic circuit, and the second inverter circuit . In claim 30,
The multi-input CMOS logic circuit includes first and second input nodes, first and second p-channel field effect transistors, and first and second n-channel field effect transistors,
The first p-channel field effect transistor is connected in series with the first n-channel field effect transistor;
The second p-channel field effect transistor is connected in series with the second n-channel field effect transistor;
The first input node is connected to the gate of the first p-channel field effect transistor and the gate of the first n-channel field effect transistor;
The semiconductor integrated circuit device, wherein the second input node is connected to a gate of the second p-channel field effect transistor and a gate of the second n-channel field effect transistor. In claim 30 or claim 31,
A semiconductor integrated circuit device, wherein a width in a direction perpendicular to the power supply wiring of the first cell is equal to a width in a direction perpendicular to the power supply wiring of the second cell . In claim 32,
The second inverter circuit, a semiconductor integrated circuit device which is constituted by the first 3p-channel field effect transistor and the 3n-channel field effect transistor.

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