JPH10200394A - Logic circuit in combination with path transistor circuit and cmos circuit and its combination method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a logic circuit with a small area and excellent circuit characteristics such as a delay time and power consumption by combining the path transistor(TR) logic circuit and the CMOS logic circuit. SOLUTION: A binary tree is generated from a logic function and the path TR logic circuit is formed by mapping a path TR selector with two inputs, one output and one control input onto each node of the tree. In the path TR logic circuit, each of the path TR selectors one input of the two outputs other than the control signal input of which is fixed to a logical 1 or 0 and acting like a NAND or NOR logic is replaced with a CMOS gate such as a NAND or a NOR equivalent to its logic function and when the replaced CMOS gate provides a more optimum circuit characteristic (for example, a smaller area, or a smaller delay time or smaller power consumption), the path TR selector is replaced with a CMOS gate. Thus, the logic circuit with a small area, a small delay time and less power consumption is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a small area, high speed, low power consumption logic circuit combining a pass transistor circuit and a CMOS circuit, and also relates to a combination of a pass transistor circuit and a CMOS circuit from a logical function. The present invention relates to a method for synthesizing a small-area, high-speed, low-power-consumption logic circuit.

[0002]

2. Description of the Related Art In a pass transistor logic circuit, which is one of the logic circuits, one transistor can have various logic functions. For this reason, the pass transistor logic circuit is configured well, all conventional CMOS logic circuits are replaced with pass transistor logic circuits, and the number of transistors in one LSI that is increasing in scale is greatly reduced.
Many studies have been published aiming at reducing the area and power consumption. In it, the binary decision diagram from the logical function
(Binary Decision Diagram), there is a method in which each node is replaced with a pass transistor selector having two inputs, one output and one control input, and a pass transistor logic circuit having a target logic function is synthesized. The binary decision diagram is a graphical representation of a logical function by a binary tree of nodes having two branches called one branch and zero branch, and has a property that a complicated logical function can be represented simply. Therefore, this method is attracting attention as a method for synthesizing a compact pass transistor logic circuit having a target logic function with a small number of transistors.

[0003] For example, Proceeding of IEEE 1994 Custom
Integrated Circuits Conference, pp.603-606 (hereafter,
In the literature 1, a two-input one-output pass transistor selector is composed of only n-channel field-effect transistors, and if necessary, a buffer inverter for reducing the delay time is inserted, and the desired pass transistor logic is selected. Methods for synthesizing circuits have been proposed. Conventional CMOS logic circuits require the same number of inferior p-channel field-effect transistors as n-channel field-effect transistors. However, in the pass transistor logic circuit synthesized by the method of Document 1, most of the circuit other than the buffer inverter can be constituted only by a high-performance n-channel field effect transistor. For this reason, conventional CM
A circuit having smaller area, delay time, and lower power consumption than the OS logic circuit and having excellent performance can be obtained.

[0004] IEEE Symposium on Low Power Elec
tronics, 1995, pp. 14-15 (hereinafter referred to as Reference 2) proposes a method that further develops Reference 1.
This method is characterized in that a pass transistor logic circuit is synthesized from a multi-stage binary decision diagram (hereinafter, referred to as a multi-stage binary decision diagram). The multi-stage BDD is created by the following procedure.

(1-1) A BDD is created from a logical function.

(1-2) On the created BDD,
The node pointed to by the 0 branch or 1 branch is different, but the other graphs having exactly the same shape (isomorphic subtree) are extracted, and a node controlled by the isomorphic subtree is newly created.

Due to the effect of (1-2), a logical function can be expressed with fewer nodes in a multistage BDD than in a normal BDD. For this reason, it is possible to synthesize a pass transistor logic circuit having a target logic function with fewer transistors than in Reference 1. Also,
Since the number of nodes connected in series is also reduced, the number of stages of the combined pass transistor circuit is reduced. For this reason, it is possible to synthesize a pass transistor logic circuit having a smaller delay time and a smaller area and lower power consumption than in Reference 1.

In addition, IEICE Technical Report VLD9
5-115, Vol. 95, No. 119, pp. 91-96 (hereinafter referred to as Reference 3)
Has proposed a method aimed at synthesizing a pass transistor logic circuit with low power consumption. In this method, as in Reference 2, a pass transistor logic circuit is synthesized from a multi-stage binary decision diagram, but a pass transistor logic circuit with lower power consumption is further reduced by narrowing the buffer inverter for delay time improvement to the minimum necessary. Can be synthesized.

Incidentally, regarding the pass transistor circuit,
JP-A-1-129611, JP-A-1-216622
JP-A-1-256219, JP-A-7-13085
No. 6, etc.

Further, a method of synthesizing a pass transistor logic circuit is described in Japanese Patent Application Laid-Open No. 7-168874 and Japanese Patent Application No. 8-97132.

[0011]

SUMMARY OF THE INVENTION The present inventors have created a BDD for some logic functions and actually synthesized pass transistor logic circuits by the methods described in References 1, 2, and 3. . As a result, for a logical function,
It is possible to synthesize a pass-transistor logic circuit having a smaller number of transistors and a smaller area, delay time, and power consumption than a conventional CMOS logic circuit. However, it has been found that the area, the delay time, and the power consumption may be increased with respect to another logic function.

For example, when a simple two-input NAND logic is synthesized by a pass transistor logic circuit according to the method described in References 1, 2, and 3, a circuit of six transistors C1 in FIG. 4 is obtained. However, a CMOS logic circuit is a simpler circuit with four transistors (C2 in FIG. 4). Also, two-input NOR
Regarding the logic, the pass transistor logic circuit is a circuit with six transistors (C3 in FIG. 4), but the CMOS logic circuit is a circuit with four transistors (C4 in FIG. 4).

As shown in FIG. 4, NAND logic and NO
In the R logic, the performance is better when the circuit is configured by CMOS gates for the area and the delay time other than the power consumption. As described above, the pass transistor selector circuit is suitable for not the NAND logic or the NOR logic but the selector logic of selecting a certain signal with another signal, instead of the NAND logic or the NOR logic. On the other hand, NAND logic and NOR logic are basic circuits of a CMOS circuit, and it can be said that a CMOS circuit can form a logic circuit with better performance. However, for power consumption, N
Also in the AND logic and the NOR logic, the pass transistor circuit can be made smaller.

Although this was overlooked in the study of the conventional pass transistor logic circuit, both the pass transistor circuit and the CMOS circuit have their respective strengths and weaknesses. Is not superior in In addition, whether the pass transistor circuit or the CMOS circuit is superior is determined by the logic circuit to be synthesized,
It also depends on which of the circuit characteristics of the delay time and the power consumption is prioritized.

Also, unlike the era when the logic circuit was designed manually, HDL (Hardware Description Lang) is now used.
logic is designed in a high-level language such as uage), so logic that is often used in HDL, combining If then else (that is, corresponding to selector logic) and Boolean algebra, can be expressed in a compact logic circuit. It is very important to be able to achieve it.

As described above, for any logic, and regardless of the circuit characteristics such as area, delay time, and power consumption, in order to create a logic circuit having excellent circuit characteristics, only a pass transistor circuit is required. It is not possible, and a pass transistor / CMOS cooperative logic circuit is created by combining the advantages of both a pass transistor circuit and a CMOS circuit so that the pass transistor circuit and the CMOS circuit cooperate well in one logic circuit. There is a need. Providing a method for automatically synthesizing such a high-performance pass transistor / CMOS cooperative logic circuit in a computer system is an LSI with a small area, a small delay time, and low power consumption. To make chips,
It has a very important meaning.

Furthermore, when a pass transistor logic circuit is synthesized from a multi-stage binary decision diagram by the method described in Reference 2, it is possible to further reduce the number of transistors. In some cases, it was late. The inventors independently analyzed this and found that there were the following problems. That is,
In a pass transistor logic circuit synthesized from a multi-stage BDD, a circuit having a configuration in which a certain pass transistor selector is connected to a control input of a subsequent pass transistor selector via a buffer inverter is formed. In this case, since the buffer inverter and the inverter in the subsequent pass transistor selector are connected in series, it has been found that the delay time is inevitably delayed. In other words, this method of synthesizing a pass transistor logic circuit from a multistage binary decision diagram, when the conditions of the delay time are severe, the above-mentioned problem of the delay time becomes a bottleneck,
It has been found that there are cases where it is not practical.

An object of the present invention is to provide a conventional logic circuit composed only of pass transistors or a CMOS circuit only by combining the advantages of pass transistor circuits and CMOS circuits for any kind of logic. Provide a pass transistor / CMOS cooperative logic circuit with better circuit characteristics such as area, delay time, power consumption, etc. than a logic circuit that has been improved, and also provide a pass transistor / CMOS cooperative logic circuit with such superior performance in a computer system. Is to provide a method of automatically synthesizing.

It is another object of the present invention to provide a pass transistor circuit and a CMOS circuit for any type of logic.
By properly combining the advantages of each, the problem of the delay time of a logic circuit synthesized only with pass transistors from the conventional multistage binary decision diagram is solved, and the delay time is small and the number of transistors is small, the area or the delay time, An object of the present invention is to provide a pass transistor / CMOS cooperative logic circuit having excellent circuit characteristics such as power consumption and a method for synthesizing the same.

Another object of the present invention is to provide a method for synthesizing a logic circuit more desirable in terms of area, or circuit characteristics such as delay time and power consumption, or a combination thereof by successfully combining a pass transistor circuit and a CMOS circuit. To provide.

[0021]

To achieve the above object, in a preferred embodiment of the present invention, the gate is controlled by a first input (IN1) and a first operating potential point (VD
D), a first p-channel field-effect transistor (TP1) having a source-drain path connected between the first node (NP1) and a gate controlled by a second input (IN2), and a first operation The potential point (VDD) and the first node (N
P1), a second p-channel field-effect transistor (TP2) having a source-drain path connected thereto, a gate controlled by a first input (IN1), and a first node (NP1) and a fourth node (TP1). NP4), a first n-channel field-effect transistor (TN1) having a source-drain path connected thereto, a gate controlled by a second input (IN2), a fourth node (NP4) and a second operation. A second n-channel field-effect transistor (TN2) having a source-drain path connected to the potential point (GND),
A third p-channel field effect transistor (TP3) having a gate controlled by a first node (NP1) and a source / drain path connected between a first operating potential point (VDD) and a second node (NP2) And a third n-channel field-effect transistor whose gate is controlled by the first node (NP1) and whose source / drain path is connected between the second node (NP2) and the second operating potential point (GND). TN3) and a fifth n-channel field effect transistor (TN5) whose gate is controlled by the second node (NP1) and whose source / drain path is connected between the third input (IN3) and the third node (NP3). ), And a sixth n-channel whose gate is controlled by the first node (NP1) and whose source / drain path is connected between the fourth input (IN4) and the third node (NP3). Le field-effect transistor (TN
6), the gate is controlled by the third node (NP3), the first operating potential point (VDD) and the first output (OUT
1) the fourth p having a source-drain path connected between
The channel field effect transistor (TP4) and the gate are controlled by the third node (NP3), and the first output (O
A logic circuit including a Boolean selector logic comprising a fourth n-channel field effect transistor (TN4) having a source-drain path connected between UT1) and a second operating potential point (GND) (FIG. 1) It is.

According to another preferred aspect of the present invention, the gate is controlled by the tenth input (IN10), and the source-drain path is provided between the first operating potential point (VDD) and the tenth node (NP10). A tenth p-channel field-effect transistor (TP10) connected to
Of the 10th node (N
P10) and a tenth n-channel field-effect transistor (TN10) having a source-drain path connected between the second operating potential point (GND) and a gate controlled by a tenth node (NP10), and an eleventh node (NP10). Input (IN1
1) and an eleventh n-channel field effect transistor (TN11) having a source / drain path connected between the eleventh node (NP11) and a gate connected to a tenth input (IN1).
0), the twelfth input (IN12) and the first
A twelfth n-channel field-effect transistor (T) having a source-drain path connected to one node (NP11).
N12) and a fifteenth p-channel field effect in which the gate is controlled by the eleventh node (NP11) and the source / drain path is connected between the first operating potential point (VDD) and the twelfth node (NP12). Transistor (TP15)
And the gate is controlled by the eleventh node (NP11), and the twelfth node (NP12) and the second operating potential point (G
ND) connected to the source / drain path
The n-channel field effect transistor (TN15) and the gate are controlled by the twelfth node (NP12).
Operating potential point (VDD) and the tenth output (OUT10)
And a gate controlled by a twelfth node (NP12), a tenth output (OUT10) and a thirteenth node (NP13). A gate of which is controlled by a thirteenth input (IN13), a first operating potential point (VDD), and a tenth operating potential point (VDD). A thirteenth p-channel field-effect transistor (TP13) having a source-drain path connected to the output (OUT10), and a gate controlled by a thirteenth input (IN13) to provide a tenth output (OUT1).
0) and a logic circuit (FIG. 2) including a Boolean selector logic comprising a thirteenth n-channel field effect transistor (TN13) having a source-drain path connected between the second operating potential point (GND). is there.

According to another preferred aspect of the present invention, the gate is controlled by the twentieth input (IN20), and the source-drain path is provided between the first operating potential point (VDD) and the twentieth node (NP20). Is connected to the twentieth p-channel field effect transistor (TP20) and the gate is
A twenty-first p-channel field effect transistor (TP21) controlled by an input (IN21) of which the source and drain paths are connected between a first operating potential point (VDD) and a twentieth node (NP20); Is controlled by a twentieth input (IN20), and the twentieth node (NP2)
0) and a twentieth n-channel field-effect transistor (TN20) having a source-drain path connected between the twenty-fourth node (NP24) and a gate connected to a twenty-first input (IN2).
1) is controlled by the 24th node (NP24) and the 2nd node
A twenty-first n-channel field-effect transistor (TN21) having a source-drain path connected to the first operating potential point (GND), and a gate controlled by a twenty-second input (IN22). (P2) a p-channel field-effect transistor (TP2) having a source-drain path connected between (VDD) and the 22nd node (NP22).
2) a 22nd n-channel electric field whose gate is controlled by the 22nd input (IN22) and whose source / drain path is connected between the 22nd node (NP22) and the second operating potential point (GND) Effect transistor (TN22)
And the gate is controlled by the 22nd node (NP22), the 23rd input (IN23) and the 23rd node (NP2)
23) an n-channel field-effect transistor (TN23) having a source-drain path connected between it and the gate, the gate being controlled by a twenty-second input (IN22);
A twenty-fourth n-channel field-effect transistor (TN24) having a source-drain path connected between the node (NP20) and the twenty-third node (NP23);
A twenty-fifth p-channel field effect transistor (TP25) controlled by the three nodes (NP23) and having a source-drain path connected between the first operating potential point (VDD) and the twentieth output (OUT20); Is controlled by the 23rd node (NP23), and the twentieth output (OUT2
0) and a logic circuit including a Boolean selector logic comprising a twenty-fifth n-channel field effect transistor (TN25) having a source-drain path connected between the second operating potential point (GND) (FIG. 3) It is.

In order to automatically synthesize a logic circuit obtained by combining such a pass transistor circuit and a CMOS circuit with a computer system, the present invention creates a binary decision graph or a multi-stage binary decision graph from a logical function, and assigns the node to the node. A pass transistor logic circuit is created by mapping all the data to the pass transistor selector having two inputs, one output and one control input. In the pass transistor logic circuit, one of the two inputs is fixed to a logical constant of 1 or 0, and the pass transistor operates as NAND logic or NOR logic (or AND logic, OR logic) Replace the selector with a logically equivalent CMOS gate such as NAND or NOR, calculate the values of the circuit characteristics such as area, delay time, and power consumption. If closer to optimal, replace the pass transistor selector with a CMOS gate. The above operation is tried for all the pass transistor selectors to synthesize a pass transistor / CMOS cooperative logic circuit having predetermined circuit characteristics that are optimal. As the circuit characteristics used for such optimization, for example, area, delay time, power consumption, or an appropriate combination thereof are used.

In another desirable aspect of the present invention, a binary decision graph or a multistage binary decision graph is created from a logical function, and two branches (zero branches,
A CMOS gate such as a NAND or a NOR which is logically equivalent to the node is mapped to a node in which only one of them is fixed to the logical constant 1 or 0. Also,
For other nodes, a 2-input / 1-output pass transistor selector is mapped and a pass transistor / CMOS
Synthesize a cooperative logic circuit.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The pass transistor / CMOS cooperative logic circuit of the present invention and a method of synthesizing the same will be described in more detail with reference to some embodiments shown in the drawings. In addition,
In the following, the same reference numbers refer to the same or similar ones.

<Embodiment 1> The pass transistor of the present invention /
One embodiment of the CMOS cooperative logic circuit will be described with reference to FIG. FIGS. 5A, 5B, and 5C show the case where the logic given by the following logical functions is configured by the pass transistor / CMOS cooperative logic circuit of the present invention and the configuration formed by the conventional pass transistor logic circuit and the CMOS logic circuit. It is the figure which compared the case where it did. Note that the inverters and CMOS gates indicated by the simplified symbols in FIG. 5 are configured by the transistor circuits shown in FIG. A out = (B * (C * D) + A * C * D) b out = (A * (B * D + B * C)) c out = (B * (C * D) + B in FIG. 5) * A) In FIG. 5A, the pass transistor / CMOS cooperative logic circuit of the present invention is a circuit including an inverter I50, a pass transistor selector S50, and a CMOS gate G50. On the other hand, in the conventional pass transistor logic circuit, the inverters I50 and I51 and the pass transistor selector S5
0 and S51 are required. In addition, a CMOS logic circuit requires inverters I52 and I54 and CMOS gates G50 to G53. As shown in FIG. 5A, in the conventional pass transistor logic circuit, NAND logic and NOR logic which are not suitable for the pass transistor circuit must be formed by the pass transistor circuit (S51). Further, in the conventional CMOS logic circuit, a selector logic that is not suitable for being constituted by a CMOS circuit must also be constituted by a CMOS circuit (G51).
To G53). In contrast, the pass transistor of the present invention / C
In the MOS cooperative logic circuit, a portion corresponding to the selector logic in the given logic is formed by a pass transistor selector (S50) suitable for the selector logic, and other NANs are provided.
The D and NOR logic parts can be formed into circuits with CMOS gates (G50) suitable for them. As described above, the S-transistor / CMOS cooperative logic circuit of the present invention has a selector logic and a NAND logic.
Logic and NOR logic (AND logic or OR logic) can be implemented in a compact circuit. For this reason,
In the pass transistor logic circuit, there are 14 transistors,
Whereas a CMOS logic circuit requires 20 transistors, the pass transistor / CMOS cooperative logic circuit of the present invention can achieve a desired logic function with 11 transistors, and has a small area and excellent performance with low power consumption. It can be seen that it is. Further, in the pass transistor / CMOS cooperative logic circuit of the present invention, the selector S5 of the pass transistor logic circuit is used.
1. Since the portion corresponding to the inverter I51 can be reduced to one CMOS gate G50, the delay time taken by the inverter in the selector S51 → the selector S51 → the inverter I51 for the buffer is reduced by the CMOS gate G50. The delay time can be reduced to only G50. Further, since the inverter having a slow delay time in the selector S51 of the pass transistor logic circuit can be removed from the path, the pass transistor / CM of the present invention can be removed.
The OS cooperative logic circuit can significantly reduce the delay time as compared with the pass transistor logic circuit. Also, CMOS
Compared to the logic circuit, the CMOS logic circuits G51 to G5
3, the paths of I52 and I54 can be shortened to S50 and I50 in the pass transistor / CMOS cooperative logic circuit of the present invention, so that the pass transistor / CMOS cooperative logic circuit of the present invention has a smaller delay time. FIG. 6 shows a layout example of the pass transistor / CMOS cooperative logic circuit of the present invention shown in FIG. 5A. In FIG. 6, cell 1 is a CMOS circuit NA.
Cell 2 corresponds to the ND gate (G50), and cell 2 corresponds to the pass transistor selector (S50). As shown in FIG. 6, the height h1 of the cell 1 and the height h4 of the cell 2, the widths h2 and h3 of the power lines (VDD and GND) of the cell 1, and the power line (VDD) of the cell 2 , And GND), it is possible to actually manufacture a logic circuit in which the pass transistor circuit and the CMOS circuit are combined into one circuit for the first time. This is the same in the following embodiments.

In the logic of FIG. 5B, in the pass transistor / CMOS cooperative logic circuit of the present invention, the inverter I6 is used.
0, pass transistor selector S60, CMOS gate G6
A circuit having a target logic function can be constituted by 11 transistors each including 0. On the other hand, the pass transistor logic circuit requires inverters I60 and I61 and pass transistor selectors S60 and S61, and requires 14 transistors. In CMOS logic circuits,
Inverters I62 and I64, CMOS gates G60 to G63
And 20 transistors are required. That is,
Also in this case, it can be seen that the pass transistor / CMOS cooperative logic circuit of the present invention has the best performance. Regarding the delay time, in the pass transistor / CMOS cooperative logic circuit of the present invention, the selector S61 of the pass transistor logic circuit,
The part corresponding to the inverter I61 is replaced by one CMOS gate G
60, the delay time required by the inverter in the selector S61 of the pass transistor logic circuit → the selector S61 → the buffer inverter I61 can be reduced to the delay time of the CMOS gate G50 alone. , The delay time can be greatly reduced as compared with the pass transistor logic circuit. Also, compared to the CMOS logic circuit, the CMOS logic circuits G61 to G63, I62, I62
The path of the portion 64 is a pass transistor / CMOS of the present invention.
Since the cooperative logic circuit can be shortened to S60 and I60, the pass transistor / CMOS cooperative logic circuit of the present invention has a smaller delay time.

In FIG. 5C, in the pass transistor / CMOS cooperative logic circuit of the present invention, a circuit having an intended logic function is composed of 11 transistors each including an inverter I70, a pass transistor selector S70, and a CMOS gate G70. Can be configured. On the other hand, the pass transistor logic circuit requires inverters I70 and I71 and pass transistor selectors S70 and S71, and requires 14 transistors. Further, a CMOS logic circuit requires inverters I72 and I74 and CMOS gates G70 to G73, and requires 20 transistors. That is, also in this case, it can be seen that the pass transistor / CMOS cooperative logic circuit of the present invention has the best performance. Fig. 5 also shows the delay time.
Of the present invention for the same reason as a and b in FIG.
OS coordination logic circuit is the smallest.

<Embodiment 2> In the above embodiment, the pass transistor / CMOS cooperative logic circuit of the present invention has been described by taking simple logic as an example. In this embodiment, for a more complicated logic, a high-performance pass transistor / CMOS cooperative logic circuit having excellent circuit characteristics such as area, delay time, and power consumption is automatically formed by the computer system shown in FIGS. A method of synthesizing will be described.

(1) Overall Configuration of System In FIG. 8, a designer inputs a logic circuit specification 10 in which a specification of a logic function of a target semiconductor integrated circuit is described.
The logic circuit specification 10 describes a logic function that describes the logic function of the circuit. In addition, it also describes target values of circuit characteristics such as the area, delay time, and power consumption of the circuit, and information on which circuit characteristics are to be prioritized.
The pass transistor / CMOS cooperative logic circuit synthesis program 100 unique to the present embodiment refers to the library 11 based on the information described in the logic circuit specification 10 and targets the circuit characteristics such as area, delay time, and power consumption. The pass transistor / CMOS cooperative logic circuit 12 having the logic function of the logic circuit specification 10 is synthesized so as to satisfy the value. The automatic layout program 160 refers to the library 11 to determine an optimal layout for the logic circuit, and creates layout data 20. Mask data creation program 170
Determines a plurality of mask patterns for generating the synthesized logic circuit using the semiconductor integrated circuit technology according to the layout data 20, and generates mask data 21 representing the mask patterns. Semiconductor manufacturing equipment 1
80 manufactures a semiconductor integrated circuit having a target logic function using the mask data 21. 100, 160, 17
Each program of 0 is executed on a different computer assigned to each program. Of course, these programs can be executed on the same computer.

FIG. 7 shows a pass transistor / CMOS of the present invention.
1 shows a schematic structure of a cooperative logic circuit synthesis program 100 and a computer system for executing the program. The computer system includes an input device, for example, a keyboard 1,
It comprises a central processing unit (CPU) 2, a display device (CRT) 3, a magnetic tape device 4, and a magnetic disk device 5 for storing a logic circuit synthesis program 100. Program 10
0 includes a binary decision diagram creation routine 110, a pass transistor selector mapping routine 120, and a CMOS gate assignment routine 130. This program is loaded from the magnetic disk device 5 to the CPU 2 by the designer giving an instruction from the keyboard 1, and
Be executed. The pass transistor / CMOS cooperative logic circuit synthesized by the program 100 is displayed on the CRT 3 and passed to the automatic layout program 160 in FIG.

In this embodiment, a binary decision diagram is created,
Of the pass transistor circuits synthesized by mapping the pass transistor selectors, find a part where the performance is better if changed to a CMOS circuit, reassemble that part with a CMOS circuit, and use the conventional pass transistor alone logic circuit or CMOS The feature is that a pass transistor / CMOS cooperative logic circuit having better performance than a single logic circuit is synthesized.
Specifically, one of the two inputs is fixed to a logical constant of 1 or 0, and a pass transistor selector operating as a NAND logic or a NOR logic (AND logic or OR logic) is logically changed. Replace with CMOS gate equivalent to NAND, NOR, etc., calculate the values of circuit characteristics such as area, delay time, power consumption, etc. If the value of the predetermined circuit characteristic is closer to optimal if it is better to replace with CMOS gate By replacing the pass transistor selector with a CMOS gate, the part that performs better with a CMOS circuit is replaced with a CMOS circuit.
Reassemble with circuit. Hereinafter, each routine of the present embodiment will be described using the following logical function as an example.

Out1 = B * A + C * A + (I * F + D) * (D + (H + E)
* (E + G)) out2 = B + ((I * F + D) * (D + (H + E) * (E + G))) When the CMOS logic circuit is synthesized by the method, G100 to G in FIG.
A circuit composed of 111 is obtained.

(2) Binary decision graph creation routine 110 This routine 110 generates a binary decision graph from the logic circuit specification 10. The logic circuit specification 10 includes input variables and output variables corresponding to input signals and output signals of a logic circuit to be synthesized, and a logic function representing a logic function of the circuit.

When a BDD is created from the above logical functions, a graph composed of nodes N100 to N111 in FIG. 11 is created. In the multi-stage BDD shown in FIG. 11, the nodes N104 to N109 are shared and concatenated to form a multi-stage, thereby reducing the number of nodes compared to the ordinary BDD. To create a small BDD with a small number of nodes,
The order of the input variables when creating the graph is very important, and the order of the input variables can be determined using an existing well-known binary decision diagram creation tool.

(3) Pass Transistor Selector Mapping Routine 120 This routine converts each node of the BDD created by the BDD creation routine 110 according to the mapping rule of FIG. A pass transistor logic circuit is generated by mapping to a selector or an inverter. Furthermore, a buffer inverter is inserted as needed.

As shown at node N1 in FIG.
If the branch and the zero branch are not connected to the logical constants 1 and 0, the n-channel field-effect transistors T0 and T0,
A two-input one-output pass transistor selector S0 composed of T1 and an inverter I0 is made to correspond. An input variable A corresponding to a node of the BDD is assigned to a control input of the pass transistor selector S0, and an output of a node connected to one branch is assigned to an input in1 selected when the control input is 1. assign. The output of the node connected to the 0 branch is assigned to the input in0 selected when the control input is 0.

When one branch is connected to the logical constant 1 and the 0 branch is connected to the logical constant 0 as in the node N2 in FIG. 12B, the output of this node is the input variable of the node. When A is 1, 1 is output, and when A is 0, 0 is output. That is, the input signal A may be directly connected to a subsequent circuit.

When one branch is connected to a logical constant 0 and the 0 branch is connected to a logical constant 1 as in a node N3 shown in FIG. 12C, the output of this node is When the input variable A is 1, 0 is output, and the input variable A is 0.
In the case of, 1 is output. That is, the input signal A may be inverted by an inverter and connected to a subsequent circuit.

By performing the mapping as described above, a pass transistor logic circuit having the same logic function as the BDD is synthesized. When a pass transistor logic circuit is synthesized from the BDD of FIG. 11, a pass transistor logic circuit composed of pass transistor selectors S100 to S105 and inverters I100 to I105 shown in FIG. 13 is synthesized. In this circuit, I100, I10
3, I105 is a buffer inverter. In the binary decision diagram of FIG. 11, nodes N102, N103, N1
09 corresponds to b in the mapping rule in FIG. 12, and the nodes N106, N107, and N111 correspond to c in FIG. Other nodes correspond to FIG.

(4) CMOS Gate Assignment Routine 130 In this routine, among the pass transistor logic circuits generated by the pass transistor selector mapping routine 120, the circuit having the area, the delay time, the power consumption, etc., which is reassembled with the CMOS gates is better. NA is thought to improve the characteristics
The pass transistor selector operating as ND logic or NOR logic (or AND logic or OR logic) is reconfigured with CMOS gates.

First, in the pass transistor logic circuit,
A pass transistor selector corresponding to the conversion patterns a to d in FIG. 14 is selected. In the pass transistor selectors shown in FIGS. 14A to 14D, one of the two inputs is fixed to VDD or GND potential, that is, NA is fixed to logical constant 1 or logical constant 0.
The selector operates as ND logic or NOR logic (or AND logic or OR logic). In the process 131, these pass transistor selectors are converted into CMOS gates according to the conversion pattern of FIG. The two-input NAND gate, the two-input NOR gate, and the inverter of the CMOS circuit shown by the symbols simplified by the conversion pattern in FIG. 14 are transistors T10 to T13, T20 to T23, and T30, respectively.
To 31 transistor level circuits.

As can be seen from the conversion pattern of FIG.
One pass transistor selector is not necessarily one CMOS
It is not converted to a gate, but usually requires an inverter for polarity adjustment. Therefore, according to the conversion pattern shown in FIG.
The conversion to the OS gate alone may result in a redundant inverter in which two inverters, which are originally present, and two inverters for polarity matching generated by the conversion, are connected in series. In other words, in order to generate a pass transistor / CMOS cooperative logic circuit having excellent circuit characteristics such as area, delay time, and power consumption, it is necessary to carry out inverter propagation and remove such useless inverters from the circuit. Also, by converting the pass transistor selector to a CMOS gate, the pass transistor selector
It is possible that a circuit that directly drives the OS gate may occur, but in this case, a pass transistor selector and
It is necessary to insert a buffer inverter between the CMOS gates. Although the above-described inverter propagation and buffer insertion processing are mutually contradictory processing, by simultaneously performing these two processings at the same time, a buffer inverter is inserted where necessary and there is no redundant inverter. Thus, a pass transistor / CMOS cooperative logic circuit having excellent circuit characteristics such as area, delay time, and power consumption can be produced (process 132).

Next, the circuit area, delay time, and power consumption are calculated for the circuit after the inverter propagation and buffer insertion. The cost of this circuit is calculated from the values of these circuit characteristics. The thus calculated cost of the circuit after conversion to the CMOS gate is compared with the previously calculated cost of the circuit before conversion to the CMOS gate (process 133). If the circuit converted to CMOS gate is more costly, select the circuit converted to CMOS gate and
If the cost of the pass transistor selector is higher than that of the gate, the circuit is returned to the circuit before conversion to the CMOS gate. In this way, the one with higher cost is selected from the CMOS gate and the pass transistor selector (process 13).
4). The above processes 131 to 134 are performed for all the pass transistor selectors corresponding to the conversion pattern in FIG. 14, and all the pass transistor selectors whose circuit characteristics are better when reassembled with CMOS gates are reassembled with CMOS gates. Create pass transistor / CMOS cooperative logic circuits with excellent circuit characteristics such as area, delay time, and power consumption.

In this method, by changing the definition of the cost determined from the area, the delay time, and the power consumption, it is possible to control which one of the area, the delay time, and the power consumption is to be emphasized in synthesizing the circuit. It is possible to For example, 1 in FIG.
When the area priority α, the delay time priority β, and the power consumption priority γ are set to α = 1, β = 0, γ = 0 at the cost defined by 35, the delay time and the power consumption are not considered. In addition, pass transistor / CMOS
The synthesis of the cooperative logic circuit is performed. Α = 0, β = 0, γ
By setting = 1, a pass transistor / CMOS cooperative logic circuit with the highest priority on power consumption is synthesized. Of course, it is also possible to combine all three circuit characteristics so as to improve them. If α = 1, β = 1, and γ = 1 are set, pass transistors are considered in consideration of area, delay time, and power consumption. / CMOS cooperative logic circuit is synthesized.

In the present embodiment, the pass transistor logic circuit shown in FIG. 13 is used in the following manner, with priority given to the area (α = 1, β = 0, γ = 0 at the cost defined by 135 in FIG. 9). A method for synthesizing a transistor / CMOS cooperative logic circuit will be described. In the circuit of FIG. 13, the selector S100 corresponds to the conversion pattern a of FIG.
It is converted to a gate, and the intermediate circuit of FIG. 15 is created. In the intermediate circuit of FIG. 15, the pass transistor selector S10
Since 1 directly drives the CMOS gate G100 as it is, the buffer inverter I108 is inserted. In addition, an inverter I107 is also inserted to match the polarity of the inverter I108. However, since the inverter I107 is a redundant inverter in which two inverters I101 and I102 are connected in series across the selector S101, the inverter I107 is removed by the inverter propagation process of process 132. Further, since the inverters I100 and I106 are redundant, they can be removed, and the pass transistor / CMOS cooperative logic circuit shown in FIG. 16 can be obtained. When the area of the circuit in FIG. 16 is calculated with reference to the library 11, it becomes 992 μ, and
The cost is also the same value as this area value. On the other hand, the area before reassembling the pass transistor selector S100 to the CMOS gate is 1164 μm, and the cost is also this value.
In other words, converting to a CMOS gate is more costly,
The circuit converted to the gate is selected. Of the remaining pass transistor selectors in the circuit of FIG.
Since 05 corresponds to the conversion pattern c in FIG. 14, it is similarly converted to a CMOS gate. However, the pass transistor selector S105 has a smaller area and is more costly if the circuit is configured by the pass transistor selector. ,
It is not reassembled into a CMOS gate. By the above processing, finally, the pass transistor / CMOS cooperative logic circuit of FIG. 17 is synthesized.

Table 1 shows pass transistor / CMOS cooperative logic circuits synthesized by the present invention from the logic functions of the second embodiment, CMOS logic circuits, pass transistor logic circuits, and
6 is a table comparing area, delay time, and power consumption of a logic circuit created by replacing a CMOS logic circuit with a pass transistor selector.

[0049]

[Table 1]

As shown in Table 1, the pass transistor / CMOS cooperative logic circuit synthesized by giving priority to area by the present method is a CMOS.
40% less area than logic circuit (Fig. 10) configured alone
The delay time and power consumption have been reduced by 5% and 60%, respectively. Although the delay time and the power consumption are inferior to those of the logic circuit (FIG. 13) composed of the pass transistor alone, the pass transistor / CM having a small target area is used.
It can be seen that the OS cooperative logic circuit has been synthesized.

As described in the first embodiment, what the pass transistor selector is best at is not the NAND logic or the NOR logic, but the selector logic that selects a certain signal with another signal. In this method, a BDD is created from a given logic function, a logic circuit composed of pass transistors alone is created, and the logic circuit uses
The pass transistor selector functioning as NAND logic or NOR logic (or AND logic or OR logic) is converted to a CMOS gate to reconfigure the logic circuit. By synthesizing a logic circuit in such a procedure, a pass transistor selector is assigned to a part corresponding to a selector logic in a given logic function, and the other NAND logic or NOR logic (or AND logic, OR logic) is equivalent to CMOS
Gates can be assigned. In this way, by properly using the pass transistor selector and the CMOS gate in appropriate portions respectively, a pass transistor / CMOS cooperative logic circuit that successfully combines the advantages of both the pass transistor selector and the CMOS gate is generated.

Even without using the logic circuit synthesizing method of the present invention, it is possible to make a logic circuit simply combining pass transistors and CMOS gates. For example, in the completely opposite procedure to this method, create a CMOS-only logic circuit, find a part of the CMOS gate that is suitable for a pass transistor selector, and convert that part to a pass transistor selector. And pass transistor and CMOS
A circuit combining gates can also be made. However, in CMOS logic circuits, all logic is NAND logic and NOR
Because it is composed of a combination of logic (or AND logic and OR logic), even if a given logic function has a selector logic part suitable for a pass transistor selector, it is difficult to find the corresponding part. . Actually, if the CMOS logic circuit (FIG. 10) synthesized from the logic function of this embodiment is replaced with a pass transistor selector, the pass transistor circuit shown in FIG. 18 is obtained. In this circuit, all of the pass transistor selectors have one of the two inputs fixed to VDD or GND potential, and are used as NAND logic and NOR logic which are not suitable for the pass transistor selector. . There is no single pass transistor selector used as the selector logic. Therefore, Table 1
As shown in FIG. 18, the circuit of FIG. 18 has all the circuits of the area, the delay time, and the power consumption more than any of the logic circuit using only CMOS (FIG. 10) and the logic circuit using only pass transistors (FIG. 13). Poor in properties. In this way, it is difficult to create a logic circuit that combines the advantages of pass transistors and CMOS gates from a CMOS logic circuit.
It can be seen that a circuit having lower performance than either the logic circuit constituted solely or the logic circuit constituted solely by the pass transistor is formed.

As can be seen from the above, it is impossible to successfully combine the advantages of the pass transistor selector and the CMOS gate simply by combining the CMOS gate and the pass transistor selector. A logic circuit with inferior circuit characteristics, which is a combination of only the disadvantages described above, is produced. That is, only by synthesizing the circuit according to the procedure shown in the present method, it becomes possible to synthesize a pass transistor / CMOS cooperative logic circuit that successfully combines the advantages of the pass transistor selector and the CMOS gate.

<Modification of Second Embodiment> In the second embodiment, an example in which the pass transistor selector is constituted by only n-channel field-effect transistors has been described. However, a pass transistor constituted by both p-channel and n-channel transistors is used. In a transistor selector (for example, a selector including transistors T200 to T203 and an inverter I200 shown in FIG. 20), a pass transistor / CMOS cooperative logic circuit having a small area can be formed by the method in the same manner as in the second embodiment. Is possible. This is exactly the same in the following embodiments. <Embodiment 3> In the present embodiment, taking the same logical function as the embodiment 2 as an example, unlike the embodiment 2, the delay time is given the highest priority (FIG. 9).
(Set to α = 0, β = 1, γ = 0 at the cost of 135) to synthesize a pass transistor / CMOS cooperative logic circuit. As in the second embodiment, a binary decision diagram is created by the binary decision diagram creation routine 110, and the pass transistor logic circuit of FIG. 13 is created by the pass transistor mapping routine 120. In the pass transistor logic circuit shown in FIG. 13, first, the pass transistor selector S100 is selected, and is converted into a CMOS gate by a process 131. Next, by the process 132, the buffer inverter is inserted into the output of the selector S101, the redundant inverter is removed, and the intermediate circuit of FIG. 16 is obtained. In the process 135, unlike the case of the second embodiment, the delay time of the circuit is calculated instead of the area, and the value of the delay time becomes the cost of the circuit. The delay time of the circuit (FIG. 13) before re-assembly into the CMOS gate is determined by the input F → selector S104 → selector S102 →
The delay time of the path from the buffer inverter I103 → the inverter in the selector S100 → the selector S100 → the buffer inverter I100. On the other hand, the corresponding path in the circuit reassembled by the CMOS gate (FIG. 16) is the input F →
Since the time is shortened to the selector S104 → the selector S102 → the buffer inverter I103 → the CMOS gate G100, the delay time is greatly reduced. For this reason, a circuit reassembled with CMOS gates is more costly.
In 4, the circuit reassembled by the CMOS gate is selected.

As described in the section to be solved by the invention, in a logic circuit of a single pass transistor composed of a multi-stage binary decision diagram, a certain pass transistor selector is connected to a subsequent pass transistor selector via a buffer inverter. (S102 → I103 → Inverter in S100 → S100 in FIG. 13). In this case, since the buffer inverter and the inverter in the subsequent pass transistor selector are connected in series, the delay time is inevitably delayed. However, as already described in the first embodiment, if the pass transistor selector in the subsequent stage can be successfully reassembled with CMOS gates as in this example, the slow inverter in the pass transistor selector can be omitted.
A logic circuit with a small delay time can be manufactured. Generally, the delay time can be reduced by reassembling a logic circuit including only a pass transistor into a pass transistor / CMOS cooperative logic circuit.

Of the remaining pass transistor selectors,
S104 and S10 correspond to the conversion pattern of FIG.
5 In the second embodiment where the area is the highest priority, only S104 is CM
Although reassembled by the OS gate, in this embodiment where delay time is given the highest priority, S105 is also converted to a CMOS gate. The reason is S
This is because, as in the case of 100, by converting the selector S105 to a CMOS gate, the slow inverter in the selector S105 can be eliminated, and the delay time can be further reduced. By the above operation, the pass transistor / CMOS cooperative logic circuit of FIG. 19 is finally obtained. Table 1
As shown in FIG. 10, in this embodiment, the delay time is reduced by 20% compared with the logic circuit (FIG. 10) constituted by CMOS alone by synthesizing the pass transistor / CMOS cooperative logic circuit by this method.
We have succeeded in reducing it soon. In addition, when compared with a logic circuit (FIG. 13) constituted only by pass transistors,
The delay time has been successfully reduced by nearly 10%.

<Embodiment 4> In this embodiment, Embodiments 2 and 3 will be described.
Contrary to this, the power consumption is made the highest priority (α = 0, β = 1, γ = 0 are set at the cost of 135 in FIG. 9) and the pass transistor / CM
A method of synthesizing an OS cooperative logic circuit will be described using the same logic function as in the second and third embodiments as an example. As in Examples 2 and 3,
The binary decision graph is created by the binary decision diagram creation routine 110, and the pass transistor logic circuit of FIG. 13 is created through the pass transistor selector mapping routine 120. In the pass transistor logic circuit of FIG. 13, first, the selector S100 is selected, and through the processes 131 and 132, the intermediate circuit of FIG. 16 is obtained. In the next process 133, unlike the second and third embodiments, the power consumption of the circuit is calculated, and the value of the power consumption becomes the cost of the circuit. The power consumption of the pass transistor / CMOS cooperative logic circuit in FIG. 16 is calculated to be 143 μW / MHz by referring to the library 11. On the other hand, the power consumption of the circuit (FIG. 13) before the conversion to the CMOS gate is 140 μW / MHz. Therefore, unlike the case of the second and third embodiments, the cost is better if the circuit is configured by the pass transistor selector. . In other words, what is selected in process 134 is not a circuit reassembled with CMOS gates,
This is a circuit composed of pass transistor selectors. FIG.
The remaining pass transistor selectors corresponding to the conversion pattern of No. 4 are S104 and S105. However, unlike the second and third embodiments, the circuit constituted by the pass transistor selector also consumes less power for these two selectors. ,
Good cost. For this reason, in this embodiment where power consumption is the highest priority, the pass transistor logic circuit of FIG. 13 is output as it is without being reassembled into a CMOS gate at all.

The reason for this is that the power consumption of the pass transistor selector is significantly smaller than that of the CMOS gate (less than half of that of the CMOS gate) as shown in the comparison result between the pass transistor selector and the CMOS gate in FIG. . This is because, in the pass transistor selector, the selector portion occupying the majority of the selector circuit is constituted only by the n-channel field-effect transistors, and the performance is degraded by reducing the number of inferior-performance p-channel field-effect transistors. It is possible to suppress the total gate width of the transistors in the pass transistor selector circuit without
This is because power consumption can be reduced.

<Embodiment 5> The pass transistor of the present invention /
In the method of synthesizing a CMOS cooperative logic circuit, it is considered that the performance of the circuit is better when converted to a CMOS gate.
The pass transistor selector operating as NOR logic (or AND logic or OR logic) is converted to a CMOS gate.
The pass transistor selector is converted to a CMOS gate, and a cost defined from the circuit area, delay time, and power consumption is calculated to determine whether the cost is improved. Therefore, according to the present method, as can be seen from the second, third, and fourth embodiments, the cost defined by the area, the delay time, and the power when the pass transistor / CMOS cooperative logic circuit is synthesized is changed. By changing the ratio between the pass transistor selector and the CMOS gate, it is possible to flexibly control various characteristics of the synthesized circuit. For example, FIG. 21 shows an example of a logic function (about 1000 gates in terms of CMOS gates) larger than those of the second, third, and fourth embodiments, and an area priority α and a power priority γ at a cost of 135 in FIG. Is changed from 0 to 1 to change the priority from the area priority to the power consumption priority, and synthesize the pass transistor / CMOS cooperative logic circuit. As can be seen from the results of FIG. 21, as the priority of power consumption increases, the ratio of pass transistors suitable for reducing power consumption increases, and a pass transistor / CMOS cooperative logic circuit that prioritizes power consumption is synthesized. You can see that it is. As described above, in the pass transistor / CMOS cooperative logic circuit synthesized by the present method, it is possible to easily control the characteristics of the synthesized circuit by controlling the ratio of the pass transistor selector and the CMOS gate. From this result, when a pass transistor / CMOS cooperative logic circuit is constructed with an actual large-scale logic, the three circuit characteristics of the area, the delay time, and the power consumption have the best balance. It became clear for the first time that the area ratio was about 10 to 60% of the entire circuit.

In the present method, the pass transistor selector is converted to a CMOS gate only when the circuit characteristics such as the area, delay time, and power consumption of the circuit are actually improved. For this reason, the present method synthesizes a logic circuit composed of only pass transistors for any logic function, or a pass transistor / CMOS cooperative logic circuit having better circuit characteristics than a logic circuit composed of only CMOS gates. It is possible. For example, FIG. 22 shows 12 types of logics (1000 to 1 in terms of CMOS gates) which are larger than the logic of FIG.
0000 gate) is a result of comparing a pass transistor / CMOS cooperative logic circuit synthesized by the present method with a pass transistor only logic circuit synthesized by the conventional method on the basis of a CMOS only logic circuit. As can be seen from the results, in the present method, for any logic, a pass transistor / CMOS cooperative logic that always has both the area and the power consumption superior to the conventional logic circuit using only the pass transistor and the logic circuit using only CMOS. It can be seen that the circuits can be synthesized.

Embodiment 6 In the above embodiment, the procedure for synthesizing the pass transistor / CMOS cooperative logic circuit by the program shown in FIG. 9 has been described. In this embodiment, FIG.
A method of synthesizing a pass transistor / CMOS cooperative logic circuit by the program shown in FIG. First, as in the second to fifth embodiments, first, the binary decision diagram creation routine 1
10 produces a binary decision diagram. Examples 2 to 5
The difference is that the pass transistor / CMOS cooperative logic circuit is directly synthesized from the BDD by the pass transistor selector / CMOS gate mapping routine 300 without passing through the pass transistor logic circuit.
The pass transistor selector / CMOS gate mapping routine 30 will now be described with reference to the binary decision diagram of FIG.
0 will be explained. First, in the process 301, the node N30
1 corresponds to b in FIG. 14 and is mapped to a CMOS gate according to the conversion pattern in FIG. 14 (G in FIG. 25).
301, I300). Other nodes N300, N30
2, N303 are mapped to the pass transistor selector and the inverter according to the mapping rule of FIG. 12 (S300, I301 of FIG. 25). Thus, the intermediate circuit of FIG. 25 is generated. In the intermediate circuit of FIG.
Since the inverters I300 and I301 are redundant inverters, they are removed by the process 302, and finally,
Are synthesized.

In the pass transistor / CMOS cooperative logic circuit synthesis program of the second to fifth embodiments (FIG. 9), once the pass transistor logic circuit is created, it operates as NAND logic or NOR logic (or AND logic, OR logic). The calculated pass transistor selector calculates a cost defined from circuit characteristics such as a circuit area, a delay time, and power consumption, and converts the cost to a CMOS gate when the cost is improved. Therefore, in any case, it is guaranteed that a logic circuit having excellent circuit characteristics can be synthesized. However, every time, the circuit area, delay time,
Since it is necessary to calculate the power consumption and the like, there is a disadvantage that it takes some time to synthesize the circuits. Also, as can be seen from FIG. 4, in most cases, the pass transistor selector operating as NAND logic or NOR logic (or AND logic or OR logic) has the characteristics of a circuit synthesized by conversion to a CMOS gate. Get better. Therefore, as in this embodiment,
Even if a pass transistor / CMOS cooperative logic circuit is created directly from a BDD without calculating costs, it can be expected that a logic circuit with excellent circuit characteristics can be synthesized. Actually, when the pass transistor logic circuit is synthesized from the BDD of FIG. 24, the circuit of FIG. 27 is synthesized.
Comparing with this circuit, it can be seen that the pass transistor / CMOS cooperative logic circuit (FIG. 25) synthesized by the present method has a smaller number of transistors, and an excellent logic circuit can be synthesized. As described above, according to the present method, it is possible to synthesize a pass transistor / CMOS cooperative logic circuit that combines the advantages of the pass transistor selector and the CMOS gate.

[0063]

As can be seen from the embodiment described above,
According to the present invention, no matter what logic the given logic circuit specification is, by combining the advantages of both the pass transistor circuit and the CMOS circuit well, the logic circuit and the pass transistor alone configured by the conventional CMOS alone can be used. It becomes possible to synthesize a pass transistor / CMOS cooperative logic circuit having better circuit characteristics such as area, delay time, and power consumption than the configured logic circuit.

Further, by adjusting the cost defined by the circuit area, the delay time, and the power consumption, the ratio of the pass transistor selector to the CMOS gate is changed, and the area of the combined pass transistor / CMOS cooperative logic circuit is changed. It is possible to flexibly control circuit characteristics such as delay time and power consumption.

[Brief description of the drawings]

FIG. 1 shows a preferred embodiment of the present invention.

FIG. 2 shows another preferred embodiment of the present invention.

FIG. 3 shows another preferred embodiment of the present invention.

FIG. 4 shows NAND logic and NO in a pass transistor selector.
FIG. 4 is a diagram illustrating a comparison between a case where the R logic is configured and a case where a CMOS gate is configured.

FIG. 5 is a diagram comparing a pass transistor / CMOS cooperative logic circuit according to the first embodiment of the present invention with a conventional pass transistor logic circuit and a CMOS logic circuit;

FIG. 6 is a layout example of a pass transistor / CMOS cooperative logic circuit according to the first embodiment of the present invention.

FIG. 7 is a schematic configuration diagram of a computer system for synthesizing a logic circuit and a logic circuit synthesis program used therein according to a second embodiment of the present invention.

FIG. 8 is a flowchart from the synthesis of a logic circuit to the manufacture of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 9 is a flowchart of a pass transistor / CMOS cooperative logic circuit synthesis program according to the second embodiment.

FIG. 10 is a circuit diagram of a CMOS logic circuit synthesized from the logic function of the second embodiment by a known method.

11 is a diagram showing an example of a multi-stage binary decision diagram created by the binary decision diagram creation routine of the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention in FIG. 9;

FIG. 12 is a diagram showing a mapping rule of a pass transistor selector.

13 is a circuit diagram of a pass transistor logic circuit created from the multi-stage binary decision diagram of FIG. 11 by a pass transistor mapping routine of the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention in FIG. 9;

FIG. 14 is a view showing a pattern of a pass transistor selector which is converted into a CMOS gate when a pass transistor / CMOS cooperative logic circuit is synthesized by the method of the present invention, and a conversion rule thereof.

FIG. 15 is a circuit diagram of an intermediate circuit created during the CMOS gate assignment routine of the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention in FIG. 9;

FIG. 16 is a circuit diagram of an intermediate circuit created during the CMOS gate assignment routine of the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention in FIG. 9;

17 is a circuit diagram of a pass transistor / CMOS cooperative logic circuit synthesized when the area is given the highest priority in the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention in FIG. 9;

FIG. 18 is a circuit diagram of a logic circuit created by converting a CMOS gate into a pass transistor selector from the CMOS logic circuit of FIG. 10;

19 is a circuit diagram of a pass transistor / CMOS cooperative logic circuit synthesized when the delay time is set to the highest priority in the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention in FIG. 9;

FIG. 20 is a circuit diagram of a pass transistor selector composed of both p-channel and n-channel transistors.

FIG. 21 shows the results when the cost is changed from the area priority to the delay time priority in the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention.

FIG. 22 shows a logic circuit synthesized by the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention and a CM synthesized by an existing known method for twelve different logics.
FIG. 5 is a diagram comparing the area and power consumption of an OS logic circuit and a pass transistor logic circuit.

FIG. 23 is a flowchart of a synthesis program of a pass transistor / CMOS cooperative logic circuit according to a sixth embodiment of the present invention.

24 is a diagram showing an example of a BDD created by the pass transistor / CMOS cooperative logic circuit synthesis program of FIG. 23 according to the present invention;

FIG. 25 is a circuit diagram of an intermediate circuit created during the pass transistor selector / CMOS gate mapping routine of the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention in FIG. 23;

FIG. 26 is a circuit diagram of a pass transistor / CMOS cooperative logic circuit synthesized by the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention in FIG. 23;

FIG. 27 is a circuit diagram of a pass transistor logic circuit synthesized from the BDD of FIG. 24;

Claims (15)

[Claims] A gate controlled by a first input;
A first p-channel field effect transistor having a source-drain path connected between the first operating potential point and the first node; a gate controlled by the second input; A second p-channel field-effect transistor having a source-drain path connected between the first node and a fourth node, the gate of which is controlled by the first input;
A first n-channel field-effect transistor having a source-drain path connected between the first node and a node, a gate controlled by a second input, a fourth node and a second
A second n-channel field effect transistor having a source / drain path connected between the first operating potential point and the second operating node; and a source / drain connected between the first operating potential point and the second node. A third p-channel field effect transistor having a path connected thereto, a gate controlled by the first node, and a second node connected to the second node.
A third n-channel field-effect transistor having a source-drain path connected to an operating potential point, and a gate controlled by a second node, and a source-drain path connected between a third input and the third node. Fifth n
A sixth field-effect transistor having a gate controlled by the first node and a source-drain path connected between the fourth input and the third node;
A fourth p-channel field-effect transistor having a gate controlled by a third node and having a source-drain path connected between the first operating potential point and the first output; Controlled by a first output and a second
A logic circuit comprising a selector logic with Boolean processing, comprising a fourth n-channel field-effect transistor having a source-drain path connected to the operating potential point. 2. The semiconductor device according to claim 1, further comprising a fifth p-channel field-effect transistor having a gate controlled by an output and having a source-drain path connected between the first operating potential point and the third node. 1 logic circuit. 3. A tenth p-channel field-effect transistor having a gate controlled by a tenth input and having a source-drain path connected between a first operating potential point and a tenth node; An n-channel field effect transistor having a source-drain path connected between the tenth node and the second operating potential point; a gate controlled by the tenth node; An eleventh n-channel field-effect transistor having a source-drain path connected between the source and the eleventh node, a gate controlled by the tenth input, and a source-drain path between the twelfth input and the eleventh node A twelfth n-channel field-effect transistor connected to the gate, a gate controlled by the eleventh node, and a source connected between the first operating potential point and the twelfth node. A fifteenth p-channel field-effect transistor having a source-drain path connected thereto, a fifteenth n-channel transistor having a gate controlled by an eleventh node, and a source-drain path connected between the twelfth node and a second operating potential point A fourteenth p-channel field effect transistor having a gate controlled by a twelfth node and having a source / drain path connected between the first operating potential point and the tenth output; A fourteenth n-channel field-effect transistor controlled by a twelfth node and having a source-drain path connected between a tenth output and a thirteenth node; a gate controlled by a thirteenth input; A thirteenth p-channel field-effect transistor having a source-drain path connected between the point and the tenth output; Including a Boolean selector logic having a thirteenth n-channel field-effect transistor controlled by an input of a third node and having a source-drain path connected between a thirteenth node and a second operating potential point. circuit. 4. An eleventh p-channel field effect transistor having a gate controlled by an output and having a source / drain path connected between a first operating potential point and an eleventh node. 3 logic circuit. 5. A twentieth p-channel field effect transistor having a gate controlled by a twentieth input and having a source / drain path connected between a first operating potential point and a twentieth node; A p-channel field effect transistor having a source-drain path connected between the first operating potential point and the twentieth node; a gate controlled by the twentieth input; A twentieth n-channel field-effect transistor having a source-drain path connected between the source and the twenty-fourth node; a gate controlled by the twenty-first input; and a source connected between the twenty-fourth node and the second operating potential point. A twenty-first n-channel field-effect transistor with a drain path connected thereto, a gate controlled by a twenty-second input, a node between the first operating potential point and the twenty-second node A twenty-second p-channel field-effect transistor having a source-drain path connected to the gate thereof, a gate controlled by the twenty-second input, and a source-drain path connected between the twenty-second node and the second operating potential point. A twenty-third n-channel field-effect transistor having a gate controlled by the twenty-second node, a source-drain path connected between the twenty-third input and the twenty-third node; A twenty-fourth n-channel field-effect transistor having a source-drain path connected between the twentieth node and the twenty-third node; a gate controlled by the twenty-third node; A twenty-fifth p-channel field-effect transistor having a source-drain path connected between it and a twentieth output; And a Boolean selector logic comprising a twenty-fifth n-channel field-effect transistor controlled by the logic mode and having a source-drain path connected between the twentieth output and the second operating potential point. Logic circuit. 6. The semiconductor device according to claim 1, further comprising a twenty-third p-channel field-effect transistor having a gate controlled by an output and a source-drain path connected between the first operating potential point and the twenty-third node. 5 logic circuits. 7. A logic circuit having at least the selector logic with Boolean processing according to claim 1 or 3 or 5, including a pass transistor selector portion and a CMOS portion, wherein the area ratio of the pass transistor selector is 10 to 60%. A logic circuit, comprising: 8. The logic circuit according to claim 1, comprising at least a cell 1 and a cell 2 on a semiconductor substrate, wherein the cells 1 and 2 have a substantially rectangular shape. Cell 2 includes a fourth p-channel field-effect transistor, fourth, fifth and sixth n-channel field-effect transistors, and a second n-channel field-effect transistor. Cell 1 and Cell 2 have two power lines running in the horizontal direction, the vertical heights of Cell 1 and Cell 2 are substantially equal, and the vertical power lines of Cell 1 and Cell 2 A logic circuit, wherein heights in directions are substantially equal. 9. A logic circuit defining a relationship between a group of input variables representing a group of input signals of a logic circuit to be synthesized and an output variable representing at least one output signal of the logic circuit, based on the logic function. A method for synthesizing a logic circuit by a computer system, comprising the following steps executed by the computer system. (A) creating a BDD from a logical function, and (b) creating a pass transistor logic circuit by replacing all nodes of the BDD with a pass transistor selector circuit having two inputs, one output and one control input. (C) A pass transistor selector in which one of the two inputs is fixed to a logical constant 1 or 0 is replaced with a logically equivalent CMOS gate such as NAND or NOR, and the area, delay time, If the value of the circuit characteristic such as power consumption is calculated and replaced with a CMOS gate, if the value of the predetermined circuit characteristic is closer to optimal, the pass transistor selector is replaced with a CMOS gate, and (d) the step (c) Is applied to all the pass transistor selectors, the predetermined circuit characteristics are optimized, and the pass transistor circuit obtained in the above steps (e) and the CMOS circuit are combined. The logic circuit Deki by outputting a logic circuit for the logic function. 10. The method of synthesizing a logic circuit according to claim 9, wherein the logic circuit having the optimum value of the predetermined circuit characteristic is a logic circuit having a minimum area. 11. The method according to claim 9, wherein the logic circuit having the optimum value of the predetermined circuit characteristic is a logic circuit having a minimum delay time. 12. The method according to claim 9, wherein the logic circuit having the optimum value of the predetermined circuit characteristic is a logic circuit having the minimum power consumption. 13. The method of synthesizing a logic circuit according to claim 9, wherein the logic circuit having an optimum value of the predetermined circuit characteristic is a logic circuit having an optimum combination of area, delay time, and power consumption. 14. A logic circuit defining a relationship between a group of input variables representing a group of input signals of a logic circuit to be synthesized and an output variable representing at least one output signal of the logic circuit. A method for synthesizing a logic circuit by a computer system, comprising the following steps executed by the computer system. (A) A binary decision diagram is created from a logical function, and (b) two branches (0 branch, 1 branch) among nodes of the binary decision graph
Branch) is a node whose logical constant is fixed to 1 or 0, the NA that is logically equivalent to that node
Replace with CMOS gates such as ND, NOR, etc., and replace the other nodes with pass transistor selector circuits with two inputs, one output and one control input, and combine the pass transistor circuit obtained by the above steps and the CMOS circuit. The resulting logic circuit is output as a logic circuit for the above logic function. 15. A plurality of mask patterns for generating a logic circuit based on a logic circuit in which a pass transistor circuit and a CMOS circuit according to claim 1 are combined, and the plurality of mask patterns are used. A method of manufacturing a semiconductor device including a step of manufacturing a semiconductor integrated circuit including the above logic circuit.