TW436990B - Process for forming a semiconductor device - Google Patents

Process for forming a semiconductor device Download PDF

Info

Publication number
TW436990B
TW436990B TW088118965A TW88118965A TW436990B TW 436990 B TW436990 B TW 436990B TW 088118965 A TW088118965 A TW 088118965A TW 88118965 A TW88118965 A TW 88118965A TW 436990 B TW436990 B TW 436990B
Authority
TW
Taiwan
Prior art keywords
seed film
film
substrate
forming
semiconductor device
Prior art date
Application number
TW088118965A
Other languages
English (en)
Chinese (zh)
Inventor
Robert D Mikkola
Rina Chowdury
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of TW436990B publication Critical patent/TW436990B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
TW088118965A 1998-11-24 1999-11-01 Process for forming a semiconductor device TW436990B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US19892298A 1998-11-24 1998-11-24

Publications (1)

Publication Number Publication Date
TW436990B true TW436990B (en) 2001-05-28

Family

ID=22735460

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088118965A TW436990B (en) 1998-11-24 1999-11-01 Process for forming a semiconductor device

Country Status (6)

Country Link
EP (1) EP1005078B1 (enExample)
JP (1) JP4444420B2 (enExample)
KR (1) KR100647996B1 (enExample)
CN (1) CN1255746A (enExample)
DE (1) DE69914294T2 (enExample)
TW (1) TW436990B (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6423200B1 (en) * 1999-09-30 2002-07-23 Lam Research Corporation Copper interconnect seed layer treatment methods and apparatuses for treating the same
EP1111096A3 (en) 1999-12-15 2004-02-11 Shipley Company LLC Seed layer repair method
KR100400765B1 (ko) * 2000-11-13 2003-10-08 엘지.필립스 엘시디 주식회사 박막 형성방법 및 이를 적용한 액정표시소자의 제조방법
US6849173B1 (en) * 2002-06-12 2005-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Technique to enhance the yield of copper interconnections
KR20040001470A (ko) * 2002-06-28 2004-01-07 주식회사 하이닉스반도체 반도체 소자의 배선 형성을 위한 구리 씨앗층 형성 방법
KR100808601B1 (ko) * 2006-12-28 2008-02-29 주식회사 하이닉스반도체 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법
CN104299958B (zh) * 2013-07-16 2018-11-16 中芯国际集成电路制造(上海)有限公司 互连结构及互连结构的形成方法
CN111031683B (zh) * 2019-12-23 2021-10-08 沪士电子股份有限公司 一种pcb生产工艺中图形电镀陪镀板的设计和使用方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0783168B2 (ja) * 1988-04-13 1995-09-06 株式会社日立製作所 プリント板の製造方法
US5391517A (en) * 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
KR20000057470A (ko) * 1996-12-16 2000-09-15 포만 제프리 엘 집적 회로 칩 상의 전기 도금된 상호 접속 구조체

Also Published As

Publication number Publication date
EP1005078B1 (en) 2004-01-21
KR20000035623A (ko) 2000-06-26
JP2000164718A (ja) 2000-06-16
JP4444420B2 (ja) 2010-03-31
KR100647996B1 (ko) 2006-11-23
DE69914294T2 (de) 2004-11-18
CN1255746A (zh) 2000-06-07
DE69914294D1 (de) 2004-02-26
EP1005078A1 (en) 2000-05-31

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GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees