TW429554B - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same

Info

Publication number
TW429554B
TW429554B TW086119197A TW86119197A TW429554B TW 429554 B TW429554 B TW 429554B TW 086119197 A TW086119197 A TW 086119197A TW 86119197 A TW86119197 A TW 86119197A TW 429554 B TW429554 B TW 429554B
Authority
TW
Taiwan
Prior art keywords
semiconductor device
layer
semiconductor substrate
conductor patterns
etching stop
Prior art date
Application number
TW086119197A
Other languages
English (en)
Inventor
Taiji Ema
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of TW429554B publication Critical patent/TW429554B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/033Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335Making a connection between the transistor and the capacitor, e.g. plug
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48Data lines or contacts therefor
    • H10B12/485Bit line contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/312DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with a bit line higher than the capacitor
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90MOSFET type gate sidewall insulating spacer

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
TW086119197A 1997-10-20 1997-12-18 Semiconductor device and method for fabricating the same TW429554B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9287466A JPH11121716A (ja) 1997-10-20 1997-10-20 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
TW429554B true TW429554B (en) 2001-04-11

Family

ID=17717713

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086119197A TW429554B (en) 1997-10-20 1997-12-18 Semiconductor device and method for fabricating the same

Country Status (4)

Country Link
US (2) US7253525B2 (zh)
JP (1) JPH11121716A (zh)
KR (1) KR100259751B1 (zh)
TW (1) TW429554B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI391790B (zh) * 2004-10-27 2013-04-01 Renesas Electronics Corp 圖案形成方法,半導體裝置之製造方法及曝光用遮罩組

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4142228B2 (ja) * 2000-02-01 2008-09-03 株式会社ルネサステクノロジ 半導体集積回路装置
KR100724568B1 (ko) * 2005-10-12 2007-06-04 삼성전자주식회사 반도체 메모리 소자 및 그 제조방법
KR101102766B1 (ko) * 2009-09-18 2012-01-03 주식회사 하이닉스반도체 반도체 소자의 제조 방법
JP5731858B2 (ja) * 2011-03-09 2015-06-10 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. 半導体装置及び半導体装置の製造方法
KR20160013765A (ko) * 2014-07-28 2016-02-05 삼성전자주식회사 반도체 장치

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5498889A (en) * 1993-11-29 1996-03-12 Motorola, Inc. Semiconductor device having increased capacitance and method for making the same
JPH0837181A (ja) 1994-07-21 1996-02-06 Mitsubishi Electric Corp 半導体装置及びその製造方法
KR100215759B1 (ko) * 1994-12-19 1999-08-16 모리시타 요이치 반도체 장치 및 그 제조방법
JP2663900B2 (ja) * 1995-02-28 1997-10-15 日本電気株式会社 半導体装置の製造方法
JP3532325B2 (ja) * 1995-07-21 2004-05-31 株式会社東芝 半導体記憶装置
JPH0964179A (ja) * 1995-08-25 1997-03-07 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3795634B2 (ja) * 1996-06-19 2006-07-12 株式会社東芝 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI391790B (zh) * 2004-10-27 2013-04-01 Renesas Electronics Corp 圖案形成方法,半導體裝置之製造方法及曝光用遮罩組

Also Published As

Publication number Publication date
US20070037344A1 (en) 2007-02-15
JPH11121716A (ja) 1999-04-30
US7253525B2 (en) 2007-08-07
KR19990035746A (ko) 1999-05-25
US20010035544A1 (en) 2001-11-01
KR100259751B1 (ko) 2000-06-15

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees