TW416122B - An etch stop layer for dual damascene process - Google Patents

An etch stop layer for dual damascene process Download PDF

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Publication number
TW416122B
TW416122B TW087117913A TW87117913A TW416122B TW 416122 B TW416122 B TW 416122B TW 087117913 A TW087117913 A TW 087117913A TW 87117913 A TW87117913 A TW 87117913A TW 416122 B TW416122 B TW 416122B
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Taiwan
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stop layer
etch stop
layer
patent application
low
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TW087117913A
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English (en)
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Sasson Somekh
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Applied Materials Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Description

6122 λ-
__—__JH 五、發明説明（） ............ 發明領域： 本發明一般係有關於基材上之積體電路之製造’且更 特別的是，本發明係有關於一新的蝕刻停止層和在内連線 之間形成低電容值之雙重鑲嵌結構之製程。 發明背景：_ 在最近十年中積體電路之設計和製造持續且可預期 的有相當的進步。其中一個改良成功之關鍵為多層内連線 技術，此技術提供了積體電路（IC)元件之裝置間的導電路 徑。大型積體電路（VLSI)和超大型積體電路（ULSI)之技術 中水平内連線（通常稱之為線（line))和垂直内連線（通常 丁 、-° 稱之為接觸窗或介層窗；接觸窗延伸到基材之底層上之 疋件’而介層窗則延伸到底層之金屬層如Ml, M2，等） <尺寸降低對於特別是内連線間電容之耦合的減小顯得 愈來愈重要。為了更要改善半導體元件在積體電路上之速 度，則需要利用具有低阻抗之導電材料和低k值（介電常 數<4.0)之絕緣體以降低鄰近金屬線之間的電容耦合。例 如，現在已考慮以铜來替代鋁，因為銅具有較低之阻抗及 較南的電流攜帶能力.而且，比二氧化矽（介電常數〜4 具有較低介電常數之介電材料也已慎重的考慮用於元件 疋生產《這些介電材料中其中一個例子為摻雜有氟之二氧 化矽，也稱之為摻雜氟之矽玻璃（FSG)(介電常數〜3 5_ 3.7)。 然而，這些材料卻在1C製造程序中產生了新的問題。 -------- 第4·頁 本纸 --------- --------^ 416122 Λ· 1Γ 五、發明説明（ 例如’由於銅很難蝕刻成精密的 從μ圖案’傳統的沉積/蝕刻製 程以形成内連線變成不可行，# &外’有一種稱作雙重鑲嵌 (dual damascene)之製程乃用爽釈二‘ 「1"請背而之注^"_項ftiri:15本π〕 〜取成鋼之内連線。在一雙重 鑲嵌之製程中，介電層乃蝕刻以令a 疋羽•出接觸窗/介層窗兩者 及内連線。金屬接著乃嵌入所定 <義< 圖案，且任何頂端超 出結構外的金屬乃利用如化學始& 瑪械研磨（CMP)之方法來加 以平坦化而移除。 第1a圖到第lc圖例舉了利用形成於基材U之上的 單一(厚的)電介層1〇用於雙重鑲嵌結構之製造方法。如第 1 a圖中所示的，介電層i 〇乃利 7布』用一限時蝕刻製程來加以 圖案化以定義出内連線2 0。垂吉ώ& 内連線16(也就是接觸窗 /介層窗）乃接著在内連線之皮却士 1 '-7. 氓邵中加以圖案化（第lb圖）並
触刻以曝露出底層之導電成生道μ E 或+導體層如基材丨2(第le 圖）。具有接觸窗/介層窗16和肉，电垃, 押内連線2〇之蝕刻結構乃填 入導體材料且上半表面加以平拍彳 τ坦化。然而，限時蝕刻步驟 之深度很難加以控制，且在内速祛ώ 1丨.* Λ:、 ' 杜門硬線溝渠中又接觸窗/介層窗 之圖案化也是很難執行的製程。 -•r/-;rf、4^^^-χ;ίί费合作扎印鉍 第2a和2b8例舉了另—個用來製造雙重鎮嵌結構之 方法。如第2a囷中所示的，—單一(厚的)介電& 1〇乃形 成於基材12之上，且接觸窗/介層窗16利用限時蝕刻製程 加以圖案化且部分的蝕刻到介電層1〇之中。内連線接 者加以圖案化且使用第二限時蝕刻來形成内連線之溝 渠，如帛2b目中所示。在此第二限時蝕刻步驟中，接觸 窗/介層窗1 6乃蝕刻到額外的深度，足夠讓接觸窗/介層窗 416122 Λ .-. ------— Β7 五、發明説明（） --------------------------- 垂直的延伸到其所想要的深度，如圖中的虛線所示。然 而此限時姓刻步鄉還是很難加以控制，因而此製程對商 業化製造來說較無吸引力。 「贫》閱"背而之：^-怨氺項再^-:;,)本頁) 第三個及更多其它較佳的方法利用兩步驟之介電層 >儿積及一蝕刻停止層沉積於其中之雙重鑲嵌結構製造方 法則如第3圖中所示。第—介電層丨〇沉積於基材之上且 接著一蝕刻停止層14乃沉積於第一介電層之上。蝕刻停 止層接著加以圖案化以定義出接觸窗/介層窗丨6的開口。 一第二介電層18然後再沉積於圖案化之蝕刻停止層之 上’且接著圖案化以定義出内連線2(^因此只執行一次姑 刻製程來定義出蝕刻停止層以下之内連線，且由蝕刻停止 訂 層圖案所曝露的未被保護之介電材料以定義出接觸窗/介 層窗。 氮化矽為所選擇之蝕刻停止層材料。然而，配置於介 電層之間的氮化矽係在内連線之間的邊緣場之中。氮化碎 和周圍之介電層比較起來具有相當高的介電常數（介電常 數〜7) ’且可以發現到氮化矽可以非常有效的增加内連線 之間耦合的電容，即便一相當低k值之介電材料乃做為主 要的絕緣體。如此則產生了串擾訊號及/或電阻-電容（RC) 延遲，並和元件之整體效能有關。 因此，極需要一個形成雙重鑲嵌之製程並在内連線之 間有降低的電容辑合。 ___ n' 五'發明説明（） 發明目的及概诚： 本發明提供了一製造程序和蝕刻終止村料，其可讓雙 重鑲嵌結構更為可靠，並減小蝕刻停止層對内連線之間的 電容搞合的影響。在一實施例中，一低k值之介電薄膜； 例如一非晶碳（a - C)或非晶碳氟化物（a - F C)薄膜用來做 為内金屬介電質（IMD)之下的蝕刻停止層。其它的低k值 材料例如聚對-二甲苯基，AF4，BCB，PAE，氮氧化物和 碳化j夕也可加以利用。 本發明較佳的製造程序至少包含沉積例如氟化碎破 璃（FSG)層之第.一介電層於一基材上，沉積例如a_FC層之 低k值介電停止層於第一介電層之上’將蝕刻停止層圖案 化以定義出接觸窗/介層窗，沉積例如FSG之第二介電層， 在第二介電層之上圖案化一阻抗層以定義出一或多個内 連線’且蝕刻内連線和接觸窗/介層窗。在最後的蝕刻步赞 中内連線乃蝕刻到蝕刻停止層，且接著繼續加以蝕刻並缒 過圖案化後的蝕刻停止層以定義出接觸窗，介層窗。一旦雙 重鑲嵌結構形成之後，最好在將此結搆填入鋼之前先岣勹 的沉積一層阻障層，以便隔離銅和其它的材料，例如矽。 而上表面則利用化學機械研磨技術加以平坦化。 周式簡單說明： 由上面之陳述將可達到本發明的特徵，優點和目的， 而且經由參:考實施例及後面之附圖之後，更可詳細的瞭解 本發明。 —__________第7頁 本紙張乂度嘀 π 中 β K 孓 d- ( t'NS ) ,\.π.--------- -----_ Λ 416122 五、發明説明（） 先 閱 讀 背 面 .冬 i 事 項 再 填 本 Τί 然而，後面之附圖只是本發明之典型實施例而已，並 不因此而限制了本發明之範圍，其它具同等效力之實施例 亦在本發明之範圍内。 第1 a-1 c圖之截面視圖顯示了依照傳統技術之雙重鑲嵌製 程； 第2a和2b圖之截面視圖也顯示了依照傳統技術之雙重鑲 嵌製程； 第3圖之截面視圖顯示了形成於一基材之上的雙重鑲嵌結 構； 第4a-4h圖之截面視圖顯示了依照本發明之一實施例的沉 積程序；及 訂 第5圖為第4圖之雙重鑲嵌結構之沉積製造程序。 圖號對照說明： 10 第 一 介 電 層 12 基 材 14 停 止 層 16 開 π 18 第 二 介 電 層 20 内 連 線 22 光 阻 層 24 阻 障 層 26 内 連 線 發明詳細說明： 本發明提供了改善的雙重鑲嵌結構*至少包含了一低 k值之蝕刻停止層，且最好是一非晶，類似鑽石結構之碳（α -C)材料。低k值之姑刻停止層在此所定義的為具有等於 第8頁 本纸張尺度適用中阔闹掌d- U'NS > : 2111 416122 ___________Η' 五、發明説明（） 或低於|l化碎之介電常數（介電常數~7 〇)的蝕刻停止層。 依照本發明所製造之雙重鑲嵌結構顯示於第4h圖’而此 結構之製造方法則依序在第4a-4h圖中描繪出來，此些圖 中的基材截面視圖中係以本發明之步驟所形成β 如第4a圖中所顯示的’最初之第一介電層1 〇，例如 FSG ’氧化矽層’或類似的材料，乃於基材12之上沉積約 5000到約10000a之厚度，並和所要製造之結構的尺寸有 關*如第4b圖中所示的’低k值之蝕刻停止層14，例如 a -C，a -FC ’聚對-二曱苯基，af4，BCB，PAE，氮氧化 物或碳化矽等材料，接著在第一介電層上沉積約2〇〇到約 1 000A之厚度β低k值蝕刻停止層14接著加以圈案化並 姓刻而定義出接觸窗/介層窗開口 16,且曝露出接觸窗/介 層窗所要形成之第一介電層1〇的面積，如第4c圈中所 示。低k值之蝕刻停止層1 4最好利用傳統的微影和蝕刻 製程以氟，碳，和氧離子加以圈案化並蝕刻。在低k值之 姓刻停止層14已加以蝕刻而形成接觸窗/介層窗的圖案且 光阻也移除之後，第二介電層1 8則沉積於蝕刻停止層！ 4 之上約5000到約i〇〇〇〇a之厚度，如第4d圏中所示。第 二介電層18接著加以圖案化以定義出内連線20，且最好 是利用傳統之微影製程及光阻層22，如第4e圖中所示。 内連線和接觸窗/介層窗接著利用離子反應蝕刻或其它的 非等向性蝕刻技術加以蝕刻以定義出金屬層結構（也就是 内連線和接觸窗/介層窗），.如第4f圖中所示。任何光阻或 其它用來圓案化並蝕刻停止層14或第二介電層18的材料 _____ 第9貰 木㈣丨，關: ~--- ^^1 ^^^1 I— - *1— t , if ^^^1 n^i V.· .- V 、T (背而之注念萝項^4、'1·:'本N ) 4^6122 Λ"
_______ JP 五、發明説明（）~~~~ … ――— 則利用氧氣剝離或其它適當的方法加以移除。 金屬層結構再以例如鋁’銅’鎢或其組合之導電材料 形成》現在的趨勢是利用銅原子來填入較小的介層窗因 為銅有較低的電阻率（和鋁的31以比較只有ι 7以 Q -cm)。如第4g圓中所示的，最好由鈦，氮化鈦，或其 它適合的阻障材料形成一層均勻的阻障層24沉積於金屬 層圖案疋上，以避免銅原子擴散到周圍的矽基材及/或介電 材料中。之後再利用化學氣相沉積，物理氣相沉積，電子 .被復’或其組合的方法將銅原子沉積以形成導電結構。一 旦結構中填入了銅或其它的金屬之後’其表面再以化學機 械研磨加以平坦化，如第4h圖中所示的。 .丁 *-=3 本發明之另一實施例則考慮利用FSG作為内金屬介 電層’ α-FC(介電常數〜2.8)作為蝕刻停止層且銅為金屬層 而完成此雙重鎮嵌結搆。此製程將在下面加以詳述β而此 實施例之製程步驟則顯示於第5圖中。 經部中央標孳局只-τ消f合作杜印製 將一基材放入來自 Applied materials，Inc.，Santa Clara, California的DxZ®反應室之中。第一覆蓋fsG層之 厚度大約5000A且利用TEOS ’ 02，和C2F6或其它氣鱧流 過基材之表面而在基材之上沉積。 一氧化阻陣層乃沉積在FSG層之上以避免在FSG層 和接下來的a -FC層之間有不同材料之擴散。 接著’將基材移到ultima HDp-CVD反應室中，此反 應室也來自 Applied materials, Inc., of Santa Clara, California，其中5〇〇A厚之a -FC蝕刻停止層乃形成於第 第10頁 ΊΊΑ] w -ΐ- ( CNS Γλ4*1' ί ：10 < ?，r · ' ；·; 416122 a: --—_____ ΙΓ 五、發明説明（ ） —FSG層之上。α -FC蝕刻停止層之沉積由八氟環丁烷 (C4F8)和甲烷（Ch4)以約20sccm和约200SCcm之速率流入 反應室而得，而最好是約50sccm。氬氣，或其它的隋性氣 體則以約20sccm到約100scem之速率流入反應室。1〇〇〇ψ 疋來源功率和丨〇〇〇w之偏壓功率分別加到來源線圈和基 材支撐元件以便在處理反應室中揸擊和維持高濃度之電 衆。在沉積時反應室之壓力最好是低於1〇mT〇rr。這是上 面所描述之較好之製程’其它的製程和例如d，c2H4， C2H6 ’ CF4，C2F6 ’ C3F8 ’ CHF3，和 C6f6 之前導氣體也可 加以利用β 接著’一光阻層在α-FC蝕刻停止層之上形成，並以 傳統的微影方法曝露而定義出接觸窗/介層窗之開口。接著 將基材移入介電層蚀刻反應器如IPS反應室中’此反應室 也來自 Applied materials，Inc‘，of Santa Clara, 經#‘部中央櫟來"JH工消伦合作社印狀
California a a _FC蝕刻停止層最好非等向性的以三氟曱坑 ’氧，和氬氣等高密度電漿加以蝕刻而經由α _fc 蚀刻停止層定義出接觸窗/介層窗開口。α _FC蝕刻停止層 之蚀刻最好在實際上蝕刻底層的FSG層時就停止以避免 過度姓刻》在a-FC層和FSG層之間的終點偵測最方便的 方式是由蝕刻副產品氣體之光學偵測。剎下的光阻層接著 利用02電漿加以剥離。 基材接著移回到DxZ®反應室中並在圖案化之a -FC 蚀刻停止層之上形成5000Α之第二FSG層。第二光阻層 接著沉積在第二FSG層之上並由傳統之微影方法定義出 __ 第11頁 各紙张尺度適川中闽闹家疗卑（（'NS ) ( 210-77"；：. ί；'' ..... - 41Q122 ***^*•*1 **! ______ Ι_·_ _ 五、發明説明（） - 光阻間的内連線開口。接著將基材移回lps反應室’將基 材曝露在多碳，無氧氣，氟-碳蝕刻環境之下以單一步想 蝕刻整個雙重鑲嵌結構。FSG層最好是以qF8或c3f6和 氬氣之電漿非等向性蝕刻，因此内連線和接觸窗/介層^乃 形成相t直的侧壁且；支有底&。加入少f的氫氣以保護側 壁。一旦内連線蝕刻到圖案化之α 層’則蝕刻乃實質
的限制到已明案化之接觸窗/介層冑。在姓刻完兩層MG 層之後的終點偵測最方便的是由光學偵測蝕刻副產品氣 體。在内連線之蝕刻完成之後，剩下的光阻層利用氧氣電 漿加以剝離。 鈦，氮化鈦，及其組合之阻障層，或其它合通之阻障 層最好案化之雙重錄嵌結搆之上形成，且接著在此結 構之上填入铜。其中一個將此結構中填入銅的方法提供了 利用CVD技術將接觸窗/介層窗填入銅，且接著利用pvD 技術將此結構剩下的體積填入銅9然而，任何適當的充填 方法例如CVD，PVD(包括高密度電漿PVD)，電子被覆或 其组合都可以使用。然後在沉積其它鍍層之前用化學機械 研磨法或其它的平坦化製程將其平坦化， 粒-,·部中央惮^'^H工消贽合竹权印鉍 如第4h圖中所示的，一铜的雙重鑲嵌結構具有位於 内連線26之間的低k值蝕刻停止層〗4乃加以形成。蝕刻 停止層14之低k值特性可預防内連線之間的串擾訊號和 增加RC延遲’而影響到元件的速度。 另外的at -C和a -FC蝕刻停止層包括其它的碳基基 材料。特別的是’有許多碳基基材料適合做氧化内金屬介 一 —__________ 第 12 頁 本紙乐度適用中闲内m ( cns )，vm'·ί^ΓΓΙΤο^：™ x j： 一'一"'—~ 416122 五、發明说明（） 電層之蝕刻停止層。這樣的材料其介電常數也低於氮化矽 (氮化矽）將可降低内連線之間的電容耦合。此類不同的碳 基底薄膜包括聚對-二甲苯基和相關的材料，例如聚對-二 甲苯基·Ν和AF4, BCB sp丨n-on，PAE，氮氧化物和碳化攻。 由於前述内容乃導向本發明之較佳實施例，本發明之 其它和更進一步的實施例也可在不偏離本發明之範圍下 得之’而其範圍則由下面之申請專利範圍所決定。 - ,—i I — 1 I Ί ί— 1.1 ^ ("WWM 背而之"^事項4"!'(,';"·^頁) 經沪却中央桴涑杓妇工消资合作杜印批 __ 第13頁 木<也疋度適β中阈网糸( ) ：丨()，：(_r r

Claims (1)

  1. δ σο δ 8 ABCD 416122 々、申請專利範圍 1.一種形成雙重鑲嵌結構之方法，該方法至少包含： 沉積一第一介電層於一基材上； 沉積一低k值蝕刻停止層於該第一介電薄膜之上； 姓刻製程該低k值蝕刻停止層以定義出垂直内連線 開口並曝露出第一介電薄膜； 沉積一第二介電薄膜於低k值蝕刻停止層和曝露之 第一介電薄膜之上；及 触刻製程該第二介電薄膜以定義出水平的内連線， 且堪續的蝕刻曝露的第一介電薄膜以定義出垂直的内 連線》 2.如申請專利範圍第1项所述之方法，其中上述之低让值 姓刻停止層係從包含α _FC，a -C，聚對-二f苯基， AI%，BCB，PAE，氮氧化物，碳化矽和其组合所組成之 群集所選擇出來。 3_如申請專利範圍第1項所述之方法，其中上述之介電屠 至少包含摻雜氟原子之矽玻璃且低k值蝕刻停止層至少 包含a -FC。 4. 如申請專利範圍第3項所述之方法，其中更包含了在沉 積低k值蚀刻停止層之前和之後沉積_氧化物阻障層。 5. 如申請專利範圍第1項所述之方法’其中上述之蝕刻水 第uT 本纸張尺度逋用中國國家標準（CNS ) ..Μ規格（210X297公渖 (請先聞讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局貝工消費合作社印製 A8 B8 C8 D8 法至少包含下列步 六、申請專利範園 平和垂直内連線係為單一步驟蝕刻程序。 6_如申請專利範圍帛1項所述之方法，其中上述之低k值 蚀刻停止層為α -FC。 7.如申請專利範圍帛6項所述之方法，其中上述之α吓c 蝕刻停止層之沉積係由選自至少包含CH4，C2h4， C2H6 ’ C6H6 ’ CF4 ’ c2f6 ’ c3f8 ’ c4f8，chf3 和其紕合 之氣體群集中. 8·如申請專利範圍丨6項所述之方法，其中上述之a-FC 姓刻停止層之沉積係來自至少包含和CH4氣體β 一種形成雙重鑲嵌結構之方法，該方 辑： iic積第一介電薄膜於一基材上； 沆積一低k值蝕刻停止層於第一介電薄膜之上： 圖案化第一光阻層以定義出一或多個垂直的内連 開ο ; 蝕刻製程該低k值介電停止層以定義出一或多個垂 直内連線開口並曝露出該第一介電薄膜； 剝離該第一光阻層，並以氧氣電漿為之； 沉積第二介電薄膜於該低k僅介電蝕刻停止層和該 曝露之第—介電薄膜之上； -------^十，---------1T-----If' - (請先Μ讀背面之注意事項再填寫太頁) 蛵濟部中夬祿隼局員工消費合作，社印製 良紙張 第15頁 (CNS ) Λ桃烙（2I0X297公聲：丨 經濟部中央標準局員工消費合作社印裝 416122 b C_.〇 D8六、申請專利範圍 沉積第二光阻層於該第二介電薄膜之上； 圖案化該第二光阻層以定義出一或多個水平的内連 線： 蝕刻製程該第二介電薄膜以定義出一或多個水平之 内連線，且繼續的蝕刻該第一介電薄膜以定義出一或多 個垂直内連線。 10. 如申請專利範圍第9項所述之方法，其中上述之低k 值蚀刻停止看係選自至少包含a-FC，α-C，聚對-二甲 苯基，AF4，BCB，PAE，氮氧化物，碳化碎和其組合之 群集中。 11. 如申請專利範圍第9項所述之方法，其中上述之介電層 至少包含摻雜氟離子之矽玻璃且該低k值蝕刻停止層至 少包含a -FC β 12. 如申請專利範圍第11項所述之方法，其中更包含了在 沉積該低k值姓刻停止層之前和之後沉積一氧化物阻障 層。 13. 如申請專利範圍第9項所述之方法，其中上述之蚀刻水 平和垂直内連線為單一步驟蝕刻程序。 1 4 .如申請專利範圍第9項所述之方法，其中上述之低k 第16耳___ 本紙張尺度適用中囤國家標準（CNS ) Λ4规格ί 2丨οκ^7公f ' (請先閱讀背面之注意事項再填寫本頁) 訂 線 416122 AS B3 C8 D8 六、申請專利範圍 值蝕刻停止層為α · F C。 15. 如申請專利範圍第14項所述之方法，其中上述之 姓刻停止層之沉積係選自至少包含CH4, c2h4 , c2h6， C2H2 ’ C6H6 ’ CF4 ’ C2F6 ’ C3F8 ’ c4f8，chf3 和其組合 之氣體群集中。 16. 如申請專利範圍第14項所述之方法，其中上述之a_Fc 蝕刻停止層之沉積係來自至少包含C4Fg和CH4氣體。 17. —種雙重鑲嵌結構，該結構至少包含： a) -第一低k值介電層定義出一或多個垂直内連 線； b) 一低k值圖案化之蝕刻停止層覆蓋於該第一低k 值介電層之上，且蝕刻製程以定義出一或多個垂直内連 線； c) 一第二低k值介電層覆蓋於該圖案化之低k值蝕 刻停止層之上且定義出一或多個水平内連線：及 句其中該低k值圓案化之蝕刻停止層至少包含介電 常數至少等於或低於該第一或第二介電層之材料。 1 8·如中請專利範園第17項所述之結構’其中上述之低k 值蚀刻停止層至少包含非晶碳。 第17頁 本紙張尺度it财賴；!：縣(CNS > Λ4規格（2Η)χ 297公舞丨 (請先W讀背面之注意事項再填寫^頁) 訂 經濟部中央標準局員工消費合作社印製 經濟部中夹標準局員工消費合作社印裝 Α8 Β8 C8 D8 申請專利範圍 19，如申請專利範圍第18項所述之結構，其中上述之第一 和第二介電層所組成之材料係選自摻雜氟之氧化矽，氧 化發或其組合。 20.如申請專利範圍第η項所述之結構，其中上述之低让 值姓刻停止層至少包含的材料係選自a-FC，α-C，聚 對·二甲苯基，AF4，BCB，PAE，氮氧化物，碳化矽和 其组合。 2ί·如申請專利範園第19項所述之結構，其中上述之一或 多個垂直内連綠和該一或多個水平内連線所组成之材 料係選自鋁，銅，鎢和其组合· 22_如申請專利範圍第21項所述之結構，其中更包含了配 置於該低k值介電層和金屬層之間的阻障層。 23 _如申請專利範圍第22項所述之結構，其中上述之阻障 層係由鈦，氮化鈦’氮化矽或其组合所组成。 24. —種蝕刻停止層，至少包含—碳基底之材料且具有小於 7之介電常數。 2 5.如申請專利範圍第24項之蝕刻停止層，其中上述之碳 基基材料係選自至少包含α-FC，£2-C，聚對_二〒苯 第18頁 本紙張尺度適財賴家料（CNS )八说格（21ϋΧ29?公誇ΐ' (请先閲讀背面之注意事項再填寫本瓦) 、va Λ8 B8 416122_^ 六、申請專利範圍 基，AF4’ BCB’ PAE’氮氧化物，碳化矽和其組合之群 集中。 26. —種碳基底之薄膜，具有低於氮化矽之介電常數，用於 矽基底内金屬介電層之下的蝕刻停止層。 27. —種碳基底之薄膜，具有低於氮化矽之介電常數，用於 雙重鑲嵌結構中之矽基底内金屬介電層之下的蝕刻停 止層。 (請先閱讀背面之注意事項再填寫本頁) -1T 禮濟部中央樣準局員工消費合作社印製 第 本紙乐足度適用中國國家標嗥（CNS ) A4現格（210X297公釐
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