TW410372B - Semiconductor device and manufaturing method thereof - Google Patents

Semiconductor device and manufaturing method thereof Download PDF

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Publication number
TW410372B
TW410372B TW088106181A TW88106181A TW410372B TW 410372 B TW410372 B TW 410372B TW 088106181 A TW088106181 A TW 088106181A TW 88106181 A TW88106181 A TW 88106181A TW 410372 B TW410372 B TW 410372B
Authority
TW
Taiwan
Prior art keywords
film
semiconductor device
gate electrode
teos
insulating film
Prior art date
Application number
TW088106181A
Other languages
English (en)
Chinese (zh)
Inventor
Shinya Ito
Original Assignee
Nippon Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co filed Critical Nippon Electric Co
Application granted granted Critical
Publication of TW410372B publication Critical patent/TW410372B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
TW088106181A 1998-04-20 1999-04-17 Semiconductor device and manufaturing method thereof TW410372B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10109734A JP3107157B2 (ja) 1998-04-20 1998-04-20 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
TW410372B true TW410372B (en) 2000-11-01

Family

ID=14517899

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088106181A TW410372B (en) 1998-04-20 1999-04-17 Semiconductor device and manufaturing method thereof

Country Status (5)

Country Link
JP (1) JP3107157B2 (ja)
KR (1) KR19990083320A (ja)
CN (1) CN1233857A (ja)
GB (1) GB2336719A (ja)
TW (1) TW410372B (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4215787B2 (ja) 2005-09-15 2009-01-28 エルピーダメモリ株式会社 半導体集積回路装置およびその製造方法
CN102201341B (zh) * 2010-03-22 2015-09-09 中芯国际集成电路制造(上海)有限公司 制造nmos晶体管的方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW203148B (ja) * 1991-03-27 1993-04-01 American Telephone & Telegraph
US5976939A (en) * 1995-07-03 1999-11-02 Intel Corporation Low damage doping technique for self-aligned source and drain regions
JP2001504639A (ja) * 1995-10-04 2001-04-03 インテル・コーポレーション ドーピング処理ガラスによるソース／ドレーンの形成
KR970030891A (ko) * 1995-11-21 1997-06-26 윌리엄 이. 힐러 Mos 기술에서의 급속 열 어닐링 처리

Also Published As

Publication number Publication date
CN1233857A (zh) 1999-11-03
GB2336719A (en) 1999-10-27
KR19990083320A (ko) 1999-11-25
GB9909042D0 (en) 1999-06-16
JPH11307759A (ja) 1999-11-05
JP3107157B2 (ja) 2000-11-06

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MM4A Annulment or lapse of patent due to non-payment of fees