GB2336719A - Sidewall insulating films for field effect transistors - Google Patents
Sidewall insulating films for field effect transistors Download PDFInfo
- Publication number
- GB2336719A GB2336719A GB9909042A GB9909042A GB2336719A GB 2336719 A GB2336719 A GB 2336719A GB 9909042 A GB9909042 A GB 9909042A GB 9909042 A GB9909042 A GB 9909042A GB 2336719 A GB2336719 A GB 2336719A
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- GB
- United Kingdom
- Prior art keywords
- film
- insulating film
- gate electrode
- semiconductor device
- sidewall insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 230000005669 field effect Effects 0.000 title description 2
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000002019 doping agent Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 230000000052 comparative effect Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000006731 degradation reaction Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The transistor comprises a gate insulating film 2, a gate electrode 3, a source-drain region 7 and a sidewall insulating film formed at a sidewall of the gate electrode, wherein the sidewall insulating film has a double layered structure made up of a TEOS NSG film 5 which is in contact with both the sidewall of the gate electrode and the surface of the semiconductor substrate and a silicon nitride film 6 which is formed on the TEOS NSG film. The transistor provides an improvement in the hot carrier resistance and is highly reliable, with the ON current showing little change over a long period.
Description
2336719 1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
The present invention relates to a semiconductor device and a method of manufacture. In a particular device and manufacturing method to be described below, by way of example in illustration of the invention an insulating film is formed at a sidewall of a gate electrode in a MOSFET (metal-oxide5 semiconductor field effect transistor).
As attempts to achieve a higher degree in the integration, or the further miniaturization, of semiconductor devices have progressed in recent years, hot carders have become a major concern.
Reference will now be made to Fig. 6 of the accompanying drawings which shows a cross-section through a previously proposed semiconductor device which aims to overcome this problem. In Fig. 6 there is shown a MOSFET with a lightly-doped drain (LDD) structure having a sidewall insulating film 12. Such a MOSFET may be manufactured in the following way. A gate oxide film 2 and a gate polysilicon 3 may be grown and then patterned into the shape of a gate electrode, and thereafter, using these as a mask, dopants are injected into a shallow region within a silicon substrate 11 using ion implantation. After that, a sidewall insulating film 12 is formed and then, using the sidewall insulating film as a mask, dopants are further injected into a deeper region within the silicon substrate 11 by means of ion implantation. Subsequent thermal annealing accomplishes the formation of a source-drain region 7 with an LDD structure.
For the sidewall insulating film, a silicon nitride film, a high temperature oxide (HTO) film, a tetraethylorthosilicate (TEOS) non-doped silicate glass (NSG) film and the like have been investigated. The silicon nitride film has, however, an insufficient hot carder resistance and its ON 2 current and threshold voltage increase with time. This is ascribed to a liability to the generation of the interfacial energy level between the silicon nitride film and the silicon substrate, resulting from a good deal of hydrogen contained in the silicon nitride film.
Therefore, in the current circumstances, an HTO film or a TEOS NSG film is being used as a sidewall insulating film, although there is a continuous demand for a further improvement in the hot carrier resistance.
Features of an arrangement to be described below, by way of example in illustration of the present invention are that, as a result of an improvement in the hot carrier resistance of a MOSFET using a sidewall insulating film, there is obtained a highly reliable semiconductor device with an ON current which shows little change over a long period.
In a particular semiconductor device to be described below, by way of example in illustration of the invention there is, upon a semiconductor substrate, a gate insulating film, a gate electrode, a source-drain region, and a sidewall insulating film formed at a sidewall of the gate electrode, wherein the sidewall insulating film has a double layered structure including a TEOS NSG film which is in contact with both the sidewall of the gate electrode and the surface of the semiconductor substrate, and a silicon nitride film which is formed on the TEOS NSO film.
Further, in illustration of the present invention there will be described by way of example a method of manufacturing a semiconductor device which includes the steps of forming a gate insulating film and a gate electrode into a prescribed shape on a semiconductor substrate, injecting dopants into a shallow region within the semiconductor substrate by means of ion implantation using the gate electrode as a mask, forming a sidewall insulating film at a side face of the gate electrode, and injecting dopants into a deeper 3 region within the semiconductor substrate by means of ion implantation using the gate electrode as well as the sidewall insulating film as a mask, thereby forming a source-drain region, wherein the formation of the sidewall insulating film is carded out by growing a TEOS NSG film and a silicon nitride film in 5 succession and etching back thereafter.
The following description and drawings disclose, by way of example, the invention, the scope of whose protection is set out in the appended claims.
In the drawings:- Fig. 1 is a cross-sectional view showing one example of a semiconductor device, Fig. 2 is a series of views illustrating steps of a manufacturing method of a semiconductor device, Fig. 3 is a set of diagrams illustrating a method of evaluating the hot carTier resistance, Fig. 4 is a graph of the ON current change A Ion plotted against the stress application time, for the semiconductor devices of the embodiments and the comparative examples, and Fig. 5 is a cross-sectional view showing another example of a semiconductor device.
Explanation of symbQ]s:
1 2 4 Semiconductor substrate Gate insulating film 2a........ Gate oxide film Gate electrode Gate polysilicon LIDD region 4 6 7 8 11 12 14 15 TEOS NSG film Silicon nitride film Source-drain region Titanium silicide layer Silicon substrate Sidewall insulating film region with a high doping concentration region with a low doping concentration Referring to Fig. 1, which illustrates one example of a MOSFET that is a semiconductor device, there is a gate electrode 3 having side faces and a gate insulating film 2. On each of the side faces of the electrode 3 there is a sidewall insulating film having a double layered structure including a TEOS NSG film 5, and a silicon nitride film 6 which is formed on the TEOS NSG film 5. Of these two films, it is only the TEOS NSG film 5 that comes into contact with the surface of the semiconductor substrate 1.
Should the TEOS NSG film 5 be too thick or too thin, its effect may not be sufficient, and the film thickness thereof is preferably between 50 to 500 A, and most preferably between 100 to 300 A.
Further, when the thickness of the TEOS NSG film 6 is represented by W and the height of the sidewall insulating film made up of both the TEOS NSG film 5 and the silicon nitride film 6 is represented by W', as shown in Fig.
1, h is preferably between 2.5 to 37% of H and, and most preferably between to 24% of H.
Further, the semiconductor device preferably has an LDID structure.
That is, within the portion ot the substrate underlying the sidewall insulating film, there exists a tightly doped drain (LIDD) region 4 in which dopants are injected into a shallow region. Dopants are further injected into a deeper region in the portion of a source-drain region that is uncovered with the sidewall insulating film and this region, together with the LIDID region constitutes the source-drain region 7. In practical devices, however, the LIDID region tends to extend into a part under the gate insulating film due to thermal diffusion, and the deeply doped region also tends to extend to a part under the sidewall insulating film.
Further, a semiconductor device may have a double doped drain (or double diffused drain DIDID) structure. In the DIDID structure, as shown in Fig.
5, a source-drain region consists of a region 15 with a low doping concentration which is formed by injecting dopants in the portion underlying the sidewall insulating film, and a region 14 with a high doping concentration which is formed by injecting dopants into a shallower region outside of the sidewall insulating film. Employing such a DIDID structure, can improve the hot carder resistance.
One example of a manufacturing method illustrative of the present invention will now be described.
As shown in Fig. 2 (a), a gate oxide film 2a is formed by means of thermal oxidation to a thickness of 40 A on a silicon substrate 11, and then a gate polysilicon 3a is deposited thereon by the chemical vapour deposition (CVD) method to a thickness of 1500 A.
The gate oxide film 2a and gate the polysilicon 3a are patterned, by means of lithography and dry etching, into the shape of a gate electrode, as shown in Fig. 2 (b), and formed into a gate insulating film 2 and a gate electrode 3, respectively.
Next, as shown in Fig. 2(c), using this gate electrode as a mask, arsenic ion is injected through the surface of the silicon substrate 11 with a 6 dose concentration of 2.5 x 10 13 cm-2 and an implantation energy of 30keV, and thereby a shallow doped region 4 is formed.
On to this substrate surface, a TEOS NSG film 5 is grown to a thickness of 100 to 200 AS by the low pressure WID (LPCVD) method the degree of vacuum being 1 Torr and the substrate temperature being 600 to 7000C while tetraethylorthosilicate is fed in at 300 sccm (standard cubic centimeters per minute). Subsequently, a silicon nitride film 6 is grown to a thickness of 800 to 900 AS by the LPCVD method, the degree of vacuum being 0.25 Torr and the substrate temperature being 700 to 800"C, while 10dichlorosilane (SiH2C'2) and ammonia (NH3) are fed in at 60 sccm and 600 sccm, respectively. Thereby, the structure shown in Fig. 2(d) is formed.
This structure in which the TEOS NSG film 5 and the silicon nitride film 6 are layered is subjected to dry etching, and thereby a sidewall insulating film having a double layered structure made up of the TEOS NSG film 5 and the silicon nitride film 6 is formed, as shown in Fig. 2(e).
Next, as shown in Fig. 2(f), using the gate electrode and the sidewall insulating film as a mask, arsenic ion is injected through the surface of the substrate into a deeper region, the dose concentration being 2.0Xl 015 cm-2 and the implantation energy being 50keV, and then, by performing thermal annealing, a source-drain region 7 with an LIDID structure is obtained.
Thereafter, a titanium film is applied to the surface of this structure and after the heat treatment the unreacted titanium is removed, and thereby a titanium silicide layer 8 is formed over the surface of the source-drain region as well as the surface of the gate electrode.
Measurements of the hot carder resistance will now be described.
At the time of stress application, respective electrodes are taken as shown in Fig. 3(a) and the voltage condition is given at VD=2.25V and 7 VS= VB= OV. As VG'S varied, the substrate current 'B becomes a maximum at a certain VG, as shown in Fig. 3(b). Because the degradation in the characteristics of transistors is the severest, VG is set to be at this value during the stress application.
When the characteristics of the transistors are measured, the source electrode and the drain electrode are interchanged, as shown in Fig. 3(c), and the drai n current 'D 'S measured at VS = VB= OV, and VG = VID = 1.8V, which is taken as the ON current 'ON. The amount of 'ON degradation A 'ON is then obtained by the following equation.
A 'ON= ( 'ON - the initial value-of 'ON) 1 the initial value of ION Fig 4 shows a graph of the amount of 'ON degradation, A 'ON plotted against the stress time, for a first embodiment (a TEOS NSG film 100 A thick and a silicon nitride film 900 A thick) and a second embodiment (a TEOS NSG film 200 A thick and a silicon nitride film 800 A thick).
Some comparative examples will now be described.
For comparison, respective sidewall insulating films are formed under the following conditions.
Comparative Example 1: An HTO film with a thickness of 1000 A.
Comparative Example 2: A TEOS NSG film with a thickness of 1 ooo A.
Comparative Example 3: A silicon nitride film with a thickness of 1000 A.
Comparative Example 4: An HTO film with a thickness of loo A (a lower layer) and a silicon nitride film with a thickness of goo A (an upper layer).
Comparative Example 5: An HTO film with a thickness of 200 A (a lower layer) and a silicon nitride film with a thickness of 800 A (an upper layer).
In these comparative examples, the HTO films are grown by the 1-PCVID method, the degree of vacuum being 0.9 Torr and the substrate temperature being 8000C, while silane (SiH4) and nitrogen oxide (N20) are fed 8 at 90 sccm and at 1200 sccm, respectively. The TEOS NSG films and the silicon nitride films are formed in the same way as in the arrangements described above and different film thicknesses are obtained by changing the deposition times.
As seen clearly in Fig. 4, semiconductor devices that have been described have comparatively large hot carder resistance and show little change in ON current.
Further, while the arrangements described above have been described with reference to NMOS (N-channel MOS) devices, they apply 10 equally to PNOS (P-channel MOS) devices.
The arrangements and manufacturing methods described above are able to provide an improvement in the hot carrier resistance of a MOSFET device that utilizes a si dewall insulating film, and a highly reliable semiconductor device with an ON current showing little change over a long 15 period.
It will be understood that, although particular arrangements have been described, by way of example, with reference to the accompanying drawings, variations and modifications thereof, as well as other arrangements, may be conceived within the scope of the appended claims.
9
Claims (10)
1. A semiconductor device including, upon a semiconductor substrate, a gate insulating film, a gate electrode, a source-drain region, and a sidewall insulating film formed at a sidewall of the gate electrode, wherein the sidewall insulating film has a double layered structure made up of a TEOS NSG film which is in contact with both the sidewall of the gate electrode and the surface of the semiconductor substrate, and a silicon nitride film which is formed on the TEOS NSG film.
2. A semiconductor device as claimed in Claim 1, wherein the sourcedrain region includes an LIDID structure.
3. A semiconductor device as claimed in Claim 1, wherein the TEOS NSG film has a thickness of 50 to 500 A.
4. A semiconductor device as claimed in Claim 2, wherein the TEOS NSG film has a thickness of 50 to 500 A.
5. A method of manufacturing a semiconductor device which includes the steps of forming a gate insulating film and a gate electrode into a prescribed shape on a semiconductor substrate, injecting dopants into a shallow region within the semiconductor substrate by means of ion implantation using the gate electrode as a mask, forming a sidewall insulating film at a side face of the gate electrode, and injecting dopants into a deeper region within the semiconductor substrate by means of ion implantation using the gate electrode as well as the sidewall insulating film as a mask, thereby forming a source-drain region, wherein the formation of the sidewall insulating film is carded out by first growing a TEOS NSG film and a silicon nitride film in succession and then etching back.
6. A method of manufacturing a semiconductor device as claimed in Claim 5, wherein the TEOS NSG film and the silicon nitride film are in successive layers having a thickness of 50 to 500 A for the TEOS NSG film and 300 to 200o A for the silicon nitride film.
7. A method of manufacturing a semiconductor device as claimed in Claim 5, wherein the TEOS NSG film is grown by the CVD method in which the substrate has a temperature between 600 and 7000C.
8. A method of manufacturing a semiconductor device as claimed in Claim 6, wherein the TEOS NSG film is grown by the CM method in which the substrate has a temperature between 600 and 70TC.
9. A semiconductor device, as claimed in claim 1, substantially as described herein with reference to any one of Figs. 1 to 5 of the accompanying drawings.
10. A method of manufacturing a semiconductor device, as claimed in claim 5, substantially as described herein with reference to any one of Figs. 1 to 5 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10109734A JP3107157B2 (en) | 1998-04-20 | 1998-04-20 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9909042D0 GB9909042D0 (en) | 1999-06-16 |
| GB2336719A true GB2336719A (en) | 1999-10-27 |
Family
ID=14517899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9909042A Withdrawn GB2336719A (en) | 1998-04-20 | 1999-04-20 | Sidewall insulating films for field effect transistors |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP3107157B2 (en) |
| KR (1) | KR19990083320A (en) |
| CN (1) | CN1233857A (en) |
| GB (1) | GB2336719A (en) |
| TW (1) | TW410372B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4215787B2 (en) | 2005-09-15 | 2009-01-28 | エルピーダメモリ株式会社 | Semiconductor integrated circuit device and manufacturing method thereof |
| CN102201341B (en) * | 2010-03-22 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Manufacture the method for nmos pass transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0506287A1 (en) * | 1991-03-27 | 1992-09-30 | AT&T Corp. | Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology |
| WO1997002594A1 (en) * | 1995-07-03 | 1997-01-23 | Intel Corporation | Low damage source and drain doping technique |
| WO1997013273A1 (en) * | 1995-10-04 | 1997-04-10 | Intel Corporation | Formation of source/drain from doped glass |
| EP0776034A2 (en) * | 1995-11-21 | 1997-05-28 | Texas Instruments Incorporated | Method of manufacturing a CMOS |
-
1998
- 1998-04-20 JP JP10109734A patent/JP3107157B2/en not_active Expired - Fee Related
-
1999
- 1999-04-17 TW TW088106181A patent/TW410372B/en not_active IP Right Cessation
- 1999-04-19 KR KR1019990013891A patent/KR19990083320A/en not_active Application Discontinuation
- 1999-04-20 CN CN99106018A patent/CN1233857A/en active Pending
- 1999-04-20 GB GB9909042A patent/GB2336719A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0506287A1 (en) * | 1991-03-27 | 1992-09-30 | AT&T Corp. | Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology |
| WO1997002594A1 (en) * | 1995-07-03 | 1997-01-23 | Intel Corporation | Low damage source and drain doping technique |
| WO1997013273A1 (en) * | 1995-10-04 | 1997-04-10 | Intel Corporation | Formation of source/drain from doped glass |
| EP0776034A2 (en) * | 1995-11-21 | 1997-05-28 | Texas Instruments Incorporated | Method of manufacturing a CMOS |
Also Published As
| Publication number | Publication date |
|---|---|
| TW410372B (en) | 2000-11-01 |
| KR19990083320A (en) | 1999-11-25 |
| JP3107157B2 (en) | 2000-11-06 |
| GB9909042D0 (en) | 1999-06-16 |
| CN1233857A (en) | 1999-11-03 |
| JPH11307759A (en) | 1999-11-05 |
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| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |