TW396474B - Method for forming bump bondings - Google Patents

Method for forming bump bondings Download PDF

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Publication number
TW396474B
TW396474B TW087110591A TW87110591A TW396474B TW 396474 B TW396474 B TW 396474B TW 087110591 A TW087110591 A TW 087110591A TW 87110591 A TW87110591 A TW 87110591A TW 396474 B TW396474 B TW 396474B
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TW
Taiwan
Prior art keywords
substrate
conductive
forming
tape
patent application
Prior art date
Application number
TW087110591A
Other languages
English (en)
Inventor
Kosuke Inoue
Tatsuya Yoneda
Takamichi Suzuki
Ryosuke Kimoto
Junichi Suzuki
Original Assignee
Hitachi Ltd
Hitachi Tokyo Electronics
Hitachi Vlsi System K K
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Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Tokyo Electronics, Hitachi Vlsi System K K filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW396474B publication Critical patent/TW396474B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
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    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10681—Tape Carrier Package [TCP]; Flexible sheet connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0338—Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/08—Treatments involving gases
    • H05K2203/081—Blowing of gas, e.g. for cooling or for providing heat during solder reflowing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1545—Continuous processing, i.e. involving rolls moving a band-like or solid carrier along a continuous production path
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/51—Plural diverse manufacturing apparatus including means for metal shaping or assembling
    • Y10T29/5136—Separate tool stations for selective or successive operation on work
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/5142—Separate tool stations for selective or successive operation on work including assembling or disassembling station and means to sever work from supply

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Description

經淤部中央樣率工消货合作社印聚 A7 B7 五、發明説明（i ) 本發明係有關在半導體封裝形態之中，於作爲與安裝 基板之接續材使用B G A ( Ball Grid Array )封裝、 C S.P ( Chip Size Package 或 Chip Scale Package )等 焊錫球之封裝（以下單以封裝稱之）搭載代表錫球及金屬 球之導電性球，被稱作隆起接點之接續用隆起之形成方法 〇 而近年被多數使用在入出力端子的L S I之半導體封 。.裝基板等之中係採用，在其下方設置配置成格子狀或鋸齒 格子狀之複數電極，再將與因應這些之電路基板之電路電 極，由隆起接點來進行接續之構造。 而作爲形成焊錫隆起接點之方法係在日本特特開平8 —1 1.5 9 1 6及日本特開平9 一.0 6 3 7 3.7等揭示過 。於此公開公報係揭示有，根據：由吸著模具所真空吸引 之錫球浸泡在焊劑液槽來供給焊劑於錫球，再將此錫球轉 印在形成於半導體封裝基板之墊片上（接續端子），然後 將根據焊劑之粘著力，保持粘著錫球（暫時固定）之電路 基板進行加熱（回流），形成焊錫隆起接點之技術及轉印 搭載錫球在半導體封裝基板上之裝置。另外，對於加熱來 說，使用針對流通在一般市場上之回流爐即可。 但，對於上述以往之方法來說，有著下記所述問題。 對於半導體封裝基板來說，帶狀可導性構成則是最近 被廣範的使用。而圖1 2所示爲使用如此之可導性基板之 半導體封裝之例。針對圖1 2、3係爲可導性基板、15 係爲焊錫隆起接點、4係爲形成焊錫隆起接點之墊片、 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)
A7 B7 ------------ 五、發明説明（2 ) 11係半導體晶片、19係爲接續墊片4與半導體晶片 11之卷帶、18係固定樹脂，來固定半導體晶片11與 可導性基板3、1 7係呈口字形之補強板。 本發明之目的係爲提供：利用簡單之製造、組裝方法 來形成隆起接點在基板之隆起接點之形成方法。 而本發明之其他目的係爲提供信賴信優越、形成隆起 接點在半導體基板上之隆起接點形成方法。 而再來之目的係爲提供：以低成本可形成隆起接點在 半導體基板上之隆起接點形成方法。 利用前述之1可導性基板的半導體封裝情況，在形成隆 .¾ 起接點時，爲了使用對於以往非可導體基板之製造裝置， 預先將此半導體封裝基板切斷成小單位之長方形。並且， 針對隆起接點形成後之半導體封裝組裝之最終工程，因將 半導體封裝基板切斷成最小單位，所以必須進行二次切'斷 工程。因而有著形成隆起接點高成本之問題。 經浐部中央樣本^只工消费合作社印掣 {請先閲讀背面之注意事項再填寫本頁) 更加地爲了投入切斷成長方形之半導體封裝基板於轉 印搭載錫球之裝置的錫球mounter及加熱用回流爐係降低 剛性之處理則爲困難，由大致將封裝基板固定在剛性高之 專用負荷裝配架，使其容易處理則爲必要。對於專用負荷 裝配架來說則要求尺寸精確度，而固定於專用負荷裝配架 之作業係主要以手來進行。如此以往係準備配合製品生產 量數量之高價的專用負荷裝配架，且因進行固定切斷成長 方形之半導體封裝基板於專用負荷裝配架上，所以有著形 成隆起接點之高成本問題。 本紙張尺度適用中國國家標準（CNS ) A4現格（210X297公釐） ~~ 經济部中央榀準沁只工消贽合作社印^ A7 __ B7 五、發明説明（3 ) 而爲了解決如此問題點係有著將錫球mounter 1 4及 回流爐各自可連續地供給帶狀半導體封裝基板地改造之後 ，再將錫球mounter與回流爐一體化，然後再由將錫球轉 印搭載完成之半導體封裝基板放入於回流爐，如此則不需 要專用負荷裝配架與爲了形成隆起接點之基板切斷工程之 想法。 但，此方法之中，當發生狀況在進行錫球轉印搭載之 。錫球mounter而裝置停止之情況，防止放置在回流爐內曝 熱於高溫中之半導體封裝基板的損傷則爲困難。另，錫球 轉印搭載所需時初係一般來說爲根據是否有再動作而變化 . ^ - ，但加熱時間之變動係牽連著接續在錫球及半導體封裝基 板之半導體所接受之熱能流量的變動，而產生隆起接點形 成不良的原因。因此，針對隆起接點之形成，加熱時間的 變動係不被允許的，而將錫球mounter與回流加熱爐二體 化係在兩個裝置的性質上來說，在現階段係無法實現。 而針對本發明，解決上述問題點，關於帶狀半導體封 裝基板，.實現不使用專用負荷裝配架，且不需要爲了形成 隆起接點之基板切斷工程。 而爲了上述目的，對於錫球mounter利用卷帶供給帶 狀半導體封裝基板，在轉印搭載錫球後，暫時將同基板卷 入在卷帶。另，不將被轉印搭載之暫時固定的錫球掉落地 使用於錫球轉印搭載時之焊劑等固定液之粘著力係對於錫 球的質量與運送時，比錫球承受各種加速度的積還大。還 有不會因機械之接觸而使被轉印搭載暫時呈固定狀態的錫 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ~ ~~ ~ {請先閲讀背面之注意事項再填寫本頁)
訂I A 7 B7 五、發明説明（4 ) 球產生位置移動地，在將帶狀半導體封裝基板卷入於卷帶 時，插入襯墊在前述基板間以防止機械的接觸。 如根據本發明，對於作爲半導體封裝基板，被廣範使 用之帶狀可導性基板的隆起接點形成，可實現不需爲了形 成隆起接點之切斷工程及使用專用負荷裝配架，且低成本 之構成。並，可將普遍使用之錫球mounter及回流爐之改 造作爲最小限度。 ..〔圖 1〕 表示本發明之隆起接點形成之流程圖。 〔圖 2〕 " 表示對於搭載端以真空吸著錫球之方法的部份剖面圖 〇 、 〔圖3〕 表示對於搭載端將焊劑供給於真空吸著後之錫球的方 法之部份剖面圖。 〔圖4〕 表示搭載錫球於可導性基板之方法的部份剖面圖。 經漪部中决樣率^只工消費合作社印" (請先閲讀背面之注意事項再填寫本頁} 〔圖5〕 表示卷入實施錫球搭載後之可導性基板之方法圖。 〔圖6〕 表示襯墊帶之一剖份斜視圖。 〔圖7〕 表示將實施錫球搭載後之可導性基板與襯墊帶同時卷 入於基板卷帶狀態之剖面圖。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) ： 經浐部中央故準>CJh-T消势合作社印業 A7 B7 五、發明説明（5:) 〔圖8〕 表示卷入隆起接點形成完了之可導性基板與襯墊帶於 基板卷帶之狀態剖面圓。 〔圖 9〕 表示加熱搭載錫球之可導性基板，再形成隆起接點之 方法圖。 〔圖 1 0〕 _ 表示可導‘性基板之例圖。 〔圖 1 1〕 表示可導性基板之其他例圖。 3. · 〔圖 1 2〕 表示使用可導性基板之半導體封裝之例圖。 主要元件對照表 ' 1 錫球 2 焊劑 3 可導性基板 4 墊片 5 搭載端 6 基板卷帶 7 襯墊膜 8 襯墊帶 9 突起 10 加熱爐（回流爐） 本紙張尺度通用中國國家標準（CNS ) A4規格（210X297公釐） (讀先聞讀背面之注意事項再填寫本頁)
—8 - 經承部屮央极率而i=c.T消費合作社印絮 A7 _________ _B7 _ 五、發明説明（6 ) 11 半導體晶片 12 半導晶片接續部 13 傳送可導性基板之穿孔 1 5 隆起接點 1 6 半導體封裝 以下根據圖面詳細說明本發明的實施例。又，關於圖 、中的同一符號，因表示同一部位，所以有省略重覆說明之 情況。另，作爲導電性球之一例係將錫球關於作爲固定液 之一例使用焊劑'之隆起接點形成方法記載著，但本隆起接 點形成方法並不限定於此種組合，而作爲導電性球使用由 錫球以外之金屬製球、導電體所覆蓋之球也可以。另，作 爲取代焊劑之固定液，使用糊狀焊錫及導電性粒子配合之 接著劑也可以。. ' 圖1係爲表示本發明的隆起接點形成方法之基本流程 圖。而針對圖1、6係在最後工程切斷之後，卷入成爲半 導體封裝之可導性基板的基板卷帶，而1 6係爲半導體封 裝。首先針對a半導體晶片接續在可導性基板，再被樹脂 封裝。接著，可導性基板係如b所示卷入於基板卷帶。接 下來針對c，從基板卷帶6抽出可導性基板，然後再搭載 錫球。而搭載有錫球之可導性基板則如d再卷入於基板卷 帶。然後再針對e，從此基板卷帶6抽出搭載錫球之可導 性基板進行加熱。而根據加熱與冷卻，在可導性基板上形 成隆起接點，再將此，如f所示地卷入於基板卷帶6。此 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)
經濟部中央標準局負工消費合作社印製 A7 ____^_^B7___ 五、發明説明（7 ) 後再洗淨可導性基板，而再進行，切斷來完成半導體封裝 。又，針對洗淨來說也可在卷入於基板卷帶6之狀態下來 進行洗淨，另從基板卷帶帶抽出可導性基板來進行洗淨也 可以。另，針對客戶的希望係不進行切斷而卷入在基板卷 帶的狀態下出貨，而這些則因應客戶的希望，也有將此切 斷之情況。 而在以下關於圖1所示流程有著更詳細說明。從圖2 至圖4之中，圖1之c所表示的係錫球搭載方法。針對各 圖1係錫球，2係焊劑，3係可導性基板，4係形成在可 導性基板上的^片，5係搭載端，1 1係半導體晶片。 於圖2係表示供給錫球在搭載端5之方法。而錫球1 係安置在其底面呈網格狀膜之球容器內，再由氣流往上通 過網格狀膜。而在球體容器上方係安置有搭載端5，根據 真空吸引真空吸著錫球於多數之各球體吸引口。' 圖3係表示對於真空吸著之錫球的焊劑供給方法。焊 劑2係預先塗上在焊劑塗覆片上。而真空吸著錫球之搭載 5係接觸靠近於此焊劑塗覆片上之焊劑面。由此焊劑則供 給於各錫球1。 而圖4係表示搭載錫球1於可導性基板3上之方法， 真空吸著錫球之搭載端則靠近於接續半導晶片11之可導 性基板3 ,再按在各錫球1，斷絕真空吸引，然後由大氣 開放或賦予相反的正壓，錫球/則由焊劑2之粘著力搭載 在可導性基板3上之墊片4上。又當錫球1沒有正確地搭 載在墊片4之情況，設置有將各錫球1突出於搭載端5內 本紙張尺度適用中國國家標準（CNS〉A4規格（210X297公釐） ―- ~ -10- (讀先鬩讀背面之注意事項再填寫本頁)
、1T #-· 經漪部中央樣4'·而卩工消费合作社印製 A7 B7 五'發明説明（8) 部之栓，然後將此推出之構造，再利用此，可確實地實現 錫球1之搭載。 焊劑2之供給係可以由在搭載錫球1之前，於墊片4 上以一般的絲網印刷及轉印法，或調配劑來進行，而作爲 焊劑2係不將由於之後的搬運之衝擊及作業員之不良處理 等而使錫球掉落，其粘著力則有必要使用比錫球1之質理 與錫球/搭載'於可導性基板3之後的可能承受之加速度還. 、大的積之構成。而所必要之焊劑粘著力的値係根據使用之 裝及錫球尺寸而有的變化，但由選擇1 〇 〇 g f以之構成 ’在一般的環g下係可完全地防止錫球的落下。又，此時 的焊劑2粘著力測試係利用例如：M A L C Ο Μ公司製之 糊狀粘著測試機等來測試即可。另.，焊劑2係如爲糊質導 電性，也可使用其他之材料，例如：使用糊質焊錫，包含 導電性粒子配合之接著劑固定液也可以。 ’ 圖1 0及圖1 1則表示針對本實施例之可導性基板3 。而可導性基板3係出自於聚酰亞胺等有著耐熱性及電氣 絕緣性良好之材料，並且形成金屬配線及.隆起接點。另 1 2係爲半導體晶片接續部，而1 3係爲使用於傳送可導 性基板3之穿孔。而表示於圖1 0之可導性基板3係配置 1個半導體晶片接續部1 2在寬度方向之例，而表示於圖 11之可導性基板3係配置2個半導體晶片接續部12在 寬度方向之例。針對圖1的.c，搭載錫球1之可導性基板 3係接著如圖1的d及圖5所示地卷入在基板帶。此時， 由錫球1與其他構成的接觸而爲了防止從墊片4上產生位 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X：297公釐) _ _ (請先閱讀背面之.注意事項再填寫本頁) 訂 經來‘部中央標準沁*.只工消費合作社印製 A7 B7 五、發明说明（9) 置移動及，從墊片4上掉落錫球1之情況’將襯墊膜7， 卷入於可導性基板3之間’而防止對於錫球1與機械性的 接觸。襯墊膜7係卷入於襯墊帶8，再與基板卷帶6之旋 轉同一時期送出襯墊膜7。圖6係以斜視圖表示襯墊膜7 之一部份。另，於圖7之中表示將搭載錫球1之可導性基 板3與襯墊膜7交互地卷入基板卷帶之情況，在圖5 A-B切斷部分之剖面圖。如此，襯墊膜7係其寬度則大略與 可導性基板3相同，而與可導性基板3重疊的狀態下，於 閃避可導性基板3上的錫球1之位置有著多數個突起9於 襯墊膜7兩面;£ Η形狀之斷面。另突起9之高度係比錫球 1之高度及接續於可導性基板相反面之半導體晶片1 1的 可導性基板3面的突出量還高。因此，在襯墊膜7之可導 性基板3上之錫球1並無接觸其他的構件，進而可防止錫 球1從可導性基板3上的墊片4移位及脫落。又，襯墊7 之材料爲廉價之壓克力，因不會曝曬於高溫下，所以可以 重覆使用。對於有著產生靜電之虞的情況，也可使用導電 性壓克力之材料。 針對圖1之d，卷入在基板卷帶6之可導性基板3係 繼續加熱、而在圖9所示之加熱工程之中，在搭載錫球1 之後，從卷入可導性基板3與襯墊膜7之基板卷帶6抽出 可導性基板3，再導入於回流爐等加熱爐進行加熱使錫球 1熔解。並且由之後的冷卻將熔解的錫球1固體化而形成 隆起接點。如圖9所示，從基板卷帶6抽出可導性基板3 時，一起與可導性基板3卷入之襯墊膜7係由襯墊帶8卷 i紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 一 _ -12 - (請先閱讀背面之注意事項再填寫本頁) 訂 B7 五、發明説明（10) 入。而根據加熱爐所產生形成之隆起接點的可導性基板3 係配合接下來之工程情況，再次卷入於基板卷帶中也可以 ’而切斷成一定尺寸也可以，但，在本實施例之中，如圖 1之ί及圖9所示，再次卷入於與之前不同之基板卷帶 6 b之例。而對於被形成之隆起接點及可導性基板3有著 劣質產生之情況，在卷入於基板卷帶時，使用襯墊膜7 b 也還是有效。而圖8所示係在形成隆起點後，將卷入形成 /隆起接點完了之可動基板3於其他基板卷帶6 b之狀態， 在圖9 C - D所切斷之部份剖面圖。而此襯墊膜7 b係與 搭載錫球1於Y導性基板3上之後可使用之材料，基本上 來說爲相同，但突起9之高度係有必要比被形成之隆起接 點1 5的高度還高。另，卷入後之可導性基板3係因應需 要，以卷入在基板卷帶6 b之狀態下成批投入於洗淨機， 除去壓克力等殘留物。 ' 經"1部中央樣4,-而只工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 其他，由加熱形成隆起接點之後，因即刻進行可導性 基板3之洗淨，所以在圖3所示之加熱爐1 0之後也可插 入市販的連續洗淨裝置。另，如圖1之f、 g、 h所示， 從基板卷帶6抽出可導性基板3，將此連續性的洗淨，之 後再卷入於基板卷帶6之中也可以。在這些情況，.不管在 洗淨後將以小單位切斷可導性基板3。 相反地也可以小單位切斷隆起接點形成完了後之可導 性基板之後，以成批式洗淨裝置來洗淨壓克力等之殘留物 的洗淨。 根據本實施形態解決針對以往形成隆起接點的問題， 本紙張尺度用中國國家標準（CNS ) A4規格（210X297公釐） ~ A 7 B7 五、發明説明（11 ) 關於帶狀半導體封裝基板，可實現不使用專用負荷裝配架 ，且不需要爲了形成隆起接點之基板切斷工程之隆起接點 形成方法。 (讀先閱讀背面之注意事項再填寫本頁) ,袈. -0 經濟部中央標準局員工消費合作社印策 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -14-

Claims (1)

  1. 經濟部中央標準局身工消费合作社印裝 、申請專利範圍 1 種隆起接點形成方法，其特徵爲：由搭載半導 體晶片於可導性基板之步驟及，使用焊劑、糊質焊錫、已 含導電性粒子配合之接著劑固定液之任何一種導電性糊劑 來暫時固定於與設置導電性球在前述可導性基板上之半導 體晶片進行電氣接續之墊片步驟及，將暫時固定前述導電 性球之前述可導性基板卷入於卷帶之步驟及，從卷帶抽出 暫時固定前述導電性球之前述可導性基板，再加熱暫時被 固定之導電性球之前述可導性基板形成隆起接點之步驟及 ，將形成前述隆起接點之前述可導性基板卷入於卷帶之步 驟及，由洗淨/切斷前述可導性基板來形成半導體封裝步 % 驟來形成。 2 .如申請專利範圍第1項之隆起接點形成方法，其 中將暫時固定前述導電性球之前述基板卷入於卷帶時，插 入襯墊於前述基板之間。 3 .如申請專利範圍第2項之隆起接點形成方法，其 中從前述卷帶將前述襯墊與前述基板分離，再將前述基板 進行加熱工程。 4 .如申請專利範圍第3項之隆起接點形成方法，其 中在加熱工程之後卷入前述基板於前述卷帶中。 5.如申請專利範圍第4項之隆起接點形成方法，其 中在加熱工程之後，將前述基板卷入於卷帶時，插入前述 襯墊在前述基板之間。 6 .如申請專利範圍第4項之隆起接點形成方法，其 中在加熱工程之後，且在將前述基板卷入於前述卷帶之前 (請先聞讀背面之注#^項再填寫本頁) -* r 衣紙張尺度適用中國困家椹率（CNS ) A4就格（210 X 297公釐） .15- Α8 Β8 C8 D8 々、申請專利範園 ，將前述基板洗淨。 7 .如申請專利範圍第4項之隆起接點形成方法，其 中在加熱工程之後，卷入前述基板於前述卷帶之狀態下來 洗淨。 8 .如申請專利範圍第3項之隆起接點形成方法，其 中在加熱工程之後，以小單位切斷前述基板。 9 .如申請專利範圍第8項之隆起接點形成方法，其 中將前述基板切斷後再洗淨。 1〇.如申請專利範圍第2項之隆起接點形成方法， 其中大致將前辨襯墊剖面形狀成爲Η狀，再將與導電性粒 子對面之凹部深度作爲比導電性球的直徑以上。 1 1 .如申請專利範圍第5項之隆起接點形成方法， 其中大致將前述襯墊剖面形狀成爲Η狀，再將與針對加熱 工程所形成之隆起接點對面之凹部深度，作爲比前述隆起 接點之高度以上。 (請先閲讀背面之注$項再填寫本頁) 訂 ΘΤ. 經濟部中央標率局属工消费合作社印製
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JP2004537853A (ja) 2001-08-01 2004-12-16 リロジックス・インコーポレイテッド・ドゥーイング・ビシネス・アズ・アールディー・オートメーション 基板に半導体素子を取り付けるための工程、装置、及びこれに必要な部品
US7032807B2 (en) * 2003-12-23 2006-04-25 Texas Instruments Incorporated Solder contact reworking using a flux plate and squeegee
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