TW373236B - Method for making interconnect for low temperature chip attachment - Google Patents

Method for making interconnect for low temperature chip attachment

Info

Publication number
TW373236B
TW373236B TW086114112A TW86114112A TW373236B TW 373236 B TW373236 B TW 373236B TW 086114112 A TW086114112 A TW 086114112A TW 86114112 A TW86114112 A TW 86114112A TW 373236 B TW373236 B TW 373236B
Authority
TW
Taiwan
Prior art keywords
mold
interconnect material
solder
aligned
electronic device
Prior art date
Application number
TW086114112A
Other languages
English (en)
Inventor
Daniel George Berger
Guy Paul Brouillette
David Hirsch Danovitch
Peter Alfred Gruber
Bruce Lee Humphrey
Liehr Michael
Thomas Motsiff Willam
Juan Sambucetti Carlos
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW373236B publication Critical patent/TW373236B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/3457—Solder materials or compositions; Methods of application thereof
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
TW086114112A 1996-09-25 1997-10-09 Method for making interconnect for low temperature chip attachment TW373236B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/710,992 US6127735A (en) 1996-09-25 1996-09-25 Interconnect for low temperature chip attachment

Publications (1)

Publication Number Publication Date
TW373236B true TW373236B (en) 1999-11-01

Family

ID=24856347

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086114112A TW373236B (en) 1996-09-25 1997-10-09 Method for making interconnect for low temperature chip attachment

Country Status (4)

Country Link
US (2) US6127735A (zh)
JP (1) JPH10107066A (zh)
KR (1) KR100267874B1 (zh)
TW (1) TW373236B (zh)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US6127735A (en) 2000-10-03
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JPH10107066A (ja) 1998-04-24

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