TW364117B - Semiconductor memory device having main word lines and sub word lines - Google Patents

Semiconductor memory device having main word lines and sub word lines

Info

Publication number
TW364117B
TW364117B TW085107210A TW85107210A TW364117B TW 364117 B TW364117 B TW 364117B TW 085107210 A TW085107210 A TW 085107210A TW 85107210 A TW85107210 A TW 85107210A TW 364117 B TW364117 B TW 364117B
Authority
TW
Taiwan
Prior art keywords
word lines
sub
main
memory device
semiconductor memory
Prior art date
Application number
TW085107210A
Other languages
English (en)
Inventor
Yasushi Matsubara
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Application granted granted Critical
Publication of TW364117B publication Critical patent/TW364117B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
TW085107210A 1995-06-07 1996-06-15 Semiconductor memory device having main word lines and sub word lines TW364117B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07140325A JP3102302B2 (ja) 1995-06-07 1995-06-07 半導体記憶装置

Publications (1)

Publication Number Publication Date
TW364117B true TW364117B (en) 1999-07-11

Family

ID=15266199

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085107210A TW364117B (en) 1995-06-07 1996-06-15 Semiconductor memory device having main word lines and sub word lines

Country Status (4)

Country Link
US (1) US5764585A (zh)
JP (1) JP3102302B2 (zh)
KR (1) KR100243456B1 (zh)
TW (1) TW364117B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6191999B1 (en) * 1997-06-20 2001-02-20 Fujitsu Limited Semiconductor memory device with reduced power consumption
KR100257580B1 (ko) * 1997-11-25 2000-06-01 윤종용 반도체 메모리 장치의 번-인 제어 회로
KR100326939B1 (ko) * 1999-09-02 2002-03-13 윤덕용 고속 열 사이클이 가능한 메모리의 파이프라인 구조
KR100334573B1 (ko) 2000-01-05 2002-05-03 윤종용 계층적인 워드 라인 구조를 갖는 반도체 메모리 장치
US6545923B2 (en) 2001-05-04 2003-04-08 Samsung Electronics Co., Ltd. Negatively biased word line scheme for a semiconductor memory device
US20030145255A1 (en) * 2002-01-15 2003-07-31 Harty Anthony Walter Hierarchical multi-component trace facility using multiple buffers per component
JP4769548B2 (ja) * 2005-11-04 2011-09-07 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体記憶装置
JP2007257707A (ja) * 2006-03-22 2007-10-04 Elpida Memory Inc 半導体記憶装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6228516A (ja) * 1985-07-26 1987-02-06 Hitachi Ltd クランク軸の製作方法
JPS63225991A (ja) * 1987-03-16 1988-09-20 Hitachi Ltd 半導体記憶装置
JPH01245489A (ja) * 1988-03-25 1989-09-29 Hitachi Ltd 半導体記憶装置
JPH05182461A (ja) * 1992-01-07 1993-07-23 Nec Corp 半導体メモリ装置
JP2812099B2 (ja) * 1992-10-06 1998-10-15 日本電気株式会社 半導体メモリ
JPH07107799B2 (ja) * 1992-11-04 1995-11-15 日本電気株式会社 半導体メモリ装置
JPH0798989A (ja) * 1993-09-29 1995-04-11 Sony Corp 半導体メモリの制御回路
JP2842181B2 (ja) * 1993-11-04 1998-12-24 日本電気株式会社 半導体メモリ装置
JP3351595B2 (ja) * 1993-12-22 2002-11-25 株式会社日立製作所 半導体メモリ装置
JP3272888B2 (ja) * 1993-12-28 2002-04-08 株式会社東芝 半導体記憶装置
US5506816A (en) * 1994-09-06 1996-04-09 Nvx Corporation Memory cell array having compact word line arrangement
JP3333352B2 (ja) * 1995-04-12 2002-10-15 株式会社東芝 半導体記憶装置

Also Published As

Publication number Publication date
US5764585A (en) 1998-06-09
JPH08335391A (ja) 1996-12-17
JP3102302B2 (ja) 2000-10-23
KR970003240A (ko) 1997-01-28
KR100243456B1 (ko) 2000-03-02

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Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent