TW334568B - Erase method for page mode multiple bits-per-cell flash EEPROM - Google Patents

Erase method for page mode multiple bits-per-cell flash EEPROM

Info

Publication number
TW334568B
TW334568B TW086105318A TW86105318A TW334568B TW 334568 B TW334568 B TW 334568B TW 086105318 A TW086105318 A TW 086105318A TW 86105318 A TW86105318 A TW 86105318A TW 334568 B TW334568 B TW 334568B
Authority
TW
Taiwan
Prior art keywords
array
bit lines
threshold voltage
voltage level
per
Prior art date
Application number
TW086105318A
Other languages
English (en)
Inventor
Bill Colin
Su Jonathan
Gutala Ravi
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of TW334568B publication Critical patent/TW334568B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
TW086105318A 1996-08-22 1997-04-24 Erase method for page mode multiple bits-per-cell flash EEPROM TW334568B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/701,288 US5675537A (en) 1996-08-22 1996-08-22 Erase method for page mode multiple bits-per-cell flash EEPROM

Publications (1)

Publication Number Publication Date
TW334568B true TW334568B (en) 1998-06-21

Family

ID=24816766

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086105318A TW334568B (en) 1996-08-22 1997-04-24 Erase method for page mode multiple bits-per-cell flash EEPROM

Country Status (5)

Country Link
US (1) US5675537A (zh)
EP (1) EP0922285B1 (zh)
DE (1) DE69706873T2 (zh)
TW (1) TW334568B (zh)
WO (1) WO1998008225A1 (zh)

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US7023735B2 (en) * 2003-06-17 2006-04-04 Ramot At Tel-Aviv University Ltd. Methods of increasing the reliability of a flash memory
US7324374B2 (en) * 2003-06-20 2008-01-29 Spansion Llc Memory with a core-based virtual ground and dynamic reference sensing scheme
US6975535B2 (en) * 2003-08-14 2005-12-13 Mosel Vitelic, Inc. Electronic memory, such as flash EPROM, with bitwise-adjusted writing current or/and voltage
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Also Published As

Publication number Publication date
WO1998008225A1 (en) 1998-02-26
DE69706873D1 (de) 2001-10-25
EP0922285B1 (en) 2001-09-19
DE69706873T2 (de) 2002-06-13
EP0922285A1 (en) 1999-06-16
US5675537A (en) 1997-10-07

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