TW301777B - - Google Patents

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Publication number
TW301777B
TW301777B TW085100436A TW85100436A TW301777B TW 301777 B TW301777 B TW 301777B TW 085100436 A TW085100436 A TW 085100436A TW 85100436 A TW85100436 A TW 85100436A TW 301777 B TW301777 B TW 301777B
Authority
TW
Taiwan
Prior art keywords
nitride
etching
item
patent application
oxide
Prior art date
Application number
TW085100436A
Other languages
English (en)
Chinese (zh)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW301777B publication Critical patent/TW301777B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
TW085100436A 1995-05-08 1996-01-16 TW301777B (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/435,063 US5622596A (en) 1995-05-08 1995-05-08 High density selective SiO2 :Si3 N4 etching using a stoichiometrically altered nitride etch stop

Publications (1)

Publication Number Publication Date
TW301777B true TW301777B (enExample) 1997-04-01

Family

ID=23726810

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085100436A TW301777B (enExample) 1995-05-08 1996-01-16

Country Status (5)

Country Link
US (1) US5622596A (enExample)
EP (1) EP0742584A3 (enExample)
JP (1) JP3193632B2 (enExample)
KR (1) KR100209041B1 (enExample)
TW (1) TW301777B (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6040619A (en) * 1995-06-07 2000-03-21 Advanced Micro Devices Semiconductor device including antireflective etch stop layer
US5897372A (en) * 1995-11-01 1999-04-27 Micron Technology, Inc. Formation of a self-aligned integrated circuit structure using silicon-rich nitride as a protective layer
US6004875A (en) * 1995-11-15 1999-12-21 Micron Technology, Inc. Etch stop for use in etching of silicon oxide
US5973385A (en) * 1996-10-24 1999-10-26 International Business Machines Corporation Method for suppressing pattern distortion associated with BPSG reflow and integrated circuit chip formed thereby
US6136700A (en) * 1996-12-20 2000-10-24 Texas Instruments Incorporated Method for enhancing the performance of a contact
US6001268A (en) * 1997-06-05 1999-12-14 International Business Machines Corporation Reactive ion etching of alumina/TiC substrates
US5880005A (en) * 1997-10-23 1999-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a tapered profile insulator shape
US6207575B1 (en) * 1998-02-20 2001-03-27 Advanced Micro Devices, Inc. Local interconnect etch characterization using AFM
US6602434B1 (en) * 1998-03-27 2003-08-05 Applied Materials, Inc. Process for etching oxide using hexafluorobutadiene or related fluorocarbons and manifesting a wide process window
US6063711A (en) * 1998-04-28 2000-05-16 Taiwan Semiconductor Manufacturing Company High selectivity etching stop layer for damascene process
US5880006A (en) * 1998-05-22 1999-03-09 Vlsi Technology, Inc. Method for fabrication of a semiconductor device
JP4776747B2 (ja) * 1998-11-12 2011-09-21 株式会社ハイニックスセミコンダクター 半導体素子のコンタクト形成方法
US6268299B1 (en) 2000-09-25 2001-07-31 International Business Machines Corporation Variable stoichiometry silicon nitride barrier films for tunable etch selectivity and enhanced hyrogen permeability
US20040175934A1 (en) * 2003-03-04 2004-09-09 International Business Machines Corporation Method for improving etch selectivity effects in dual damascene processing
US20060045986A1 (en) 2004-08-30 2006-03-02 Hochberg Arthur K Silicon nitride from aminosilane using PECVD
US9293379B2 (en) * 2009-09-03 2016-03-22 Raytheon Company Semiconductor structure with layers having different hydrogen contents

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4299862A (en) * 1979-11-28 1981-11-10 General Motors Corporation Etching windows in thick dielectric coatings overlying semiconductor device surfaces
US4447824A (en) * 1980-08-18 1984-05-08 International Business Machines Corporation Planar multi-level metal process with built-in etch stop
US4367119A (en) * 1980-08-18 1983-01-04 International Business Machines Corporation Planar multi-level metal process with built-in etch stop
JPS6010644A (ja) * 1983-06-30 1985-01-19 Toshiba Corp 半導体装置の製造方法
US4656729A (en) * 1985-03-25 1987-04-14 International Business Machines Corp. Dual electron injection structure and process with self-limiting oxidation barrier
JPS62205645A (ja) * 1986-03-06 1987-09-10 Fujitsu Ltd 半導体装置の製造方法
EP0265584A3 (en) * 1986-10-30 1989-12-06 International Business Machines Corporation Method and materials for etching silicon dioxide using silicon nitride or silicon rich dioxide as an etch barrier
US5443998A (en) * 1989-08-01 1995-08-22 Cypress Semiconductor Corp. Method of forming a chlorinated silicon nitride barrier layer
US5468987A (en) * 1991-03-06 1995-11-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
EP0523856A3 (en) * 1991-06-28 1993-03-17 Sgs-Thomson Microelectronics, Inc. Method of via formation for multilevel interconnect integrated circuits
US5252515A (en) * 1991-08-12 1993-10-12 Taiwan Semiconductor Manufacturing Company Method for field inversion free multiple layer metallurgy VLSI processing
US5252516A (en) * 1992-02-20 1993-10-12 International Business Machines Corporation Method for producing interlevel stud vias
US5324690A (en) * 1993-02-01 1994-06-28 Motorola Inc. Semiconductor device having a ternary boron nitride film and a method for forming the same

Also Published As

Publication number Publication date
JPH08306658A (ja) 1996-11-22
JP3193632B2 (ja) 2001-07-30
EP0742584A2 (en) 1996-11-13
KR960042996A (ko) 1996-12-21
KR100209041B1 (ko) 1999-07-15
US5622596A (en) 1997-04-22
EP0742584A3 (en) 1997-10-08

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