TW439117B - A method for measuring thickness of layers in chemical mechanic polishing process - Google Patents

A method for measuring thickness of layers in chemical mechanic polishing process Download PDF

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TW439117B
TW439117B TW88123152A TW88123152A TW439117B TW 439117 B TW439117 B TW 439117B TW 88123152 A TW88123152 A TW 88123152A TW 88123152 A TW88123152 A TW 88123152A TW 439117 B TW439117 B TW 439117B
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Taiwan
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layer
forming
patent application
silicon
silicon oxide
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TW88123152A
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Chinese (zh)
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Hung-Dian You
Tzu-Shiung Feng
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Applied Materials Inc
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Abstract

A method to reduce the footing of the photoresist layer above the semiconductor substrate is disclosed. First, forms the antireflective layer containing silicon, oxygen and nitrogen on the semiconductor substrate, and in situ forms the hardmask containing silicon and oxygen on the antireflective layer. Then forms the photoresist layer on the hardmask, and defines patterns on the photoresist layer, wherein the hardmask has low concentration of nitrogen which can reduce the footing of the photoresist layer.

Description

4391 1 7 A7 B7 經濟部智慧財產局員工消費合作社印" 五、發明説明() 相關申請案: 本發明係有關於民國8 6年1 〇月2曰申請之專利案第 8 6 1 1 4 2 6 6號名稱“改良基材微影製程之锖確性的方法與装 置”。 發明領域:_ 本發明與一種半導體製程中之微影製程(lit ho grapgy) 有關,特别是一種可降低光阻層足跡效應(footing)以精確的 定義圖案於金屬層上之方法。 發明背景: 隨著半導體工業持續的進展,在超大型積體電路 (ULSI)的開發與設計肀,爲了符合高密度積體電路之設計趨 勢,各式元件之尺寸皆降至次微米以下。並且由於元件不斷 的縮小,也導致在進行相關半導體製程時,往往遭遇了前所 未有之難題,且製程之複雜程度亦不斷提高。其中,對廣泛 應用於半導體製程中之微影製程(photolithography)而言,如 何在紋路尺寸不斷縮小的情況下,定義出具高猜確度的結 構,成島當前極重要之課題。 (請先閲**背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標隼(CNS > A4規格(210X297公釐) 4 3 〇 …7 A7 W___B7 五、發明説明() 一般而言,在進行微影製程時’往往先在半導體底材 的表面上形成一層感光材料(photo-sensitive material),如光 阻(photoresist)。然後,藉著使用來自光源(丨ight source)的 .光束,在經過具有各式圖案的光罩後,照射在此層光阻上。 其中,透過光罩的光束,可將與光罩相同的圖案,轉移至光 阻層上,並使光阻層產生選擇性的感光。如此,可將光罩上 的圖案,完整的轉移並傳遞至光阻層上,而造成曝光 (exposure)。値得注意的是,用來進行曝光程序的光阻,可 分爲正光阻(positive)與負光阻(negative)。其中在絰過顯影 (development)後,光阻上所形成之圊案與光罩上相同時,便 是正光阻;相對地,當光阻上所形成之固案與先罩上圖案, 具有互補(complementary)關係時,所使用之光阻便爲負光 阻。 請參照第_圖,該圖所顯示爲使用微影製程,定義圖 案於半導體底材上之步驟。其中,首先沉積有待製作圖案之 第一層4於半導體底材2上。接著,形成光阻層6於該第一 層4上,用以進行後續轉移圖案之製程》藉著上述定義圖案 於光阻層6上之步驟,可使用光源經由光罩’對光阻6進行 曝光程序,並在完成顯影製程後,可在光阻層6上得到所需 之囷案。仍參照第一圖,其中藉著曝光與顯影等步驟,可以 形成所需之開σ圖案8於光阻層6上。如此一來,再利用殘 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) (請先閱伟.\面之^意事項再填寫本頁) 訂 線1 經濟部智慧財產局員工消费合作社印製 H,,"71, a7 ____B7_ 五、發明説明() 餘光阻層6作爲蝕刻罩冪,可對其下之第一層4推 疋仃蝕刻程 序,而定義出開口圖案於第一層4上。 然而,値得注意的是,在對光阻層6進行嗾 .叱興顯影 製程時’所定義的開口圖案8其側壁鄰接第一層 ^之區域 上,往往會產生如第一圖中所示之足跡(footing)殘如物7 一般而言,此種足跡殘留物7乃曝光不足的光阻付料,在進 行顯影程序中殘留於側壁上所造成。其中,所形成之足跡殘 留7,往往是與第一層4之氮含量有關。當第一屬4表面具 有過多的胺基(NH4 )時,由於其具有驗性’是以可與光阻層^ 6底部之材料(微酸性),甩成鍵結而導致光阻材料之光感度 下降。由此,將促使光阻層6底部無法完全顯影,而產生如 團中所示之足跡殘留物7。儘管’藉著延長曝光時間,可以 使位於開口圖案中央之光阻層6,完全曝光而有效的加以移 除》然而對於位於開口圖案兩侧之光阻層6而言,僅僅藉著 延長曝光時間,並無法有效的解決由於光阻材料光感度降低 所導致爆光不足的問題°其中,由於經由光罩照射於光阻層 6上之光束,會產生繞射現像,使得照射於開口囷案中央之 光線強度較強;同理,照射於開口囷案兩側之光線強度則較 弱。是以即使延長了照射的時間,位於開口圏案兩側之光阻 廣6其曝光效果依舊不佳,而產生足路效應7。如此一來, 將造成後續定義圖案於第一層4之蝕刻程序中,光阻層6 本紙張尺度適用中國國家標準(CNS ) A4^格(21〇Χ297公釐) (請先閲铲背面.V·.注意事項再填寫本頁) 訂 邊1' 經濟部智慧財產局員工消費合作社印製 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明( 所定義的開口圖案8其線寬’偏離了預期的尺寸。 然而’値得注意的是’《了有效的提昇微影製程中, 光阻層之解析度,往往會在光祖層之下方,形成一抗反射廣 (Anti-Refiective layer ARf、。工:★ ^ ^ y ; 而在目前的半導體製程中, 使用作爲抗反射層之材料,往往爲具有氛肩子之氮氧化石夕 3。其中,對氮氧化矽層而言,由於其處理程序很容易與其 它半導體底材之處理過程整合,且其材料之光學品質及相關 製程之參數業以徹底了解,是以在用來作爲抗反射層材料 時,可有效的加以控制與調整。如此一來,卻也導致在進行 疋義圖案於光阻層上足製程時,由於氮氧化矽層中之氮原子 與光阻材料反應’而產生不期待之足跡效應。 另外,對微影製程而言,如何有效的避免在進行蝕刻 程序中,產生不期待的蝕穿現像,亦爲一重要課題。請參照 第二圖’該圖所顯示爲在一半導體底材上,用以定義圖案之 蝕刻程序。其中,在此半導體底材12上具有欲定義圖案之 第一層〗4。並且,一用以減少後續光阻層產生反射、駐玫 與其它光學現象之抗反射層16,形成於第一層14上。然後, 如同前述,形成光阻層18於抗反射層】6表面上,並對光阻 層I8進行定義開口圖案之程序。在轉移開口圖案至光[t且層 1 8上後,利用此光阻層1 8作爲蝕刻罩冪,可對位於其下之 表紙張尺度適用中國國家標率(CNS ) A4規格(210 X 297公釐> --Γ— - !! - - - - - ml DV. I n - ----] I -- I n Jl I i- , . (請先閱^背面皂注意事項耳填窝本頁」 A7 43911 7 B7 五'發明説明() (請先閱^背面之注意事項再填寫本頁) 抗反射層16及第一層14進行定義圖案之触刻製程α並且, 形成如圖中所示之開口圖索2 0。但是,値得注意的是,當 在進行蝕刻抗反射層1 6與第一層1 4時,如果所使用之蝕刻 劑對光阻層 1 8之選擇性差距不大,往往會造成光阻層 18 在蝕刻程序中,亦遭受嚴重的蝕刻沉狀。甚至,會造成光阻 層18被独穿而產生缺口 22。如此,位於其下之抗反射層16 與第一層14亦會遭受侵蝕,而導致第一層14的表面形狀產 生非期望性的改變,甚至造成後續所形成之裝置無法運作。 請參照第三圖,該圖所顯示爲解決上述問題之方法。 其中,首先在半導體底材32上形成欲定義圖案之第一層 34。接著,依序形成抗反射層36、硬式罩冪38於第一層34 上,並形成光阻層40於硬式罩冪38表面上。如此,在進行 定義圖案於第一層34上之蝕刻程序時,即便會對光阻層4〇 造成優蝕,而導致餘穿缺口 44發生。然而,由於有硬式罩 冪3 8之保護,是以可有效防止其下之第一層3 4受到侵蝕, 從而提高整個製程的良率° 發明目的及概述: 經濟部智慧財產局員工消費合作社印製 本發明之目的爲一種定義圖案於金屬層上之微影製 程方法。 本紙張尺度適用中國國家標準(CNS ) Α4規格(210 X 297公釐) 4391 1 i A7 B7 五、發明説明() (請先閲^,。背面之注意事項再填寫本頁) 本發明之再一目的爲一種降低位於半導體底材上方 之光阻層其足跡效應(footing)之方法。 本發明之又一目的爲一種在半導體底材上情確定義 圖案於金屬層上之方法,其中同步形成氮氧化矽層與氧化矽 層,以有效降低製程成本、縮減製程時間、且降低製程中可 能之污染。 本發明提供了一種在半導體底材上精確定義圖案於 金屬層之方法。首先,形成金屬層於該半導體底材上。然後, 形成氮氧化石夕層於金屬層上以作爲抗反射層,且同步(in-situ)形成氧化碎層於抗反射層上以作爲硬式罩冪 (hardmask)。接著,形成光阻層於氧化咬層之上,_以便定義 圖案於光阻層上,其中氧化矽層可用以降低光阻層之足跡效 應。接著,使用光阻層作爲罩冪,對氧化矽層、氬氧化矽層 與金屬層進行蝕刻程序,以轉移開口圖案至氡化矽層、氮氧 化矽層與金屬層上。 經濟部智慧財產局員工消費合作社印製 圖式簡單説明: 藉由以下詳細之描述結合所附圖示,將可輊易的了解 上述内容及此項發明之諸多優點,其中: 本紙張尺度適用中國國家標率(CNS ) A4規格(210 X 297公釐) 五、發明説明() (請先閲#背面之注意事項再填寫本頁) 第一圖爲半導體晶片之截面圖,顯示根據傳統技術定 義開口圖案於光阻層上時,造成之足跡效應; 弟二圖爲半導體晶片之截面圖》顯示根據傳統技術定 義圖案於半導體底材上時,所產生之之蝕穿效應; 第三圖爲半導體晶片之截面圖,顯示根據傳統技術, 形成硬式罩冪於光阻層與抗反射層間,以防止光阻層被蝕穿 時,位於硬式罩冪其下之各層亦遭受侵蝕: 第四圖爲半導體晶片之截面圖,顯示根據本發明第一 實施例,同步形成抗反射層與硬式罩冪層之步騍; 第五圖爲半導體晶片之截面圖,顯示根據本發明第一 實施例,定義圖案於半導體底材上之步驟; 第六圖爲半導體晶片之截面圖,顯示根據本發明第二 實施例,同步形成硬式罩冪層與抗反射層之步騍;及 第七圖爲半導體晶片之截面圖,顯示根據本發明第二 實施例,定義圖案於半導體底材上之步骤 發明詳細説明: 經濟部智慧財產局員工消费合作钍印契 本發明所揭示爲一種定義圖索於金屬層上之方法。其 中使用此方法,可有效降低光阻層足跡效應,且有效避免由 於光阻層穿透所造成之缺口影晌其下金屬層°並且,在本發 明所提供之方法中,藉著同步(in-situ)形成氮氧化妙層與氧 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 A7 _______B7_ 五、發明説明() 化碎層’可大幅縮減進行沉積程序所需之時間,並減少產生 ’亏染之機會。有關本發明之詳細説明如下所述。 首先’請參照第四圖,在一較佳之具體實施例中,提 供一具<100>晶向之單晶矽底材102。_般而言,其它種類 之半導體材科,諸如坤化鎵(gallium arsenide)、錄(germanium) 或疋位於絶緣屠上之妙底材(silic〇ri 〇n insulator, SOI)亦可 作爲半導體底材使用。另外,由於半導體底材表面的特性對 衣發明而言’並不會造成特别的影晌,是以其晶向亦可選擇 < 1 1 0>或 < 1 1 1 > 〇 接著’形成金屬層104於半導體底材102上。一般而 言’由於铭金屬之電阻率較低,且對其它氧化層之附著情形 良好’是以往往用以作爲金屬層1〇4之材料。其中可藉由所 熟知之技術,如物理氣相沈積法(pvD)、濺鍍等類似製程在 半導體底材102上沈積而得,其它可供選擇作爲金屬層ι〇4 之材料’尚包含鋁、鈦、鎢、鋼、金、鉑或合金等等。此外, 導電材料如經掺雜之多晶矽、矽化鎢(Tungsten Silicide)等 等材料’亦可用以取代上述金屬層丨〇4。値得注意的是在形 成上述金屬;f 104之前’半導體底材1〇2上已先形成所需之各 種功能層,與各式各樣所需之元件。 本紙張磁用中國國家揉準 ---------I------訂---^----^ί (請先聞If背面之注意事項再填寫本頁)4391 1 7 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs " V. Description of the invention () Related applications: The present invention relates to the patent filed in the Republic of China on October 10, 1996. No. 8 6 1 1 4 The name 2 6 6 "method and device for improving the accuracy of the lithography process of the substrate". Field of the Invention: The present invention relates to a litho grapgy process in a semiconductor process, and particularly to a method that can reduce the footing effect of a photoresist layer to precisely define a pattern on a metal layer. Background of the Invention: With the continuous progress of the semiconductor industry, in the development and design of ultra-large integrated circuits (ULSI), in order to meet the design trend of high-density integrated circuits, the size of various components has been reduced to sub-micron. In addition, due to the continuous shrinking of components, the related semiconductor process often encounters unprecedented difficulties, and the complexity of the process is also increasing. Among them, for photolithography, which is widely used in semiconductor processes, how to define a structure with a high degree of accuracy while the texture size is shrinking has become an extremely important issue at present. (Please read the notes on the back of ** before filling this page) This paper size applies to Chinese national standard (CNS > A4 size (210X297 mm) 4 3 〇… 7 A7 W___B7 V. Description of invention () Generally speaking During the lithography process, a layer of photo-sensitive material, such as photoresist, is often formed on the surface of the semiconductor substrate. Then, by using a light source from a light source After passing through a photomask with various patterns, it is irradiated on this layer of photoresist. Among them, the light beam transmitted through the photomask can transfer the same pattern as the photomask to the photoresist layer and cause the photoresist layer to be generated. Selective photosensitivity. In this way, the pattern on the photomask can be completely transferred and transferred to the photoresist layer, resulting in exposure. It should be noted that the photoresist used for the exposure process can be divided Positive photoresistance (negative) and negative photoresistance (negative). After development, the photoresist formed on the photoresist is the same as that on the photomask. In contrast, when the photoresist Solid case When there is a complementary relationship, the photoresist used is a negative photoresist. Please refer to Figure _, which shows the steps of defining a pattern on a semiconductor substrate using a lithographic process. First, A first layer 4 to be patterned is deposited on the semiconductor substrate 2. Then, a photoresist layer 6 is formed on the first layer 4 for the subsequent process of transferring the pattern. "The pattern is defined on the photoresist layer 6 as described above. In the above steps, the light source 6 can be exposed to the photoresist 6 through the photomask, and after the development process is completed, the desired solution can be obtained on the photoresist layer 6. Still referring to the first figure, which is exposed by exposure Steps such as development and development can form the required open sigma pattern 8 on the photoresist layer 6. In this way, the remaining paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) (please read Wei . \ 面 的 ^ 意 事 再到 此 表。 Please fill in this page) Line 1 Printed by H ,, " 71, a7 ____B7_ of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the invention () The remaining photoresist layer 6 is used as an etching mask. Can push the first layer 4 below it The opening pattern is defined on the first layer 4. However, it should be noted that, when the photoresist layer 6 is subjected to the 嗾. Development process, the sidewall of the opening pattern 8 defined by the first layer is adjacent to the first layer. In the area, footing residues 7 as shown in the first figure are often generated. Generally, such footprint residues 7 are underexposed photoresist materials and remain in the development process. Caused by the side wall. Among them, the remaining 7 of the footprint formed is often related to the nitrogen content of the first layer 4. When the surface of the first genus 4 has too many amine groups (NH4), it is empirical. Can be bonded to the material at the bottom of the photoresist layer ^ 6 (slightly acidic), which will cause the photosensitivity of the photoresist to decrease due to bonding. As a result, the bottom of the photoresist layer 6 cannot be fully developed, and a footprint residue 7 as shown in the figure is generated. Although 'the photoresist layer 6 located in the center of the opening pattern can be completely exposed and effectively removed by extending the exposure time', for the photoresist layer 6 located on both sides of the opening pattern, only by extending the exposure time And cannot effectively solve the problem of insufficient light exposure caused by the reduced photosensitivity of the photoresist material. Among them, the light beam irradiated on the photoresist layer 6 through the photomask will generate a diffraction image, so that it is irradiated to the center of the opening case. The light intensity is strong; similarly, the light intensity on both sides of the opening case is weak. Therefore, even if the exposure time is prolonged, the exposure effect of the photoresistors located on both sides of the opening case is still not good, and a footpath effect is generated. As a result, the subsequent definition of the pattern in the etching process of the first layer 4, the photoresist layer 6 paper size applies the Chinese National Standard (CNS) A4 ^ grid (21〇 × 297 mm) (please read the back of the shovel first. V ·. Note, please fill in this page again.) Margin 1 'Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 Printed by the Employees’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 'Deviated from the expected size. However, what should be noted is that "In the effective improvement of the lithography process, the resolution of the photoresist layer is often below the light ancestor layer, forming an anti-refiective layer ARf, workmanship: ★ ^ ^ y; In the current semiconductor process, the material used as the anti-reflection layer is often oxynitride with a shoulder. 3. Among them, for the silicon oxynitride layer, Because its processing procedure is easy to integrate with other semiconductor substrate processing processes, and its optical quality and related process parameters are thoroughly understood, it can be effectively controlled when used as an anti-reflection layer material. In this way, it also leads to an unexpected footprint effect due to the reaction of nitrogen atoms in the silicon oxynitride layer with the photoresist material during the process of making a sense pattern on the photoresist layer. For the lithography process, how to effectively avoid the occurrence of undesired etch-through images during the etching process is also an important issue. Please refer to the second figure, which is shown on a semiconductor substrate for An etching process for defining a pattern. Among them, there is a first layer of the pattern to be defined on the semiconductor substrate 12. And, an anti-reflection layer 16 is used to reduce the subsequent photoresist layer from reflection, immersion and other optical phenomena. Is formed on the first layer 14. Then, as before, a photoresist layer 18 is formed on the surface of the antireflection layer] 6, and a procedure for defining an opening pattern is performed on the photoresist layer I8. The transfer opening pattern is transferred to light [t and After layer 18 is used, the photoresist layer 18 is used as an etching mask power, and the Chinese paper standard (CNS) A4 specification (210 X 297 mm >) can be applied to the paper size below it. !!-----ml DV. I n-----] I- I n Jl I i-,. (Please read ^ Back Soap Precautions Ear Filler Page ”A7 43911 7 B7 Five 'Invention Description () (Please read ^ Back Precautions before filling this page) Anti-reflective layer 16 and the first layer 14 perform a touch-etching process α defining a pattern and form an opening pattern 20 as shown in the figure. However, it should be noted that when the anti-reflection layer 16 and the first layer are being etched, At 14 o'clock, if the selectivity of the used etchant to the photoresist layer 18 is not large, it will often cause the photoresist layer 18 to suffer severe etching sinking during the etching process. It may even cause the photoresist layer. 18 was worn alone to create a gap 22. In this way, the anti-reflection layer 16 and the first layer 14 underneath will also be eroded, resulting in an undesired change in the surface shape of the first layer 14 and even causing the subsequent formed devices to fail to operate. Please refer to the third figure, which shows a solution to the above problems. Among them, a first layer 34 having a pattern to be defined is first formed on the semiconductor substrate 32. Next, an anti-reflection layer 36 and a hard mask 38 are sequentially formed on the first layer 34, and a photoresist layer 40 is formed on the surface of the hard mask 38. In this way, when the etching process of defining the pattern on the first layer 34 is performed, even if the photoresist layer 40 is caused to be etched, a residual punch-through gap 44 occurs. However, due to the protection of the hard cover 38, it can effectively prevent the first layer 3 4 underneath from being eroded, thereby improving the yield of the entire process. Purpose and Summary of the Invention: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs An object of the present invention is to provide a lithography process for defining a pattern on a metal layer. This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 4391 1 i A7 B7 V. Description of the invention () (Please read ^ ,. Note on the back before filling this page) One object is to reduce the footprint of a photoresist layer over a semiconductor substrate. Yet another object of the present invention is a method for defining a pattern on a metal layer on a semiconductor substrate, in which a silicon oxynitride layer and a silicon oxide layer are simultaneously formed, so as to effectively reduce the process cost, the process time, and the process time. Possible pollution. The present invention provides a method for precisely defining a pattern on a metal substrate on a semiconductor substrate. First, a metal layer is formed on the semiconductor substrate. Then, an oxynitride layer is formed on the metal layer as an anti-reflection layer, and an oxide fragment layer is formed in-situ on the anti-reflection layer as a hard mask. Next, a photoresist layer is formed on the oxide bite layer to define a pattern on the photoresist layer. The silicon oxide layer can be used to reduce the footprint effect of the photoresist layer. Next, using the photoresist layer as a mask, an etching process is performed on the silicon oxide layer, the argon silicon oxide layer, and the metal layer to transfer the opening pattern to the silicon oxide layer, the silicon nitride oxide layer, and the metal layer. A simple illustration of the printed drawings of the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs: With the following detailed description combined with the attached drawings, the above content and many advantages of this invention can be easily understood, of which: This paper scale is applicable to China National Standards (CNS) A4 specification (210 X 297 mm) V. Description of the invention () (Please read the note on the back of # before filling out this page) The first figure is a cross-sectional view of a semiconductor wafer, showing the definition according to traditional technology Footprint effect caused by the opening pattern on the photoresist layer; The second figure is a cross-sectional view of a semiconductor wafer "shows the erosion effect generated when a pattern is defined on a semiconductor substrate according to traditional technology; the third image is a semiconductor The cross-sectional view of the chip shows that according to the conventional technology, a hard mask is formed between the photoresist layer and the anti-reflection layer to prevent the layers under the hard mask from being eroded when the photoresist layer is eroded: The fourth picture is a semiconductor A cross-sectional view of a wafer shows the steps of forming an anti-reflection layer and a hard mask layer simultaneously according to the first embodiment of the present invention; the fifth view is a cross-section of a semiconductor wafer , Which shows the step of defining a pattern on a semiconductor substrate according to the first embodiment of the present invention; the sixth diagram is a cross-sectional view of a semiconductor wafer, which shows that a hard mask layer and an anti-reflection layer are simultaneously formed according to the second embodiment of the present invention; Step 7; and Figure 7 is a cross-sectional view of a semiconductor wafer, showing the steps for defining a pattern on a semiconductor substrate according to the second embodiment of the present invention. Detailed description of the invention Revealed as a way to define maps on metal layers. Wherein using this method, the footprint effect of the photoresist layer can be effectively reduced, and the notch caused by the penetration of the photoresist layer can affect the underlying metal layer. Moreover, in the method provided by the present invention, by synchronizing (in -situ) Formation of Nitrogen Oxidation Layer and Oxygen This paper scale is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) Printed by A7 of Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs _______B7_ V. Description of the Invention 'Can significantly reduce the time required to perform the deposition process and reduce the chance of' defective '. A detailed description of the present invention is as follows. First, please refer to the fourth figure. In a preferred embodiment, a single crystal silicon substrate 102 having a < 100 > crystal orientation is provided. _ In general, other types of semiconductor materials, such as gallium arsenide, germanium, or silicon 〇 On insulator (SOI) can also be used as a semiconductor substrate材 用。 Wood use. In addition, due to the characteristics of the surface of the semiconductor substrate, the invention does not cause any special effects, and the crystal orientation can also be selected as < 1 1 0 > or < 1 1 1 > 〇 and then formed. The metal layer 104 is on the semiconductor substrate 102. In general, 'the metal resistivity is low and the adhesion to other oxide layers is good' is a material often used as the metal layer 104. Among them, it can be deposited on the semiconductor substrate 102 by well-known techniques such as physical vapor deposition (pvD), sputtering and the like. Other materials that can be selected as the metal layer ι04 include aluminum. , Titanium, tungsten, steel, gold, platinum or alloys, etc. In addition, conductive materials such as doped polycrystalline silicon, tungsten silicide (Tungsten Silicide), etc. can also be used to replace the above metal layer. It should be noted that before the formation of the above-mentioned metals; before f 104 ', various required functional layers and various required elements have been formed on the semiconductor substrate 102. This paper is magnetically calibrated by the Chinese state --------- I ------ Order --- ^ ---- ^ ί (Please read the precautions on the back of If before filling out this page)

經濟部智慧財凌局Μ工消費合作社印製 五、發明説明() 接著,可選擇性(〇Ptional)形成氮化鈇(TiN)層106於 金屬層1 04上,以作爲阻障層(barrier layer)。其中,此氮 化鈦層1 06除了可用以降低金屬層1 〇4與後續形成於其上 备層間產生尖峰現象(sPiking effect)外,亦可提昇其間之附 著能力。其中,在一較佳實施例中,氮化鈦層106具有厚度 約2 0 0至 5 0 0埃°在—較佳實施例中,可使用氮化反應 (Nitridation)製程來形成所需之氮化鈦層106。首先進行濺 鍍程序,以沉積一鈦層於金屬層丨〇4上表面,再於1^2或NH3 的環境中,經由高溫處理而形成所需之氮化鈦層此外, 也可利用反應性濺鍍程序來形成氮化鈦層1 〇 6。藉著利用電 漿離子轟擊鈦金屬,且通入氬氣與氮氣,以便經轟擊所漱出 的鈦原子,可與經由解離反應(Dissociati〇n Reacti〇n)所形成 的氮原子,反應並生成氮化鈦而沉積於金屬層1〇4表面。 接著,再形成氮氧化矽層於氮化鈦層106上以作 爲抗反射層(Anti-Reflection layer; ARC),且同步(in-situ) 形成氧化矽層1 1 〇於氮氧化矽層I 〇 8上’以作爲硬式罩幂 (hardmask) »其中同步形成氮氧化矽層1〇8與氧化H 1 1〇 之步驟,是使用電漿增強化學氣相沉積法(Plasma enhanced chemical vapor deposition; PECVD)所形成’且所使用之機 台爲應用材料股份有限公司所製造之p·5000 CENTURA型 或Producer機台。並且上述氮氧化梦屠與氧化梦層110 (請先聞沐背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國囤家標隼(CNS ) Α4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 4 a 31 17' * A7 ______B7_____ 五、發明説明() 是在同一個反應室中所形成,其中所使用之反應室爲AMAT DxZ、DLH或Twin型反應室》 在一較佳實施例中,上述氮氧化矽層1 〇 8具有折射係 數(η)約1.9至2.9,且其反射係數(k)約在0.5至0.9。並且 具有厚度約爲200至1500埃。至於上述氧化矽層11〇之厚 度則大約爲50至8000埃。在形成氮氧化矽層1〇8時,通入 反應室中之反應氣體包括了約40至60 seem之SiH4、約70 至110 seem之N20與約1600至2600 seem之He,並且是 在溫度約350至45〇1〇,壓力约5至7torr的環境中進行。 至於其中所施加之電壓功率則約爲70至130Watt。此外, 當形成氡化矽層110時,通入反應室中之反應氣體包含了 90 至 130 seem 之 SiH4 與 1 800 至 2200 seem 之 N20。其中 反應室之溫度大約控制於350至450 eC,而壓力約1.8至2.6 torr。且其中所施加之電壓功率約爲200至280 Watt。 在同步形成上述氮氧化矽層108與氧化矽層110後, 接著形成光阻層1 12於氧化矽層1 1 0之上。在一較佳實施例 中,所形成之光阻層112約具有4000至8000埃的厚度。 然後,請參照第五圉,使用微影製程技術,定義圖隶 於金屬層104上。其中,首先使用傳統技術中之微影製程, 本紙浪尺度通用中國國家標準(CNS > A4規格(210X297公釐) ---------V 乂------訂------線1 (請先閲^^面之注意事項再填寫本頁) 經濟部智慧財產局工消費合作社印製 3 91 1 7ii A7 — _B7五、發明説明() 定義諸如開σ圖案等所需之圖案於光阻層112上。接著,再 使用光阻層1 1 2作爲軍冪,對氧化矽層1 10、氮氧化矽層 1 08、氮化鈦層1 〇6與金屬層1 04進行蝕刻程序,以定義開 σ圖案115至氧化矽層11〇、氮氣化矽層108'氮化鈦層106 與金屬層104上。在一較佳實施例中,可使用反應離子蝕刻 程序用來蝕刻上述各層。其中氮氧化矽層108之蝕刻配方可 選擇CF4/H2、 CHF 3或CH3CHF2;至於蝕刻氧化層110之 蝕刻配方則可選擇 CC12F2、CHF3/CF4、CHF^O:、CH/HF^ CF4/〇2。另外,用來定義鋁金屬圉案之蝕刻劑,則可選擇 SiCl4、BC13、BBr3、CC14等氣體與Cl2加以混合。 値得注意的是,如同前述,由於作爲抗反射層使用之 氮氡化矽層108具有氮原子,是以若直接形成光阻層112 於此氬氧化矽層108表面時,將會造成氮原子與光阻層底部 材料發生反應,而使得光阻層112底部之光感度下降,並造 成後續定義圖時的曝光程序中,光阻層112之曝光不全,從 而造成足跡效應。因此,藉著在形成氮氧化矽層108時,同 步形成氧化矽層110於氮氧化矽層108上,除了可作爲硬式 罩冪層,以防止在定義圖案時,產生光阻層112茅透,而導 致良率下降外;更可使用氣化矽層110來避免氮氧化矽層 108直接與光阻層112接觸。是以此氧化矽層110可產生降 低光阻層發生足跡效應之效果。 ---------乂------,玎------^ 1 (請先saift背面之注意事項再填寫本頁) 本紙張尺度適用中园固家標率(CNS ) A4洗格(210X297公釐}Printed by the Intellectual Property Cooperative Bureau of the Ministry of Economic Affairs, M. Industrial Cooperatives. 5. Description of the invention () Next, a 鈇 Nitride (TiN) layer 106 may be selectively formed on the metal layer 104 as a barrier layer. layer). Among them, the titanium nitride layer 106 can not only reduce the spiking effect between the metal layer 104 and the subsequent formation layer thereon, but also improve the adhesion ability therebetween. Wherein, in a preferred embodiment, the titanium nitride layer 106 has a thickness of about 200 to 500 angstroms. In a preferred embodiment, a nitritization process can be used to form the required nitrogen.化 titanium layer 106. First, a sputtering process is performed to deposit a titanium layer on the upper surface of the metal layer. Then, in a 1 ^ 2 or NH3 environment, the required titanium nitride layer is formed by high temperature treatment. In addition, the reactivity can also be used. A sputtering process is performed to form a titanium nitride layer 106. By bombarding titanium metal with plasma ions, and passing in argon and nitrogen, the titanium atoms eluted by the bombardment can react with the nitrogen atoms formed by the dissociation reaction (Dissociatión Reactio). Titanium nitride is deposited on the surface of the metal layer 104. Next, a silicon oxynitride layer is formed on the titanium nitride layer 106 as an anti-reflection layer (ARC), and a silicon oxide layer 1 1 0 is formed in-situ simultaneously with the silicon oxynitride layer I 〇 8 is used as a hardmask »The step of simultaneously forming the silicon oxynitride layer 108 and oxidizing H 1 10 is performed using plasma enhanced chemical vapor deposition (PECVD) The formed and used machines are p · 5000 CENTURA or Producer machines manufactured by Applied Materials Co., Ltd. And the above mentioned Nitrogen Oxidation Dream Slaughter and Oxidation Dream Layer 110 (please read the notes on the back of the Mu first and then fill out this page) The size of the paper is applicable to the Chinese storehouse standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperative of the Property Bureau 4 a 31 17 '* A7 ______B7_____ 5. The description of the invention () is formed in the same reaction chamber, where the reaction chamber used is AMAT DxZ, DLH or Twin type reaction chamber. In a preferred embodiment, the silicon oxynitride layer 108 has a refractive index (η) of about 1.9 to 2.9, and a reflection coefficient (k) of about 0.5 to 0.9. And has a thickness of about 200 to 1500 Angstroms. The thickness of the silicon oxide layer 110 is about 50 to 8000 angstroms. When the silicon oxynitride layer 10 is formed, the reaction gas introduced into the reaction chamber includes about 40 to 60 seem of SiH4, about 70 to 110 seem of N20, and about 1600 to 2600 seem of He, and the temperature is about It is carried out in an environment of 350 to 4501 and a pressure of about 5 to 7 torr. As for the voltage power applied, it is about 70 to 130 Watt. In addition, when the hafnium silicon layer 110 is formed, the reaction gas introduced into the reaction chamber includes 90 to 130 seem SiH4 and 1 800 to 2200 seem N20. The temperature of the reaction chamber is about 350 to 450 eC, and the pressure is about 1.8 to 2.6 torr. And the voltage power applied therein is about 200 to 280 Watt. After the silicon oxynitride layer 108 and the silicon oxide layer 110 are formed simultaneously, a photoresist layer 112 is formed on the silicon oxide layer 110. In a preferred embodiment, the photoresist layer 112 is formed to have a thickness of about 4000 to 8000 angstroms. Then, referring to the fifth step, the lithography process technology is used to define the map on the metal layer 104. Among them, the lithography process in the traditional technology is used first, and the paper scale is in accordance with the Chinese national standard (CNS > A4 specification (210X297 mm) --------- V 乂 ------ order- ---- Line 1 (please read the precautions on ^^ before filling out this page) Printed by the Industrial and Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 3 91 1 7ii A7 — _B7 V. Description of the invention () Definitions such as opening σ patterns, etc. The required pattern is on the photoresist layer 112. Next, the photoresist layer 1 12 is used as a military power, and the silicon oxide layer 1 10, the silicon oxynitride layer 1 08, the titanium nitride layer 1 06, and the metal layer 1 are used. 04 An etching process is performed to define the σ pattern 115 to the silicon oxide layer 110, the silicon nitride layer 108 ', the titanium nitride layer 106, and the metal layer 104. In a preferred embodiment, a reactive ion etching process can be used. To etch the above layers. CF4 / H2, CHF 3 or CH3CHF2 can be selected as the etching formula for the silicon oxynitride layer 108; CC12F2, CHF3 / CF4, CHF ^ O :, CH / HF can be selected as the etching formula for the oxide layer 110 ^ CF4 / 〇2. In addition, for the etchant used to define aluminum metal cases, SiCl4, BC13, BBr3, CC14 and other gases can be selected to be mixed with Cl2. It should be noted that, as mentioned above, because the silicon nitride layer 108 used as an anti-reflection layer has nitrogen atoms, if a photoresist layer 112 is directly formed on the surface of the silicon oxide layer 108, it will cause The nitrogen atom reacts with the material at the bottom of the photoresist layer, which decreases the photosensitivity at the bottom of the photoresist layer 112, and causes the exposure process of the photoresist layer 112 to be incomplete in the exposure procedure in the subsequent definition map, thereby causing a footprint effect. Therefore, by When the silicon oxynitride layer 108 is formed, the silicon oxide layer 110 is simultaneously formed on the silicon oxynitride layer 108, except that it can be used as a hard mask layer to prevent the photoresist layer 112 from being transparent during the definition of the pattern, resulting in a good quality. In addition, the silicon oxide layer 110 can be used to prevent the silicon oxynitride layer 108 from directly contacting the photoresist layer 112. This is because the silicon oxide layer 110 can reduce the footprint effect of the photoresist layer. ---- ----- 乂 ------, 玎 ------ ^ 1 (Please pay attention to the notes on the back of saift before filling out this page) This paper size is applicable to Zhongyuan Gujiao Standard (CNS) A4 washing Grid (210X297 mm)

A7 B7 經濟部智慧財產局員工消費合作·社印製 五、發明説明() 株另外’請參照第六圖’該圖所顯示爲根據本發所提供 第一實施例。其中’如同上述,首先形成金屬層2〇4於半 導體底材202上,且形成氬化欽層206於金屬層2〇4上,以 作爲阻障層使用。接著,依序形成氣化矽層208於氮化鈦層 2〇6上’且同步(in-situ)形成氮氧化矽層210於氧化矽層208 咕。其中如同前述,所形成之氧化矽層208可作爲後續蝕刻 1 fe中之硬式罩冪,而氮氧化矽層2丨〇則用來作爲提昇微影 解析庋之抗反射層a 然後,形成一蓋層212於氮氧化矽層210上。其中, 忒蓋層2 1 2具有含量極低之氮原子,以便降低由氬原子與後 續光阻層反應所產生之足跡效應.其中,在一較佳實施例 中,所使用之蓋層212可由氧化矽層所構成。接著,再形成 光阻層214於蓋層212之上。 在沉積蓋層2 1 2以覆蓋於氮氧化矽層2丨〇上後,可沉 積一光阻層214於蓋層2丨2上,以便進行後續定義圖案於金 屬層2 04上之程序。其中,如同前述,首先使用微影製程, 轉移圖案至光阻層2M上。再使用光阻層2丨4作爲蝕刻罩 冪,對其下各層進行蝕刻,直至曝露出半導體底材2〇2爲 止。如此,可形成如第七圖中所示之開口圖案215。其中, 本紙張尺度適用中國國家標準(CNS ) A4規格{ 210X297公釐) ---------A------訂------^ 1 (请先閲讚背面之注意事項再填寫本f ) A7 B7 439117 五、發明説明( 7一層_12具有極低之氬含量’是以可用以降低該先 產生足跡政應义機會。並且,由於在金屬層2 〇4與气 鈦層206上方,且有作& 乳处 、’作爲硬式罩冪工氧化矽層2〇8,是 便光阻層214發峰社_ Ρ 赞生姓穿現象,仍可有效的昉止其下 2〇4受到侵蝕。 屬層 本發明具有極多的優點。其中,藉著使用ρ_5〇〇〇 CENTURA或pr()dueer機台,來同步形成作爲抗反射廣使 ^,氧化矽層與作爲硬式罩冪之氧化矽層,可大幅降低形 氮氧化矽層與氧化矽層於半導體底材上之時間。並且,藉 同步形成氤氧化矽層與氧化矽層,可有效降低傳统製程中 在不同的機台上形成上述兩層時,容易產生之微粒污染 題〇 本發明雖以一較佳實例闌明如上,然其並非用以限定 本發明精神與發明實體,僅止於此一實施例爾。是以,在不 脱離本發明之锖神與範圍内所作之修改,均應包含在下述之 申請專利範圍内。 κ^— II--' f ^ I — II - II 訂 f請先閑讀背面·:/注意事項再填两本£ 經濟部智慧財產局員工消費合作社印製 ------ 本紙張尺度適用中國國家標準(CNS )八4规格(210 X 297公釐)A7 B7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Co-operation, Printed by the Society V. Invention Description () Strain In addition, please refer to the sixth figure. The figure shows the first embodiment provided by the Institute. Among them, as described above, a metal layer 204 is first formed on the semiconductor substrate 202, and an argon layer 206 is formed on the metal layer 204 to be used as a barrier layer. Next, a vaporized silicon layer 208 is sequentially formed on the titanium nitride layer 206 'and a silicon oxynitride layer 210 is formed on the silicon oxide layer 208 in-situ. As mentioned above, the formed silicon oxide layer 208 can be used as a hard mask in subsequent etching 1 fe, and the silicon oxynitride layer 2 丨 〇 is used as an anti-reflection layer a for improving lithographic analysis. Then, a cover is formed. The layer 212 is on the silicon oxynitride layer 210. Among them, the capping layer 2 1 2 has a very low content of nitrogen atoms, so as to reduce the footprint effect caused by the reaction of argon atoms with the subsequent photoresist layer. In a preferred embodiment, the capping layer 212 used may be Made of silicon oxide. Next, a photoresist layer 214 is formed on the capping layer 212. After the capping layer 2 12 is deposited to cover the silicon oxynitride layer 2 丨 0, a photoresist layer 214 can be deposited on the capping layer 2 丨 2, so as to carry out the subsequent procedure of defining a pattern on the metal layer 204. Among them, as mentioned above, the lithography process is first used to transfer the pattern to the photoresist layer 2M. The photoresist layer 2 and 4 are then used as etching masks, and the underlying layers are etched until the semiconductor substrate 200 is exposed. In this way, the opening pattern 215 shown in the seventh figure can be formed. Among them, this paper size is applicable to China National Standard (CNS) A4 specification {210X297 mm) --------- A ------ Order ------ ^ 1 (Please read the back of the praise first Note for refilling this f) A7 B7 439117 V. Invention description (7 layer_12 has extremely low argon content 'is used to reduce the chance of the first generation of footprints and political opportunities. Also, since the metal layer 2 〇4 Above the gas titanium layer 206, there is & milk, 'as a hard cover power silicon oxide layer 208, is a photoresist layer 214 hair peak company _ Zansheng surname wear phenomenon, still effective Stop the next 204 from being eroded. The metal layer of the present invention has many advantages. Among them, by using ρ_500 CENTURA or pr () dueer machine, synchronous formation of anti-reflective silicon oxide layer, silicon oxide layer And the silicon oxide layer as a hard mask, can greatly reduce the time of the silicon nitride oxide layer and the silicon oxide layer on the semiconductor substrate. Moreover, by simultaneously forming a hafnium silicon oxide layer and a silicon oxide layer, the traditional process can be effectively reduced. When the above two layers are formed on different machines, the problem of particulate pollution that is easy to occur. The present invention is based on a preferred example. Lang Ming is as above, but it is not used to limit the spirit and the invention of the invention, but only to this embodiment. Therefore, all modifications made without departing from the spirit and scope of the invention should be included in the following Within the scope of applying for patents. Κ ^ — II-- 'f ^ I — II-II Please read the back of the book f. --- This paper size applies to China National Standard (CNS) 8-4 (210 X 297 mm)

Claims (1)

8 00 8 8 AflcD 4 3 91 1 7 六、申請專利範国 〖·一種降低位於半導體底材上方之光阻層其足跡效 應(footing)之方法,該方法至少包含下列步骤: 形成包含矽、氧與氮之抗反射層於半導體底材上,且 同步(in-situ)形成包含矽與氡之硬式罩冪(hardmask)於該抗 反射層上; 形成光阻層於該硬式罩幂之上,且 定義圖案於該光阻層上,其中該硬式罩冪具有低含量 之氮’可用以降低該光阻層之足跡效應。 2. 如申請專利範園第1項之方法,其中上述形成該 抗反射層,且同步形成該硬式罩冪之步驟,是使用電漿增強 化學氣相沉積法(plasma enhanced chemical vapor deposition; PEC VD)所形成,且所使用之機台爲台灣應用材料股份有限 公司所製造之P-5000、CENTURA或Producer型機台。 經濟部智慧財產局員工消費合作社印製 3. 如申請專利範圍第1項之方法’其中上述形成該抗 反射層且同步形成該硬式罩冪之步驟’是在同—個反應室中 所進行,且所使用之該反應室爲AMAT DxZ、DLH或Twin 型反應室。 4. 如申請專利範圍第1項之方法’其中在形成上述之 本紙張尺渡逍用中國S家揉準(CNS > A4规格(2丨0X297公釐) 43 A8 BS C8 D8 六、申請專利範圍 抗反射層之前,更包括形成金屬層於該半導體底材上之步 驟。 5.如申請專利範固第4項之方法,其中上述之金屬 層爲銘金属。 6.如申請專利範固第4項之方法,其中在形成上述 之抗反射層前,更包括形成氮化鈦(TiN)層於該金屬層上, 以作爲阻障層,其中該氡化鈦層具有厚度約200至5 00埃。 7. 如申請專利範圍第1項之方法,其中上述之抗反 射層具有折射係數(η)約1.9至2.9,且反射係數(k)約〇. 5至 〇.9,至於該抗反射層之厚度則約爲200至1500埃11 8. 如申請專利範圍第1項之方法,其中上述之硬式 罩冪厚度約50至8〇〇〇埃。 經 部 智 慧 財 產 局 員 X 消 費 合 h 社 印 製 9 .如申請專利範圍第1項之方法’其中上述之抗反 射層爲氬氧化矽層,且形成該氮氧化破層之步驟_,所使用 之反應氣體包舍40至60 seem之SiH70至110 seem之 N20 與約 1600 至 2600 sccm 之 He ° 1 0.如申請專利範圍第9項之方法’其中形成上述之 16 本紙張尺度逍用中囷國家棣丰(CNS) A4规格(2丨0)<297公着) 六、申請專利範圍 (請先閲欢背面之注意事項再填寫本頁) 氮氧化矽層之步驟,是在溫度約3 5 〇至4 5 〇 *C,壓力約5至 7 torr的環境中進行’且其中所施加之電壓功率約爲7〇至 1 30 Watt。 t 1 .如申請專利範圍第9項之方法,其中與上述抗反 射層同步形成之硬式罩冪是由氧化矽層所構成,且形成該氧 化矽層之步骤中’所使用之反應氣體包含90至130 seem之 SiH4 與 1 800 至 2200 seem 之 N2〇。 12. 如申請專利範圍第Η項之方法,其中形成上述 氣化矽層之步驟,是在溫度約350至450,壓力約1.8至 2.6 torr的環境中進行’且其中所施加之電壓功率約爲200 至 280 Watt。 13. —種在半導體底材上精確定義圖案於金屬層之方 一 、 法,該方法至少包含下列步骤: 一 形成金屬層於該半導體底材上; 經濟部智慧財產局員工消黄合作社印製 形成氮氧化矽層於該金屬層上以作爲抗反射層,且同 步(in-situ)形成氧化矽層於該抗反射層上以作爲硬式罩冪 (hard mask); 形成光阻層於該氡化矽層之上; 定義該圏案於該光阻層上,其中該氧化矽層可用以降 本紙張尺度逍用中國a家橾丰(CNS ) A4规格(210 X 297公釐) 4 Α8 Β8 C8 D8 六、申請專利範圍 低該光阻層之足跡效應;且 使用該光阻層作爲罩冪’對該氧化矽層、該氮氧化矽 層與該金屬層進行蝕刻程序,以轉移該圖案至該氧化矽層、 該氮氧化矽層與該金屬層上。 I4.如申請專利範圍第13項之方法,其中上述形成 該氮氧化矽層,且同步形成該氧化矽層之步驟,是使用電漿 增強化學氣相沉積法(P丨asma enhanced chemical vapor deposition; PEC VD)所形成,且所使用之機台爲應用材料股 份有限公司(AM AT)所製造之p-5〇〇〇'CENTURA或Producer 型機台。 1 5 .如申請專利範圍第1 3項之方法’其中上述形成該 氮氡化矽層且同步形成該氧化矽層之步騍’是在同一個反應 室中所進行,且所使用之該反應室爲AMAT DxZ、DLH或 T w i η型反應室。 16. 如申請專利範園第13項之方法,其中上述之金 屬層爲銘金屬。 17. 如申請專利範圍第13項之方法,其中在形成上 述之氮氧化矽層前’更包括形成氮化鈦(:ΠΝ)層於該金展層 本紙張尺度適用t躅®家梯率< CNS ) Α4規格(210X297公釐) (請先閩清背.面之注意事項再填寫本頁) 訂 "! 經濟部智慧財產局員工消費合作社印製 ·.· ^ ? Irl. it r C8 __ D8六、申請專利範圍 經濟部智慧財羞局員工消費合作社印製 上’以作爲阻障層,其中該氮化鈦層具有厚度約200至500 埃。 如申請專利範圍第13項之方法,其中上述之氮 氡化较層具有折射係數(n)約1 9至2 9,且反射係數(k)約 〇.5至0.9’至於該氮氧化矽層之厚度則約爲2〇0至1 500埃。 19.如申請專利範園第13項之方法,其肀上述之氧 化發層厚度約5 0至8 0 0 〇埃。 2〇.如申請專利範圍第1 3項之方法,其中上述形成 該気氡化矽層之步驟中,所使用之反應氣體包含40至60 seem 之 SiH4、70 至 110 sccm 之 N20 與約 1600 至 2600 sccm 之He。 2 1.如申請專利範園第20項之方法,其中形成上述 氮氧化矽層之步騍,是在溫度約350至450 ·〇,壓力約5至 6 torr的環境中進行,且其中所施加之電壓功率約島70至 130 Watt。 22.如申請專利範圍第13項之方法,其中形成上述 氧化矽層之步驟中,所使用之反應氣體包舍90至130 seem 之 SiH4 與 1800 至 2200 seem 之 N20。 (請先閲會背面之注意事項再填寫本頁) 訂 %丨· 本紙張尺度通用申國阖家標準(CNS)A4規格(210X 297公釐) 々、申請專利範圍 ABCD 經濟部智蕙財產局員工消費合作社印製 2 3 .如申請專利範圍第2 2項之方法,其中形成上述氧 化矽層之步驟,是在溫度約3 5 0至4 5 0 °C,壓力約1 · 8至2.6 to rr的環境中達行,且其f所施加之電壓功率約爲200至 2 8 0 W att。 24. —種在半導體底材上情確定義圖案於金屬層之方 g,該方法至少包含下列步裸: 形成金屬層於該半導體底材上; 形成氧化矽層於該金屬層上,且同步(in_situ)形成氛 氧化矽層於該氧化矽層上以作爲抗反射層’其中該氧化5夕層 可在定義圖案於該金屬層上之步驟中,作爲硬式罩冪 (hardmask); 形成蓋層於該氮氧化矽層之上; 形成光阻層於該蓋層之上; 定義該圖案於該光阻層上’其中該蓋層可用以降低該 光阻層之足跡效應;且 使用該光阻層作爲罩冪’對該蓋層、該氮氧化發層、 該氧化矽層與該金屬層進行蝕刻程序,以轉移該圖案至該蓋 層、該氮氧化矽層、該氧化矽層與該金屬層上。 25.如申請專利範圍第24項之方法’其中上述形成 (請先閱1*·背面之注意事項再填寫本頁) 訂 本紙張尺度適用t國國家揉率(CNS ) A4现格(210X297公釐) A8 B8 C8 D8 夂、申請專利範圍 (請先閲贫^-面^注意事項再填寫本頁) 該氮氡化矽層,且同步形成該氧化矽層之步驟,是使用電漿 增強化學氣相沉積法(plasma enhanced chemical vapor deposition; PEC VD)所形成,且所使用之機台爲台灣應用材 料股份有限公司所製造之P-5000、CENTURA或Producer 型機台。 26.如申請專利範圍第24項之方法,其中上述形成該 氡化矽層且同步形成該氮氧化矽層之步驟,是在同一個反應 室中所進行,且所使用之該反應室爲AMAT DxZ、DLH或 Twin型反應室。 27.如申請專利範圍第24項之方法,其中上述之金 屬層爲鋁金屬。 2 8.如申請專利範圍第24項之方法,其中在形成上 述之氮氧化矽層前,更包括形成氮化鈦(TiN)層於該金屬層 上,以作爲阻障層,其中該氮化鈦層具有厚度約200至500 埃。 經濟部智慧財產局員工消費合作社印製 29.如申請專利範圍第24項之方法,其中上述之氮 氡化矽層具有折射係數(η)約1 9至2.9,農反射係數(k )約 0.5至0.9,至於該氮氧化矽層之厚度則約爲200至1500埃。 218 00 8 8 AflcD 4 3 91 1 7 VI. Patent application country 〖· A method for reducing the footing effect of a photoresist layer above a semiconductor substrate, the method includes at least the following steps: forming a layer containing silicon, oxygen An anti-reflection layer with nitrogen is formed on the semiconductor substrate, and a hard mask including silicon and hafnium is formed in-situ on the anti-reflection layer; a photoresist layer is formed on the hard mask; And a pattern is defined on the photoresist layer, wherein the hard mask has a low content of nitrogen 'to reduce the footprint effect of the photoresist layer. 2. For the method of applying for the first paragraph of the patent application park, wherein the step of forming the anti-reflection layer and simultaneously forming the hard mask is to use plasma enhanced chemical vapor deposition (PEC VD) ), And the machine used is a P-5000, CENTURA or Producer machine manufactured by Taiwan Applied Materials Co., Ltd. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 3. If the method of applying for the scope of patent No. 1 'wherein the above steps of forming the anti-reflection layer and forming the hard cover simultaneously' are performed in the same reaction chamber, The reaction chamber used is an AMAT DxZ, DLH or Twin type reaction chamber. 4. If the method of applying for the scope of the first item of the patent, 'wherein the above-mentioned paper ruler is used in China SCN (CNS > A4 specification (2 丨 0X297 mm) 43 A8 BS C8 D8 Before the range of the anti-reflection layer, a step of forming a metal layer on the semiconductor substrate is further included. 5. If the method of applying for patent No. 4 is applied, wherein the above-mentioned metal layer is Ming metal. The method of item 4, wherein before forming the above-mentioned anti-reflection layer, it further comprises forming a titanium nitride (TiN) layer on the metal layer as a barrier layer, wherein the titanium halide layer has a thickness of about 200 to 5000 7. The method according to item 1 of the patent application range, wherein the above-mentioned anti-reflection layer has a refractive index (η) of about 1.9 to 2.9, and a reflection coefficient (k) of about 0.5 to 0.9, as for the anti-reflection The thickness of the layer is about 200 to 1500 angstroms. 11 8. As described in the method of claim 1, the thickness of the hard cover is about 50 to 8000 angstroms. Member of the Intellectual Property Bureau of the Ministry of Economic Affairs and X Consumer Products System 9. If the method of applying for the scope of patent No. 1 The anti-reflection layer is a silicon argon oxide layer and the step of forming the oxynitride layer_, the reaction gas used includes 40 to 60 seem SiH70 to 110 seem N20 and about 1600 to 2600 sccm He ° 1 0 . If the method of applying for the 9th item of the scope of patents', where the above 16 paper sizes are used, the Chinese National Standard Bank (CNS) A4 specification (2 丨 0) < 297 is published) 6. The scope of patent application (please first Note on the back of Huan Huan, please fill in this page again) The steps of the silicon oxynitride layer are performed in an environment with a temperature of about 3 5 0 to 4 5 0 * C and a pressure of about 5 to 7 torr ', and the voltage and power applied therein About 70 to 1 30 Watt. t 1. The method according to item 9 of the scope of patent application, wherein the hard mask formed in synchronization with the anti-reflection layer is composed of a silicon oxide layer, and the reaction gas used in the step of forming the silicon oxide layer includes 90 SiH4 to 130 seem and N2〇 to 1 800 to 2200 seem. 12. The method according to item Η of the scope of patent application, wherein the step of forming the above-mentioned siliconized silicon layer is performed in an environment of a temperature of about 350 to 450 and a pressure of about 1.8 to 2.6 torr ', and the voltage and power applied therein are about 200 to 280 Watt. 13. —A method for precisely defining a pattern on a semiconductor substrate on a metal layer. The method includes at least the following steps:-forming a metal layer on the semiconductor substrate; printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs Forming a silicon oxynitride layer on the metal layer as an anti-reflection layer, and in-situ forming a silicon oxide layer on the anti-reflection layer as a hard mask; forming a photoresist layer on the 氡The silicon layer is defined on top of the photoresist layer. The silicon oxide layer can be used to reduce the paper size. It is easy to use a Chinese specification (CNS) A4 (210 X 297 mm) 4 Α8 Β8 C8 D8 6. The scope of the patent application is low for the footprint effect of the photoresist layer; and the photoresist layer is used as a mask to perform an etching process on the silicon oxide layer, the silicon oxynitride layer, and the metal layer to transfer the pattern to the A silicon oxide layer, the silicon oxynitride layer and the metal layer. I4. The method according to item 13 of the application, wherein the step of forming the silicon oxynitride layer and forming the silicon oxide layer simultaneously is using a plasma enhanced chemical vapor deposition method (P 丨 asma enhanced chemical vapor deposition); PEC VD), and the machine used is a p-5OO'CENTURA or Producer machine manufactured by Applied Materials Co., Ltd. (AM AT). 15. The method according to item 13 of the scope of the patent application, wherein the step of forming the silicon nitrided silicon layer and forming the silicon oxide layer simultaneously is performed in the same reaction chamber, and the reaction is used. The chamber is an AMAT DxZ, DLH or T wi η type reaction chamber. 16. For the method of applying for the patent item No. 13, wherein the above-mentioned metal layer is Ming metal. 17. The method according to item 13 of the scope of patent application, wherein before the formation of the silicon oxynitride layer described above, it further comprises forming a titanium nitride (: ΠΝ) layer on the gold-plated layer. ; CNS) Α4 specification (210X297 mm) (please fill in this page first before you clear the front page) Order "! Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs ··· ^? Irl. It r C8 __ D6. Patent application scope The Ministry of Economic Affairs ’s Smart Finance Bureau employees' consumer cooperatives printed on it as a barrier layer, where the titanium nitride layer has a thickness of about 200 to 500 Angstroms. For example, the method of claim 13 of the patent application, wherein the above-mentioned nitrogenated layer has a refractive index (n) of about 19 to 29, and a reflection coefficient (k) of about 0.5 to 0.9 '. As for the silicon oxynitride layer The thickness is about 2000 to 1,500 Angstroms. 19. The method according to item 13 of the patent application park, wherein the thickness of the above-mentioned oxidation layer is about 50 to 800 angstroms. 20. The method according to item 13 of the scope of patent application, wherein in the step of forming the siliconized silicon layer, the reaction gas used comprises 40 to 60 seem SiH4, 70 to 110 sccm N20, and about 1600 to 2600 sccm of He. 2 1. The method according to item 20 of the patent application park, wherein the step of forming the above silicon oxynitride layer is performed in an environment at a temperature of about 350 to 450 · 0, and a pressure of about 5 to 6 torr, and the applied The voltage power is about 70 to 130 Watt. 22. The method according to item 13 of the scope of patent application, wherein in the step of forming the above silicon oxide layer, the reaction gas used includes 90 to 130 seem of SiH4 and 1800 to 2200 seem of N20. (Please read the notes on the back of the meeting before filling out this page) Order% 丨 · This paper size is universally applicable to the National Standard for Family Standards (CNS) A4 (210X 297 mm) 々 Scope of patent application ABCD Intellectual Property Office of the Ministry of Economic Affairs Printed by the employee consumer cooperative 2 3. The method according to item 22 of the patent application range, wherein the step of forming the above-mentioned silicon oxide layer is at a temperature of about 3 50 to 4 50 ° C and a pressure of about 1.8 to 2.6 to In the environment of rr, the voltage and power applied by f is about 200 to 280 W att. 24. A method for defining a pattern on a semiconductor substrate on a square of a metal layer, the method includes at least the following steps: forming a metal layer on the semiconductor substrate; forming a silicon oxide layer on the metal layer, and synchronizing (In_situ) forming an atmospheric silicon oxide layer on the silicon oxide layer as an anti-reflection layer, wherein the oxide layer can be used as a hardmask in the step of defining a pattern on the metal layer; forming a cap layer On the silicon oxynitride layer; forming a photoresist layer on the cover layer; defining the pattern on the photoresist layer; wherein the cover layer can be used to reduce the footprint effect of the photoresist layer; and using the photoresist Layer as a mask, an etching process is performed on the cap layer, the oxynitride layer, the silicon oxide layer and the metal layer to transfer the pattern to the cap layer, the silicon oxynitride layer, the silicon oxide layer and the metal On the floor. 25. If the method of applying for the scope of patent application No. 24, where the above is formed (please read 1 * · Notes on the back before filling this page) The size of the paper is applicable to the national kneading rate (CNS) A4 of the country (210X297) (%) A8 B8 C8 D8 夂, patent application scope (please read the ^ -face ^ precautions before filling out this page) The step of forming the silicon nitride layer and simultaneously forming the silicon oxide layer is to use a plasma to enhance chemistry Formed by plasma enhanced chemical vapor deposition (PEC VD), and the machine used is a P-5000, CENTURA or Producer machine manufactured by Taiwan Applied Materials Co., Ltd. 26. The method of claim 24, wherein the steps of forming the silicon oxide layer and forming the silicon oxynitride layer simultaneously are performed in the same reaction chamber, and the reaction chamber used is AMAT DxZ, DLH or Twin type reaction chamber. 27. The method of claim 24, wherein the metal layer is an aluminum metal. 2 8. The method of claim 24, wherein before forming the silicon oxynitride layer described above, it further comprises forming a titanium nitride (TiN) layer on the metal layer as a barrier layer, wherein the nitride The titanium layer has a thickness of about 200 to 500 Angstroms. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 29. The method of item 24 of the patent application, wherein the above silicon nitrided silicon layer has a refractive index (η) of about 19 to 2.9, and an agricultural reflection coefficient (k) of about 0.5 To 0.9, the thickness of the silicon oxynitride layer is about 200 to 1500 Angstroms. twenty one 43 7 A8 B8 C8 D8 々、申請專利範圍 經濟部智慧財產局員工消費合作社印製 30.如申請專利範圍第24項之方法,其中上述之氧 化矽層厚度約5 0至8 0 0 0埃。 3 1 .如申請專利範圍第24項之方法’其中上述形成 該氮氧化矽層之步驟中,所使用之反應氣體包含40至60 5<:。〇1之5;^14、7〇至11〇5(:(:111之仏〇與约1600至260〇3(:(:111 之He。 3 2.如申請專利範圍第3 1項之方法,其中形成上述 氮氧化矽層之步驟,是在溫度約3 5 0至4 5 0 °C,壓力約5至 6 torr的環境中進行,且其中所施加之電壓功率約爲70至 1 3 0 Watt。 33 .如申請專利範圍第24項之方法’其中形成上述 氧化矽層之步驟中,所使用之反應氣體包含90至130 SCCm 之 SiH4 與 1800 至 2200 seem 之 N20° 3 4.如申請專利範圍第3 3項之方法,其中形成上述氧 化矽層之步驟,是在溫度約3 5 0至4 5 0*C ’壓力約1 8至2 6 torr的環境中進行,且其中所施加之電壓功率約爲200至 280 Watt ° 本紙張尺度適用中國國家橾準(CNS ) A4規格(210X297公釐) (請先閱^背^^注意事項再填寫永頁) 訂 C8 D8 &、申請專利範圍 35.如申請專利範圍第24項之方法,其中該蓋層具有 低含量之氬,以便在定義圖案於該光阻層上時’可降低光阻 層之足跡效應(footing)。 (請先閱讀背ώ之注意事項再填寫本頁) klr 咬 經濟部智慧財產局員工消費合作社印製 23 本紙張尺度適用t國國家橾準(CNS ) Α4規格(210Χ 297公釐)43 7 A8 B8 C8 D8 々. Scope of patent application. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 30. If the method of the scope of patent application is No. 24, the thickness of the above-mentioned silicon oxide layer is about 50 to 80 Angstroms. 31. The method according to item 24 of the scope of patent application, wherein in the step of forming the silicon oxynitride layer, the reaction gas used comprises 40 to 60 5 <:. 〇1 of 5; ^ 14, 70 to 1105 (: (: 111 of 111 and about 1600 to 260 003 (:: He of 111. 3 2. The method of the 31st scope of the patent application The step of forming the above silicon oxynitride layer is performed in an environment of a temperature of about 3 50 to 450 ° C, a pressure of about 5 to 6 torr, and an applied voltage and power of about 70 to 130 Watt. 33. The method according to item 24 of the scope of patent application, wherein in the step of forming the above silicon oxide layer, the reaction gas used includes SiH4 of 90 to 130 SCCm and N20 ° of 1800 to 2200 seem 3. The method according to item 33, in which the step of forming the above silicon oxide layer is performed in an environment with a temperature of about 3 50 to 4 50 * C 'and a pressure of about 18 to 2 6 torr, and the voltage applied therein Power is about 200 to 280 Watt ° This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) (Please read ^ back ^ ^ Note before filling in the permanent page) Order C8 D8 &, patent application scope 35. The method of claim 24, wherein the capping layer has a low argon content in order to define a pattern on the light When layered on top, it can reduce the footing effect of the photoresist layer. (Please read the precautions on the back page first and then fill out this page) klr Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 23 This paper is applicable to countries in t country Standard (CNS) A4 specification (210 × 297 mm)
TW88123152A 1999-12-28 1999-12-28 A method for measuring thickness of layers in chemical mechanic polishing process TW439117B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1646989B (en) * 2002-04-16 2011-06-01 国际商业机器公司 Composition for reflecting hardmask layer and method for forming characteristic of patterned material

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1646989B (en) * 2002-04-16 2011-06-01 国际商业机器公司 Composition for reflecting hardmask layer and method for forming characteristic of patterned material

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