KR20040103073A - Method for removing photo-resist in semiconductor manufacturing process - Google Patents
Method for removing photo-resist in semiconductor manufacturing process Download PDFInfo
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- KR20040103073A KR20040103073A KR1020030034960A KR20030034960A KR20040103073A KR 20040103073 A KR20040103073 A KR 20040103073A KR 1020030034960 A KR1020030034960 A KR 1020030034960A KR 20030034960 A KR20030034960 A KR 20030034960A KR 20040103073 A KR20040103073 A KR 20040103073A
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- 238000000034 method Methods 0.000 title claims abstract description 104
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 91
- 238000004380 ashing Methods 0.000 claims abstract description 31
- 239000007789 gas Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000001257 hydrogen Substances 0.000 claims abstract description 14
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 238000004528 spin coating Methods 0.000 claims abstract description 6
- 238000002513 implantation Methods 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- 239000002245 particle Substances 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 230000000452 restraining effect Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 8
- 150000002431 hydrogen Chemical class 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- -1 hydrogen compound Chemical class 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/42—Stripping or agents therefor
- G03F7/427—Stripping or agents therefor using plasma means only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Plasma & Fusion (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Drying Of Semiconductors (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
Description
본 발명은 반도체 제조공정에서의 포토레지스트 제거방법에 관한 것으로, 더욱 상세하게는 수소가스(H2)를 함유하고 있는 혼합가스를 플라즈마로 발생시켜 포토레지스트를 제거하는 애싱(ashing)공정이 수행되도록 하기 위한 반도체 제조공정에서의 포토레지스트 제거방법에 관한 것이다.The present invention relates to a method of removing a photoresist in a semiconductor manufacturing process, and more particularly to an ashing process of removing a photoresist by generating a mixed gas containing hydrogen gas (H 2 ) into a plasma. It relates to a photoresist removal method in a semiconductor manufacturing process for.
반도체 제조공정 중 하나인 포토 리소그래피(Photo Lithography)공정은 반도체 기판에 포토레지스트층을 형성하기 위하여 포토레지스트를 스핀(spin) 코팅하는 단계, 포토레지스트 층을 선택적으로 노광(exposure)하는 단계, 포토레지스트 패턴을 발생시키기 위하여 노광된 포토레지스트 층을 현상(Develope)하는 단계, 포토레지스트에 의하여 가려지지 않은 반도체 기판의 영역을 에칭(Eching) 혹은 불순물 주입하는 단계와 에칭 및 불순물 주입 단계에서 마스크로 사용된 포토레지스트 패턴을 제거하는 애싱 단계로 이루어 진다.Photolithography, one of the semiconductor manufacturing processes, involves spin coating a photoresist to selectively form a photoresist layer on a semiconductor substrate, selectively exposing the photoresist layer, and photoresist. Developing an exposed photoresist layer to generate a pattern, etching or impurity implantation of regions of the semiconductor substrate that are not covered by the photoresist and used as masks in the etching and impurity implantation steps. An ashing step is performed to remove the photoresist pattern.
상기 반도체 제조공정 중 애싱 단계를 수행한 후에는 웨이퍼에 형성된 소자간의 연결을 위한 배선, 칩 외부와의 연결을 위해 본드 패드(Bone Pad)용 등으로 사용되는 금속막을 형성하기 위한 금속 배선층 형성 공정이 이어진다.After the ashing step is performed in the semiconductor manufacturing process, a metal wiring layer forming process for forming a metal film used for connection between devices formed on a wafer and a bond pad for connection to the outside of the chip is performed. It leads.
그중에서 애싱공정은 에칭공정 또는 이온주입공정 후 임무가 끝난 포토레지스트를 제거하는 공정으로 일종의 식각 공정이다. 포토레지스트 물질은 포토레지스트 밑에 있는 기판에 패턴을 에칭하기 위해 또는 기판의 노출 영역 안으로 이온을 선택적으로 주입하기 위한 마스크로 사용되는 물질이다.Among them, the ashing process is a process of removing the finished photoresist after the etching process or the ion implantation process, which is a kind of etching process. The photoresist material is a material used as a mask to etch a pattern into a substrate underneath the photoresist or to selectively implant ions into an exposed area of the substrate.
그리고, 상기 애싱공정에서는 플라즈마를 이용하는데 반응가스로는 주로 산소(O2)를 이용하고 있다. 그러므로 상기 포토레지스트 제거 공정은 결과적으로 포토레지스트를 산소와 반응시키는 것이므로 산화과정이라 할 수 있으며 산화는 일종의 태워버리는 것이므로 'Ashing' 공정이라고 불리우며, 상기와 같이 애싱 공정을 수행하는 장비를 애셔(Asher)라 한다.In the ashing process, plasma is used, but oxygen (O 2 ) is mainly used as a reaction gas. Therefore, the photoresist removal process is an oxidation process because the photoresist is reacted with oxygen as a result, and since the oxidation is a kind of burning, it is called an ashing process. It is called.
최근에는 반도체 제조기술에 있어서 디바이스의 집적도 및 고속도가 요구됨에 따라서 웨이퍼의 공정이 더욱 세밀해지고 있으나, 이러한 상황에서는 웨이퍼의 주 구성 성분인 실리콘이 여러 공정상에서 조금씩 손실되고 있는 문제점이 발생한다. 특히, 애싱을 하는 과정에서 사용되는 플라즈마 발생을 위해 산소가스를 사용하는 경우 웨이퍼의 일부 표면이 상기 공정가스인 산소와 반응을 해서 산화막이 생기게 된다. 상기와 같이 실리콘 표면에 산화막 층이 생기게 되면 결과적으로 향후 쉘로우 졍션(shallow juntion)을 필요로 하는 소자 제조 및 전극으로 사용하는 도핑된 다결정 실리콘(doped poly-si)의 손실이 많이 생기는 문제점이 있다.In recent years, as semiconductor device technology requires device density and high speed, wafer processing is becoming more detailed. However, in this situation, silicon, which is a main component of the wafer, is gradually lost in various processes. In particular, when oxygen gas is used to generate plasma used in the ashing process, an oxide film is formed by reacting some surfaces of the wafer with oxygen, which is the process gas. As described above, when the oxide layer is formed on the silicon surface, there is a problem that a lot of doped poly-si (Si) used as an electrode and a device is fabricated requiring a shallow junction in the future.
또한, 종래와 같은 포토레지스트 애싱공정에서는 웨이퍼에 고 도즈 이온주입(High Dose Implantation)한 후에 파핑 현상이 발생하게 되므로, 상기 파핑현상을 감소시키기 위해 공정온도를 저온으로 하거나 고 도즈 이온주입(High Dose Implantation) 공정이후에 핀업(Pin-up)공정이 수행되도록 하나, 파핑문제를 완전히 해결할 수 없다는 문제점이 있다.In addition, in the conventional photoresist ashing process, since a paping phenomenon occurs after high dose ion implantation on a wafer, a process temperature is lowered or a high dose ion implantation is performed in order to reduce the paping phenomenon. After the implantation process, a pin-up process is performed, but there is a problem in that the popping problem cannot be completely solved.
또한 고집적화된 실리콘에서는 파장이 436㎚대인 G-line 빛이나 파장이 365㎚대인 I-line 빛은 빛의 파장이 길어 기판상에서 정의할 수 있는 선폭이 너무 큰 문제점이 있으므로 보다 정밀한 작업을 수행하기 위하여는 파장이 248㎚, 193㎚ 대인 하이 도우즈 이온이 주입된 DUV(Deep Ultra Violet) 빛과 X 선의 사용이 더 유리한 점이 있다. 또한 기존의 I-line포토레지스트는 그 분자의 크기가 크고 점성이 큰 문제점이 있기 때문에 고집적화된 실리콘에서는 I-line 포토레지스트 대신에 하이 도우즈 이온이 주입된 DUV(Deep Ultra Violet) 포토레지스트를 사용하고 있다.In addition, in the highly integrated silicon, G-line light having a wavelength of 436 nm or I-line light having a wavelength of 365 nm has a long wavelength of light, which can be defined on the substrate, so that the line width can be defined. The use of DUV (Deep Ultra Violet) light and X-ray implanted with high dose ions having wavelengths of 248 nm and 193 nm is more advantageous. In addition, the conventional I-line photoresist has a problem that the molecule is large in size and has a high viscosity, so highly integrated silicon uses DUV (Deep Ultra Violet) photoresist implanted with high dose ions instead of I-line photoresist. Doing.
그러나 상기의 하이 도우즈 이온이 주입된 DUV 포토레지스트는 기존의 산소를 이용하는 애싱공정으로는 잔여물이 제거되지 않는 문제점이 있다.However, the DUV photoresist into which the high dose ions are implanted has a problem that residues are not removed by an ashing process using oxygen.
이에 따라 본 발명의 목적은 수소가스(H2)를 함유하고 있는 혼합가스를 플라즈마로 발생시켜 포토레지스트를 제거하는 애싱(ashing)공정이 수행되도록 하기 위한 반도체 제조공정에서의 포토레지스트 제거방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a photoresist removal method in a semiconductor manufacturing process for performing an ashing process of removing a photoresist by generating a mixed gas containing hydrogen gas (H 2 ) into a plasma. It is.
또한 본 발명의 다른 목적은 실리콘 산화막의 생성을 최소화하여 실리콘의 손실을 최소화하고 파핑현상이 전혀 발생하지 않도록 하며, 하이 도우즈 이온이 주입된 DUV 포토레지스트의 잔여물마저 완전히 제거할 수 있도록 하기 위한 반도체 제조공정에서의 포토레지스트 제거방법을 제공하는데 있다.In addition, another object of the present invention is to minimize the formation of silicon oxide film to minimize the loss of silicon, so that no paping occurs at all, and to completely remove the residue of the DUV photoresist implanted with high dose ions A photoresist removal method in a semiconductor manufacturing process is provided.
본 발명의 또 다른 목적은 애싱 공정의 효율을 높일 수 있는 반도체 제조공정에서의 포토레지스트 제거방법을 제공함에 있다.Another object of the present invention is to provide a method of removing photoresist in a semiconductor manufacturing process that can increase the efficiency of the ashing process.
도1은 종래의 방법에 의하여 공정을 수행한 후 촬영한 투과전자현미경 사진이다.1 is a transmission electron microscope photograph taken after performing a process by a conventional method.
도2는 본원발명의 실시예에 의하여 공정을 수행한 후 투과전자현미경으로 촬영한 사진이다.2 is a photograph taken with a transmission electron microscope after the process according to an embodiment of the present invention.
따라서 본 발명은 상기 목적을 달성하기 위하여, 반도체 구조체로부터 포토레지스트 물질을 제거하는 애싱 공정에 수소(H2)가스를 사용하는 플라즈마의 이용을 제안한다. 본 발명은 모든 포토레지스트 애싱공정에 적용이 가능하며, 특히 하이 도우즈 이온 주입(High Dose Ion Implantation) 실리콘 기판에서 그 효용성이 크다.Accordingly, the present invention proposes the use of a plasma using hydrogen (H 2 ) gas in the ashing process for removing the photoresist material from the semiconductor structure to achieve the above object. The present invention can be applied to all photoresist ashing processes, and is particularly useful in high dose ion implantation silicon substrates.
본 발명에 따른 애싱 방법에서는 반도체 기판에 포토레지스트층을 형성하기 위하여 포토레지스트를 스핀(spin) 코팅하는 단계와; 포토레지스트 층을 선택적으로 노광(exposure)하는 단계와; 포토레지스트 패턴을 발생시키기 위하여 노광된 포토레지스트 층을 현상(Develope)하는 단계와; 상기 포토레지스트에 의하여 가려지지 않은 반도체 기판의 영역을 에칭(Eching) 혹은 불순물 주입하는 단계와; 상기 에칭 및 불순물 주입 단계에서 마스크로 사용된 포토레지스트 패턴을 제거하는 애싱 단계를 포함하는 반도체 제조공정에 있어서, 상기 애싱단계는, 수소(H2)를 함유하는 혼합가스를 플라즈마로 발생시켜 고온에서도 파핑이 발생되지 않아 파티클 발생이 억제된 상태에서 포토레지스트 패턴이 제거되도록 하는 것을 특징으로 하는 반도체 제조공정에서의 포토레지스트 제거 방법으로서, 상술한 과제를 해결한다.The ashing method according to the present invention comprises the steps of spin coating the photoresist to form a photoresist layer on the semiconductor substrate; Selectively exposing a photoresist layer; Developing the exposed photoresist layer to generate a photoresist pattern; Etching or impurity implantation of regions of the semiconductor substrate that are not covered by the photoresist; In the semiconductor manufacturing process including the ashing step of removing the photoresist pattern used as a mask in the etching and impurity implantation step, the ashing step, by generating a mixed gas containing hydrogen (H 2 ) to the plasma at a high temperature A photoresist removal method in a semiconductor manufacturing process characterized in that the photoresist pattern is removed in a state in which particle generation is suppressed because no paping occurs, thereby solving the above problem.
특히, 상기와 같이 수소를 함유하는 혼합가스를 플라즈마로 발생시키는 경우 산화막 생성을 최소화시킬 수 있기 때문에 실리콘 손실을 최소화시킬 수 있다.In particular, when generating a mixed gas containing hydrogen in the plasma as described above it can minimize the loss of silicon because the oxide film generation can be minimized.
또한, 상기 반도체 기판은, 고 도즈 이온 주입(High Dose ion Implantation) 방식에 따라 제작된 기판인 것을 특징으로 하는 반도체 제조공정에서의 포토레지스트 제거방법으로서, 상술한 과제를 해결한다.In addition, the semiconductor substrate is a photoresist removing method in a semiconductor manufacturing process, characterized in that the substrate produced by a high dose ion implantation (High Dose ion Implantation) method, solves the above problems.
또한, 상기 포토레지스트는, 고자외선(Deep Ultra Violet) 포토레지스트를 포함하는 것을 특징으로 하는 반도체 제조공정에서의 포토레지스트 제거방법으로서, 상술한 과제를 해결한다.In addition, the photoresist is a method of removing a photoresist in a semiconductor manufacturing process, characterized in that it comprises a deep ultra violet photoresist, which solves the above problems.
또한, 상기 수소(H2)와 혼합되는 가스는, 질소(N2), 헬륨(He) 중 하나인 것을 특징으로 하는 반도체 제조공정에서의 포토레지스트 제거방법으로서, 상술한 과제를 해결한다.In addition, the gas mixed with the hydrogen (H 2 ) is one of nitrogen (N 2 ) and helium (He), which solves the above-described problem in the method of removing a photoresist in a semiconductor manufacturing process.
또한, 본 발명에서 상기 수소(H2) 가스의 량이 전체 가스량에 대하여 2부피% 내지 100부피% 인 것을 특징으로 하는 반도체 제조공정에서의 포토레지스트 제거방법으로서, 상술한 과제를 해결한다.In addition, in the present invention, the above-mentioned problem is solved by the method of removing a photoresist in a semiconductor manufacturing process, wherein the amount of hydrogen (H 2 ) gas is 2% by volume to 100% by volume based on the total amount of gas.
또한, 상기 애싱공정의 온도가, 100℃에서 200℃ 사이인 것을 특징으로 하는포토레지스트 제거방법으로서, 상술한 과제를 해결한다.Moreover, the problem mentioned above is solved as a photoresist removal method characterized by the temperature of the said ashing process being between 100 degreeC and 200 degreeC.
또한, 본 발명의 다른 실시예는 반도체 기판에 포토레지스트층을 형성하기 위하여 포토레지스트를 스핀(spin) 코팅하는 단계와; 포토레지스트 층을 선택적으로 노광(exposure)하는 단계와; 포토레지스트 패턴을 발생시키기 위하여 노광된 포토레지스트 층을 현상(Develope)하는 단계와; 상기 포토레지스트에 의하여 가려지지 않은 반도체 기판의 영역을 에칭(Eching) 혹은 불순물 주입하는 단계와; 상기 에칭 및 불순물 주입 단계에서 마스크로 사용된 포토레지스트 패턴을 제거하는 애싱 단계를 포함하는 반도체 제조공정에 있어서, 상기 애싱단계는, 수소(H2)를 함유하는 혼합가스 또는 암모니아(NH3)를 플라즈마로 발생시켜 고온에서도 파핑이 발생되지 않아 파티클 발생이 억제된 상태에서 포토레지스트 패턴이 제거되도록 하는 것을 특징으로 하는 반도체 제조공정에서의 포토레지스트 제거 방법으로서, 상술한 과제를 해결한다.In addition, another embodiment of the present invention comprises the steps of spin coating the photoresist to form a photoresist layer on the semiconductor substrate; Selectively exposing a photoresist layer; Developing the exposed photoresist layer to generate a photoresist pattern; Etching or impurity implantation of regions of the semiconductor substrate that are not covered by the photoresist; In the semiconductor manufacturing process including an ashing step of removing the photoresist pattern used as a mask in the etching and impurity implantation step, the ashing step, a mixed gas containing hydrogen (H 2 ) or ammonia (NH 3 ) A photoresist removal method in a semiconductor manufacturing process, wherein the photoresist pattern is removed in a state in which particle generation is suppressed because the generation of plasma is not caused at high temperature, thereby solving the above problems.
이하 에서는 본 발명을 첨부한 도면을 참조하여 바람직한 실시 예를 통하여 상세히 설명한다. 아래의 표1은 전체 실험의 예로서 요약표이다.Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail through preferred embodiments. Table 1 below is a summary table as an example of the entire experiment.
상기 [표1]을 간단히 설명하지면 A 공정은 종래에 사용하던 애싱 방법 중 O2가스 7000sccm 와 N2가스 800sccm 를 250℃ 공정온도에서 75초의 시간 동안 공정을 수행한 것으로, 첨부도면 도1에 나타난 바와 같이 공정 수행 후 투과전자현미경으로 산화막의 두께를 측정한 결과 두께가 17Å으로 측정된다.In brief description of Table 1, the process A is performed by performing the process of the O 2 gas 7000sccm and the N 2 gas 800sccm in a process temperature of 250 seconds at a process temperature of 250 ° C. in the conventional ashing method. As shown, the thickness of the oxide film was measured by a transmission electron microscope after the process was performed.
다음으로 B 공정은 본 발명의 실시예 중에서 8000sccm H2N2가스만으로 250℃에서 285초 동안 공정을 수행한 것으로, 도2에 나타난 바와 같이 공정 수행 후 투과전자현미경으로 측정한 결과 산화막의 두께는 거의 측정할 수 없을 정도이다.Next, in step B, the process was performed for 285 seconds at 250 ° C. with only 8000 sccm H 2 N 2 gas in the embodiment of the present invention. As shown in FIG. 2, the thickness of the oxide film was measured by transmission electron microscope after the process was performed. It is almost impossible to measure.
또한 상기 표1의 조건으로 진행한 공정에 대하여 공정 챔버(process chamber)의 보임창으로 확인해 본 결과, 종래 기술 공정인 A 공정은 파핑현상이 발견되고 본 발명의 실시예인 수소가스를 사용한 B 공정에서는 파핑현상이 전혀 나타나지 않는다.In addition, as a result of confirming with the window of the process chamber about the process proceeded under the conditions of Table 1, the process A is a prior art process is found in the process B and the process B using hydrogen gas as an embodiment of the present invention There is no popping phenomenon.
상기 [표2]는 하이 도우즈 이온이 주입된 DUV 포토레지스트를 사용한 웨이퍼에서 애싱 공정을 수행한 후 잔여물을 조사한 것이다.[Table 2] shows the residue after performing the ashing process on the wafer using a DUV photoresist implanted with high dose ions.
C 공정은 일반적으로 기존의 포토레지스트를 제거하는 공정으로서 압력은 2 Torr, O2는 17000 sccm, N2는 1900 sccm, 공정온도는 250℃, 공정시간은 150 초 동안으로 하여 공정을 수행한 것이다.Process C is generally a process to remove the existing photoresist, the pressure is 2 Torr, O 2 is 17000 sccm, N 2 is 1900 sccm, the process temperature is 250 ℃, the process time is 150 seconds .
D 공정은 본 발명의 일 실시예로서 압력은 2 Torr, O2는 8000 sccm, H2N2는8000 sccm, 공정온도는 150℃, 공정시간은 150초 동안으로 하여 공정을 수행한 것이다.D process is an embodiment of the present invention, the pressure is 2 Torr, O 2 is 8000 sccm, H 2 N 2 is 8000 sccm, the process temperature is 150 ℃, the process time is carried out for 150 seconds.
상기 공정을 수행한 후 그 결과를 검토하여 보면, C 공정의 결과에서는 많은 잔여물이 남아 있는 반면, D 공정을 수행한 경우에는 잔여물이 완전히 제거된다.After reviewing the results after performing the process, many residues remain in the results of process C, while residues are completely removed when the process D is performed.
수소가스를 기본으로 하는 공정에서, 수소를 기본으로 하면서 위 실험에서 사용한 질소(N2)는 물론이고 헬륨(He)을 사용한 혼합물도 상기 [표2]와 같은 결과를 보였으며 암모니아(NH3) 같은 수소 화합물로 공정을 수행한 경우에도 잔여물을 완전히 제거할 수 있다.In the process based on hydrogen gas, the mixture based on nitrogen (N 2 ) as well as helium (He) used in the above experiments based on hydrogen showed the same results as in [Table 2] above and ammonia (NH 3 ) Even if the process is carried out with the same hydrogen compound, the residue can be completely removed.
상기 공정을 수행하면서 반응(공정)온도를 100 내지 200℃로 한 경우에서도 잔여물이 모두 제거되는 효과를 달성할 수 있다.Even when the reaction (process) temperature is set to 100 to 200 ° C. while performing the above process, all of the residues can be removed.
상기에서 설명한 바와 같이, 포토레지스트를 애싱하는 공정에서 본 발명이 제시하는 공정을 사용하여 진행한 경우 실시예의 결과에서 알 수 있듯이 산화막이 전혀 형성되지 않기 때문에, 향후 쉘로우 졍션을 필요로 하는 소자 제조 및 전극으로 사용하는 도핑된 다결정 실리콘(doped poly-Si)의 제작시 실리콘 손실을 막을 수 있다는 효과를 달성할 수 있다.As described above, when the process of ashing the photoresist proceeds using the process proposed by the present invention, as the result of the embodiment shows that no oxide film is formed, device fabrication requiring shallow cushioning in the future and It is possible to achieve the effect of preventing the loss of silicon in the production of doped poly-silicon (doped poly-Si) used as an electrode.
또한 본 발명은 고 도즈 이온 주입(High Dose Ion Implantation)후에 포토레지스트를 제거하기 위해 수행하는 애싱 공정에서 본 발명의 방법을 사용하는 경우 200℃이상의 공정온도에서도 파핑(popping) 현상이 전혀 발생하지 않아파티클(particle)발생을 억제할 수 있으므로 반도체 제조 생산수율을 향상시킬 수 있다는 효과를 달성할 수 있다.In addition, the present invention does not generate any popping phenomenon even at a process temperature of 200 ° C. or higher when the method of the present invention is used in an ashing process performed to remove photoresist after high dose ion implantation. Particles (particles) can be suppressed, so that the effect of improving the semiconductor manufacturing production yield can be achieved.
또한 본 발명은 고집적화된 실리콘에서 필수적으로 사용하는 하이 도우즈 이온이 주입된 DUV 포토레지스트의 잔여물을 제거하는 공정에서 본 발명인 수소를 기본으로 하는 화합물이나 혼합물을 저온에서 사용했을 때 하이 도우즈 이온이 주입된 DUV 포토레지스트의 잔여물이 완전히 제거할 수 있도록 하는 효과를 달성할 수 있다.In addition, the present invention is a high-dose ion when the hydrogen-based compound or mixture of the present invention is used at a low temperature in the process of removing the residue of the DUV photoresist implanted with high-dose ions essential to highly integrated silicon. The effect of allowing the residue of this implanted DUV photoresist to be completely removed can be achieved.
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| US6346489B1 (en) * | 1999-09-02 | 2002-02-12 | Applied Materials, Inc. | Precleaning process for metal plug that minimizes damage to low-κ dielectric |
| JP2001313280A (en) * | 2000-04-02 | 2001-11-09 | Axcelis Technologies Inc | Postetched photoresist and method for removing residue |
| JP2002158210A (en) * | 2000-11-20 | 2002-05-31 | Shibaura Mechatronics Corp | Resist removing method |
-
2003
- 2003-05-30 KR KR20030034960A patent/KR100542031B1/en not_active IP Right Cessation
-
2004
- 2004-05-29 WO PCT/KR2004/001279 patent/WO2004107418A1/en active Application Filing
- 2004-05-29 JP JP2005518198A patent/JP2006513586A/en active Pending
- 2004-05-29 CN CNB2004800008915A patent/CN100343953C/en not_active Expired - Fee Related
- 2004-05-31 TW TW93115506A patent/TWI251265B/en not_active IP Right Cessation
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9941108B2 (en) | 2004-12-13 | 2018-04-10 | Novellus Systems, Inc. | High dose implantation strip (HDIS) in H2 base chemistry |
| KR100679826B1 (en) * | 2004-12-22 | 2007-02-06 | 동부일렉트로닉스 주식회사 | Method for removing the polymer residue of MIM area |
| KR100736126B1 (en) * | 2005-12-28 | 2007-07-06 | 동부일렉트로닉스 주식회사 | Method for manufacturing semiconductor device |
| KR100727706B1 (en) * | 2006-05-15 | 2007-06-13 | 동부일렉트로닉스 주식회사 | Method for stabilizing atmosphere inside the asher chamber |
| US9564344B2 (en) | 2009-12-11 | 2017-02-07 | Novellus Systems, Inc. | Ultra low silicon loss high dose implant strip |
| US9613825B2 (en) | 2011-08-26 | 2017-04-04 | Novellus Systems, Inc. | Photoresist strip processes for improved device integrity |
| US9514954B2 (en) | 2014-06-10 | 2016-12-06 | Lam Research Corporation | Peroxide-vapor treatment for enhancing photoresist-strip performance and modifying organic films |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1701414A (en) | 2005-11-23 |
| CN100343953C (en) | 2007-10-17 |
| KR100542031B1 (en) | 2006-01-11 |
| TWI251265B (en) | 2006-03-11 |
| TW200426917A (en) | 2004-12-01 |
| WO2004107418A1 (en) | 2004-12-09 |
| JP2006513586A (en) | 2006-04-20 |
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