JPH03116737A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03116737A JPH03116737A JP25331789A JP25331789A JPH03116737A JP H03116737 A JPH03116737 A JP H03116737A JP 25331789 A JP25331789 A JP 25331789A JP 25331789 A JP25331789 A JP 25331789A JP H03116737 A JPH03116737 A JP H03116737A
- Authority
- JP
- Japan
- Prior art keywords
- plasma
- electrode
- hydrogen
- substrate
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000001301 oxygen Substances 0.000 claims abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 6
- YZCKVEUIGOORGS-IGMARMGPSA-N Protium Chemical compound [1H] YZCKVEUIGOORGS-IGMARMGPSA-N 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 5
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 4
- 229910001882 dioxygen Inorganic materials 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 4
- 239000001257 hydrogen Substances 0.000 abstract description 4
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 238000004380 ashing Methods 0.000 abstract 1
- 238000007599 discharging Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 12
- 230000000694 effects Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 235000002918 Fraxinus excelsior Nutrition 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000002956 ash Substances 0.000 description 1
- XMPZTFVPEKAKFH-UHFFFAOYSA-P ceric ammonium nitrate Chemical compound [NH4+].[NH4+].[Ce+4].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O XMPZTFVPEKAKFH-UHFFFAOYSA-P 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は薄膜トランジスタ
(以後TPTと呼ぶ)
等、半導体装置の製造方法に関し、特に眉間絶縁膜によ
り被覆された電極と電気的接続を得る際に、安定にオー
ミック接触を得るための電極上の酸化物除去法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing semiconductor devices such as thin film transistors (hereinafter referred to as TPT), and particularly to a method for manufacturing semiconductor devices such as thin film transistors (hereinafter referred to as TPT). The present invention relates to a method for removing oxides on electrodes to obtain ohmic contact.
従来の技術
第4図に従来のTPTの工程断面図を示す。第4図(a
)に示すように基板1上にCr等からなるゲート電極2
を選択的に被着形成後、全面に窒化シリコン等からなる
ゲート絶縁膜3を堆積し、さらにゲート電極2の一部と
重なるように非晶質シリコン半導体膜4が堆積される。BACKGROUND OF THE INVENTION FIG. 4 shows a cross-sectional view of a conventional TPT process. Figure 4 (a
), a gate electrode 2 made of Cr or the like is formed on a substrate 1.
After selectively depositing the gate electrode 2, a gate insulating film 3 made of silicon nitride or the like is deposited on the entire surface, and an amorphous silicon semiconductor film 4 is further deposited so as to partially overlap the gate electrode 2.
次に第4図ら)に示すようにホトレジスト5を塗布後露
光、現像して電極2と電気的に接続を必要とする部分に
開口部7を形成する。その後第4図(C)に示すように
開口部7のゲート絶縁膜をエツチング除去し、さらにホ
トレジストを真空室内で酸素プラズマにより灰化除去す
る。最後に第4図(d)に示すようにA1等からなるソ
ース・ドレイン電極6 a s 6 bおよびゲート電
極2と電気的接続を得るための電極6Cを選択的に被着
形成してTPTが完成する。Next, as shown in FIG. 4 et al., a photoresist 5 is coated, exposed and developed to form openings 7 in areas where electrical connection with the electrodes 2 is required. Thereafter, as shown in FIG. 4C, the gate insulating film in the opening 7 is removed by etching, and the photoresist is removed by ashes using oxygen plasma in a vacuum chamber. Finally, as shown in FIG. 4(d), source/drain electrodes 6a, s, 6b made of A1, etc. and an electrode 6C for electrical connection with the gate electrode 2 are selectively deposited to form TPT. Complete.
発明が解決しようとする課題
前述の製造方法において、酸素プラズマによりレジスト
を除去する際に、Crゲート電極2の表面に酸化Crが
形成される。この酸化Cr膜は希フッ酸等一般的な酸性
水溶液により容易に除去できないため、Crゲート電極
2とAI電極6cとの間の抵抗となり、第2図の曲線(
b)に示すようにCr−Al電極間の印加電圧に対して
電流が直線的に増加しないというような正常な電気的接
続が得られず、またこのことが原因となってTPT特性
が劣化するという不良が発生した(第3図参照)また、
従来酸化Crを除去するために硝酸セリウムアンモニウ
ムを主成分とする専用エツチング液を用いて除去した。Problems to be Solved by the Invention In the above-described manufacturing method, Cr oxide is formed on the surface of the Cr gate electrode 2 when the resist is removed using oxygen plasma. Since this Cr oxide film cannot be easily removed with a general acidic aqueous solution such as dilute hydrofluoric acid, it becomes a resistance between the Cr gate electrode 2 and the AI electrode 6c, and the curve (
As shown in b), a normal electrical connection such as the current not increasing linearly with the applied voltage between the Cr-Al electrodes cannot be obtained, and this causes deterioration of the TPT characteristics. A defect occurred (see Figure 3).
Conventionally, Cr oxide was removed using a special etching solution containing cerium ammonium nitrate as a main component.
しかしながら、エツチングの均一性が悪く、かつCr自
身がエツチングされるために、工程管理が複雑になるば
かりでなくCrが除去されない部分が発生したり、Cr
電極が消失するという不良が発生した。However, the uniformity of etching is poor and Cr itself is etched, which not only complicates process control, but also causes parts where Cr is not removed, and Cr itself to be etched.
A defect occurred in which the electrode disappeared.
本発明はかかる課題にのぞみなされたもので、正常な電
気的接続が得るための酸化膜の容易な除去方法によりT
PT特性が劣化することのない製造方法を提供すること
を目的とする。The present invention was conceived to solve this problem, and provides a method for easily removing the oxide film to obtain normal electrical connection.
It is an object of the present invention to provide a manufacturing method that does not cause deterioration of PT characteristics.
課題を解決するための手段
本発明は上記課題を解決するために酸素プラズマにより
レジストを除去した後、プラズマ放電や光により発生さ
せた水素ラジカル雰囲気中にさらすことより酸化膜を除
去する。Means for Solving the Problems In order to solve the above problems, the present invention removes the resist using oxygen plasma and then removes the oxide film by exposing the resist to a hydrogen radical atmosphere generated by plasma discharge or light.
作用
本発明は上記技術的手段により表面に形成された酸化膜
が還元され、酸化膜を除去したのと同様の効果が得られ
るため、良好な電気的接続が得られる。また、酸化膜が
除去された時点でそれ以上の還元反応は停止するため素
材の金属が消失することはない。Function: According to the present invention, the oxide film formed on the surface is reduced by the above-mentioned technical means, and an effect similar to that obtained by removing the oxide film can be obtained, so that a good electrical connection can be obtained. Furthermore, once the oxide film is removed, further reduction reactions stop, so the metal material does not disappear.
実施例 以下、本発明の実施例について説明する。Example Examples of the present invention will be described below.
第1図に本実施例の工程断面図を示す。第1図(a)に
示すように基板21上にCrゲート電極22を形成し、
プラズマCVD法により窒化シリコン23を全面に堆積
し、ゲート電極22と一部重なるように非晶質シリコン
半導体24を堆積する。次にホトレジスト25を塗布し
、露光、現像工程により第1図ら)に示すようにCr電
極上に開口部を形成し、さらに開口部29の窒化シリコ
ンをエツチング除去する。その後、第1図(C)に示す
ように基板をプラズマ処理装置27に入れ、酸素ガスを
導入してプラズマ放電によりレジストを灰化除去し、続
いて酸素ガスの代わりに水素ガスを導入し、真空度I
Torr、放電電力300mW/cd、放電時間5分の
条件で連続的にプラズマ放電を行い、水素ラジカル中に
さらす。最後に第1図(d)に示すようにソース・ドレ
インおよび接続AI電極26a、b、cを形成して本実
施例の製造方法によるTPTが完成する。FIG. 1 shows a process sectional view of this embodiment. As shown in FIG. 1(a), a Cr gate electrode 22 is formed on a substrate 21,
Silicon nitride 23 is deposited over the entire surface by plasma CVD, and amorphous silicon semiconductor 24 is deposited so as to partially overlap gate electrode 22 . Next, a photoresist 25 is applied, and an opening is formed on the Cr electrode by exposure and development steps as shown in FIG. 1, etc., and the silicon nitride in the opening 29 is etched away. Thereafter, as shown in FIG. 1(C), the substrate is placed in a plasma processing apparatus 27, oxygen gas is introduced and the resist is incinerated and removed by plasma discharge, and then hydrogen gas is introduced instead of oxygen gas. Vacuum degree I
Plasma discharge was performed continuously under the conditions of Torr, discharge power of 300 mW/cd, and discharge time of 5 minutes, and the specimen was exposed to hydrogen radicals. Finally, as shown in FIG. 1(d), the source/drain and connecting AI electrodes 26a, b, c are formed to complete the TPT according to the manufacturing method of this embodiment.
このように形成したCrゲート電極22とAI電極26
c間の電流〜電圧特性を測定したところ、第2図の直線
(a)に示すように、電圧の増加とともに電流が直線的
に増加し、良好な電気的接続が得られていることがわか
る。また、完成したTPTの特性を評価したところ、第
3図に示すように従来の製造方法により作製したTPT
に比べ闇値電圧が小さくなり、また飽和電流が増加して
特性が改善された。The Cr gate electrode 22 and AI electrode 26 formed in this way
When measuring the current-voltage characteristics between C and C, as shown in the straight line (a) in Figure 2, the current increases linearly as the voltage increases, indicating that a good electrical connection is obtained. . Furthermore, when we evaluated the characteristics of the completed TPT, we found that the TPT produced by the conventional manufacturing method was
Compared to the previous model, the dark voltage was lower, the saturation current was increased, and the characteristics were improved.
発明の効果
以上述べてきたように、本発明は酸素プラズマによるレ
ジスト除去の際に形成された金属の酸化膜を水素プラズ
マにより還元することにより、素材の電極が消失するこ
となく安定して他方の電極との電気的接続が得られ、T
PT特性が劣化しない製造方法を提供できる効果を有す
る。Effects of the Invention As described above, the present invention uses hydrogen plasma to reduce the metal oxide film formed during resist removal using oxygen plasma, thereby stably removing the material electrode from the other side without losing it. Electrical connection with the electrode is obtained and T
This has the effect of providing a manufacturing method that does not cause deterioration of PT characteristics.
第1図は本発明の実施例の工程断面図、第2図は従来お
よび本発明の実施例における電気的接続部の電流−電圧
特性図、第3図はTPT特性図、第4図は従来の工程断
面図である。
1.21・・・・・・ガラス基板、2,22・・・・・
・Cr電極、3.33・・・・・・ゲート絶縁膜、4,
44・・・・・・半導体膜、5.25・・・・・・ホト
レジスト、6,26・・・・・・AI電極、27・・・
・・・真空室、28・・・・・・水素プラズマ。Fig. 1 is a process sectional view of an embodiment of the present invention, Fig. 2 is a current-voltage characteristic diagram of the electrical connection part in the conventional and embodiment of the present invention, Fig. 3 is a TPT characteristic diagram, and Fig. 4 is a conventional FIG. 1.21...Glass substrate, 2,22...
・Cr electrode, 3.33... Gate insulating film, 4,
44...Semiconductor film, 5.25...Photoresist, 6,26...AI electrode, 27...
...Vacuum chamber, 28...Hydrogen plasma.
Claims (2)
導電体層を選択的に形成する工程と、絶縁体層を全面に
被覆する工程と、前記第1の導電体層上の絶縁体層の一
部に開口部を形成するためのレジストを真空室内の酸素
プラズマにより除去する工程、前記開口部内の前記第1
の導電体層の表面を真空室内で水素ラジカル雰囲気中に
暴露する工程と、第2の導電体層を前記第1の導電体層
と電気的に接続するように選択的に形成する工程とを有
する半導体装置の製造方法。(1) A step of selectively forming a first conductive layer made of a metal or a semiconductor on one main surface of the substrate, a step of covering the entire surface with an insulating layer, and a step of coating the first conductive layer on the first conductive layer. a step of removing a resist for forming an opening in a part of the insulating layer using oxygen plasma in a vacuum chamber;
a step of exposing the surface of the conductor layer to a hydrogen radical atmosphere in a vacuum chamber; and a step of selectively forming a second conductor layer so as to be electrically connected to the first conductor layer. A method for manufacturing a semiconductor device comprising:
ズマ放電により形成されることを特徴とする請求項(1
)記載の半導体装置の製造方法。(2) Claim (1) characterized in that the hydrogen radical atmosphere is formed by plasma discharge using hydrogen gas.
) A method for manufacturing a semiconductor device according to the method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25331789A JPH03116737A (en) | 1989-09-28 | 1989-09-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25331789A JPH03116737A (en) | 1989-09-28 | 1989-09-28 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03116737A true JPH03116737A (en) | 1991-05-17 |
Family
ID=17249622
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25331789A Pending JPH03116737A (en) | 1989-09-28 | 1989-09-28 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03116737A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100269286B1 (en) * | 1996-10-24 | 2000-10-16 | 윤종용 | Manufacturing method for polysilicon-TFT |
US6759283B2 (en) * | 2001-05-16 | 2004-07-06 | Nec Lcd Technologies, Ltd. | Thin film transistor and method of fabricating the same |
WO2004107418A1 (en) * | 2003-05-30 | 2004-12-09 | Psk, Inc. | Method for removing photoresist in semiconductor manufacturing process |
CN1324359C (en) * | 2003-05-28 | 2007-07-04 | 友达光电股份有限公司 | Planar displaying device and producing method thereof |
CN109920729A (en) * | 2019-03-27 | 2019-06-21 | 合肥鑫晟光电科技有限公司 | A kind of preparation method of display base plate, display device |
-
1989
- 1989-09-28 JP JP25331789A patent/JPH03116737A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100269286B1 (en) * | 1996-10-24 | 2000-10-16 | 윤종용 | Manufacturing method for polysilicon-TFT |
US6759283B2 (en) * | 2001-05-16 | 2004-07-06 | Nec Lcd Technologies, Ltd. | Thin film transistor and method of fabricating the same |
CN1324359C (en) * | 2003-05-28 | 2007-07-04 | 友达光电股份有限公司 | Planar displaying device and producing method thereof |
WO2004107418A1 (en) * | 2003-05-30 | 2004-12-09 | Psk, Inc. | Method for removing photoresist in semiconductor manufacturing process |
CN109920729A (en) * | 2019-03-27 | 2019-06-21 | 合肥鑫晟光电科技有限公司 | A kind of preparation method of display base plate, display device |
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