JPS61281523A - Formation of contact - Google Patents

Formation of contact

Info

Publication number
JPS61281523A
JPS61281523A JP12391885A JP12391885A JPS61281523A JP S61281523 A JPS61281523 A JP S61281523A JP 12391885 A JP12391885 A JP 12391885A JP 12391885 A JP12391885 A JP 12391885A JP S61281523 A JPS61281523 A JP S61281523A
Authority
JP
Japan
Prior art keywords
contact hole
contact
etching
substrate
type region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12391885A
Other languages
Japanese (ja)
Inventor
Tamaki Kuki
九鬼 環
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Gakki Co Ltd
Original Assignee
Nippon Gakki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Gakki Co Ltd filed Critical Nippon Gakki Co Ltd
Priority to JP12391885A priority Critical patent/JPS61281523A/en
Publication of JPS61281523A publication Critical patent/JPS61281523A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the contact by using alkaline system etching liquid as etching liquid when the damage layer on the semiconductor surface after a contact hole has been formed. CONSTITUTION:After an N<+> type region 12 has been formed on the surface of a P-type surface of a semiconductor substrate 10 made by silicon, an insulative film 14 of silicon oxcide, etc. is formed on the surface of the substrate, and a photo-resist layer 16 having a hole corresponding to the desired contact hole is formed on the surface of the insulative film 14. Then, a part of the insulative film 14 is selectively removed with reactive ion etching to form a contact hole 14A, and to expose a part of the N<+> type region 12. After the photo-resist film 16 has been removed, the exposed surface of the N<+> region 12 is etch-removed with alkaline system etching liquid. Patterning is done by coating the surface of the substrate with electrode metal of Al or Al alloy to form an electrode layer 18 ohmically contacting with the N<+> type region 12 through the contact hole 14A, thereby providing highly reliable contact with low resistance.

Description

【発明の詳細な説明】 〔産業上の利用分野〕       。[Detailed description of the invention] [Industrial application field].

この発明は、LSI等の半専体装tp#細電極形成に用
いるに好適な改良されたコンタクト形成法に関するもの
である。
The present invention relates to an improved contact forming method suitable for forming semi-dedicated tp# fine electrodes in LSIs and the like.

〔発明の概要〕[Summary of the invention]

この発叩け1.反応性イオンエツチングによりコンタク
ト孔を形成した後、コンタクト孔内の半導体表面にイオ
ン衝撃により生じたダメージ層をアルカリ系エッチ液で
エッチ除去することによりコンタクト抵抗の低減を図っ
たものである。150、〔従来の技術〕  ・    
    ・  ・従来、L@■等の微細電極形成に際し
てドラ、イエツテングによってマンタクト孔を形成する
ことは知られている。そして、このような場合に用いら
れるドライエツチングとしては、反応性イオンエツチン
グが主流となっている。これは、反応性イオンエツチン
グがラジカル(化学的)トイ、オど(物理的)両方のフ
ァクターをそなえているため、材料選択性に優れ且つ方
向性のあるエツチングが可能であり1、微細加工に通し
ているからである。
Hit this shot 1. After a contact hole is formed by reactive ion etching, a damaged layer generated by ion bombardment on the semiconductor surface within the contact hole is etched away using an alkaline etchant, thereby reducing contact resistance. 150, [Conventional technology] ・
・ ・It has been known to form man-tact holes by using a driver or a punch when forming fine electrodes such as L@■. Reactive ion etching is the mainstream dry etching used in such cases. This is because reactive ion etching has both radical (chemical) and oxidative (physical) factors, making it possible to perform directional etching with excellent material selectivity. This is because it is passing through.

しかし、反応性イオンエツチングには、次のような問題
点もある。
However, reactive ion etching also has the following problems.

、(1)イオン衝撃により8i 等の半導体表面に%檀
の結晶欠陥が生ずる。
, (1) Ion bombardment causes %Dan crystal defects on the surface of semiconductors such as 8i.

(3)反応ガスとチャン・々材1.電極あるいけレジス
トとの反応の結果、C,F、O等の不純物が生じ、半導
体表面を、汚染する。
(3) Reactive gas and chamber materials 1. As a result of the reaction between the electrode and the resist, impurities such as C, F, and O are generated and contaminate the semiconductor surface.

(4)ガスプラズマによね生ずる紫外線のために照射損
傷が生ずる。
(4) Irradiation damage occurs due to the ultraviolet rays generated by the gas plasma.

これらの欠陥、汚染、損傷等は、デ・5イスの電気的特
性に影響を及ばし、例えば電極拳配線におけるコンタク
ト抵抗の増大、PNQ合におけるリーク電流の増大等を
招く。
These defects, contamination, damage, etc. affect the electrical characteristics of the device, and cause, for example, an increase in contact resistance in the electrode interconnection, an increase in leakage current in the PNQ connection, and the like.

このための対策として、反応性イオンエツチングにより
コンタクト孔を形成した後、コンタクト孔内の半導体表
面のダメージ層を低ダメージのプラズマエツチング(例
えばCP4 +02系又はC12系のガスを用いた等方
性ラジカルエツチング)によってエッチ除去する方法が
知られている。
As a countermeasure for this, after forming a contact hole by reactive ion etching, the damaged layer on the semiconductor surface inside the contact hole is etched by low-damage plasma etching (for example, isotropic radical etching using CP4+02-based or C12-based gas). A method of etching is known.

〔発明が解決しようとする問題点〕 上記のように半導体表面のダメージ層をプラズマエッチ
する方法によると、短時間処理のために時凹設定、がク
リティカルで、再現性が良好でない。
[Problems to be Solved by the Invention] According to the method of plasma etching the damaged layer on the semiconductor surface as described above, the time-depression setting is critical due to the short processing time, and the reproducibility is not good.

”特に0.3’[μm] 以下の浅いPN接合の場合に
は、過剰エッチのためにコンタクト抵抗や接合リーク電
流が増大することがあり、エツチング制御が困難である
``Especially in the case of shallow PN junctions of 0.3' [μm] or less, contact resistance and junction leakage current may increase due to excessive etching, making etching control difficult.

別の方法として、HF−HNO3系のエッチ液で半導体
表面のダメージ層を除去することも考えられるが、この
方法では、反応が急激で、エツチング後の半導体表面に
スティン膜が生ずる不部会がある。
Another method is to remove the damaged layer on the semiconductor surface using an HF-HNO3-based etchant, but with this method, the reaction is rapid and a stain film may be formed on the semiconductor surface after etching. .

〔問題点を解決するための手段〕[Means for solving problems]

この発明は−・′上記した問題点を解決するためになさ
れたものであって、コンタクト孔形成後に半導体表面の
ダメージ層を除去する際のエッチ液としてアルカリ系の
エッチ液を用いることを特徴とするものである。
This invention was made to solve the above-mentioned problems, and is characterized by using an alkaline etchant as an etchant when removing the damaged layer on the semiconductor surface after contact hole formation. It is something to do.

〔作用〕[Effect]

この発明の方法によると、アルカリ系のエッチ液′1に
:用いるので、反応が緩慢で、エツチング制御が容易で
あり、スティン膜を生ずるとともない。
According to the method of the present invention, since an alkaline etchant '1 is used, the reaction is slow, the etching can be easily controlled, and a stain film is not formed.

従って、ダメージ層をエッチ除去したととろに電極層又
は配線層を電気的に接触させる“と;良好なコシタクト
が得られる。  □ ゛ 〔実施例)    ”  ”’=  ”   ’第1図
乃至第3図は、この発明の一実施例による配線形成工程
!示すもので、各々の図番に対応する■程11)〜(3
)7¥:順次に説明するエ ゛  −′・(1)例えば
シリコンからなる半導体基板10のP型領域表面にN+
型領領域12形成した後、基板上面には例えばCvD(
ケミカル・4ニノセー−デボジシ白ン)法によりシリコ
ジオキサイド等め絶縁膜14ヲ形成する。そして、絶縁
膜14の表面に周知の方法により所望のコンタクト孔に
対応する孔を有量るホトレジスト膜16を形成した後、
ホトレジスト膜16’&マスクとして反応性イオジエッ
チングケ実施して絶縁膜14の一部を選択的に除去する
ことによりコンタクト孔14Aを形成し、゛N+型領域
12の一部を露呈させる。     − ′(2)次に、適宜の方法によりホトレジスト膜16を
除去した後、アルカリ系のエッチ液として例えばコリン
(HOCH2CH2N (cI(3)a )+ o)(
−の1%〜2%の水溶液を用い且つ絶縁膜14ヲマスク
としてN+型領領域12露呈表面を約150λ〜300
人の深さまでエッチ除去する。この結果、前述の反応性
イオンエツチングによるダメージ層はtlに完全に除去
される。なお、このアルカリ系ウェットエツチングでは
絶縁gi(14の膜減りは殆どない。
Therefore, if the damaged layer is removed by etching and the electrode layer or wiring layer is brought into electrical contact with the electrode layer, a good coherence tact can be obtained. Here is a wiring forming process according to an embodiment of the present invention! 11) to (3) corresponding to each figure number.
) 7 yen: Explanation will be made in sequence ゛ -'・(1) For example, N+
After forming the mold region 12, the upper surface of the substrate is coated with, for example, CvD (
An insulating film 14 made of silicon dioxide or the like is formed by a chemical deposition method. After forming a photoresist film 16 having a large number of holes corresponding to desired contact holes on the surface of the insulating film 14 by a well-known method,
A contact hole 14A is formed by selectively removing a portion of the insulating film 14 by performing reactive ion etching using the photoresist film 16' and a mask, and exposing a portion of the N+ type region 12. -'(2) Next, after removing the photoresist film 16 by an appropriate method, an alkaline etchant such as choline (HOCH2CH2N (cI(3)a)+o)(
Using a 1% to 2% aqueous solution of - and using the insulating film 14 as a mask, the exposed surface of the N
Etches to the depths of a person. As a result, the damaged layer caused by the aforementioned reactive ion etching is completely removed at tl. It should be noted that in this alkaline wet etching, there is almost no reduction in the film of the insulation gi (14).

(3)こめ後は、基板上面にAl又はA1合金等の電極
金属を蒸着法、スパッタ法等の任意の方法で被着してホ
トリソグラフィ技術によりノゼターニングすることに′
よりコンタクト孔14A’%−介して・N+型領領域1
2オー・ミック接触する電極層18を形成する。
(3) After heating, an electrode metal such as Al or A1 alloy is deposited on the top surface of the substrate by any method such as vapor deposition or sputtering, and nose turning is performed using photolithography.
Through the contact hole 14A'%-N+ type region 1
An electrode layer 18 making 2-ohm contact is formed.

上記実施例では、基板表面での電極形成についてこの発
明を説明したが、この発明は、例えば多層配線構造にお
いてポリシリコン層にコンタクト孔を介して他の配線層
を電気接触させるような場合にも応用可能である。 □
       。
In the above embodiments, the present invention has been described with respect to the formation of electrodes on the surface of a substrate, but the present invention can also be applied to the case where, for example, in a multilayer wiring structure, another wiring layer is brought into electrical contact with a polysilicon layer through a contact hole. It is applicable. □
.

〔発明の効果〕′ 以上のように、この発明によれば、反応性イオンエッチ
ングによるダメージ層をアルカリ系のエッチ液でエッチ
除去するようにしたので、次のような優れた作用効果が
得られる。
[Effects of the Invention]' As described above, according to the present invention, the damaged layer caused by reactive ion etching is removed by etching with an alkaline etchant, so the following excellent effects can be obtained. .

(1)プラズマエツチングでは多少なりともダメージを
伴うが、アルカリ系ゆエツトエッチでは全くダメージが
ない。
(1) Plasma etching causes some damage, but alkaline wet etching causes no damage at all.

(2)プラズマエツチングやHF−HNO3系のウェッ
トエツチングに比べてエツチング制御が容易で、再現性
が良好である。
(2) Etching control is easier and reproducibility is better than plasma etching or HF-HNO3 wet etching.

f31HF4NOB系のウェットエツチングのようにエ
ツチング後の半導体表面にスティン膜が生ずることがな
い。このことは、ダメージ層の除去と相俟って低抵抗且
つ高信頼のコンタクトケ得るのを可能にする。
Unlike f31HF4NOB wet etching, no stain film is formed on the semiconductor surface after etching. This, together with the removal of the damaged layer, makes it possible to obtain a low resistance and highly reliable contact.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第3図は、この発明の一実施例による電極形
成工程を示す基板断面図である。 10・・・半導体基板、12・・・N+型領領域14・
・・絶縁膜、16・・・ホトレジスト膜、18・・・電
極層。 第 1 図 (反Jそセtイオ〉エヅチ)第 2 図 
(アル方す糸九・/トエヅチ) ・第3図(/1.極形
人)
1 to 3 are cross-sectional views of a substrate showing an electrode forming process according to an embodiment of the present invention. 10... Semiconductor substrate, 12... N+ type region 14.
...Insulating film, 16... Photoresist film, 18... Electrode layer. Figure 1 (Anti J Sosetio〉Ezuchi) Figure 2
(Aru Hosu Itoku/Toezuchi) ・Figure 3 (/1. Polar figure)

Claims (1)

【特許請求の範囲】 (a)半導体表面をおおう絶縁膜の一部を反応性イオン
エッチングにより選択的に除去してコンタクト孔を形成
する工程と、 (b)前記コンタクト孔内の半導体表面部分をアルカリ
系のエッチ液に接触させて前記反応性イオンエッチング
によるダメージ層を除去する工程と、(c)前記ダメー
ジ層が除去された半導体表面部分に前記コンタクト孔を
介して導電層を電気的に接触させる工程と を含むコンタクト形成法。
[Claims] (a) forming a contact hole by selectively removing a part of the insulating film covering the semiconductor surface by reactive ion etching; (b) removing a portion of the semiconductor surface within the contact hole; (c) electrically contacting the conductive layer with the semiconductor surface portion from which the damaged layer has been removed through the contact hole; A contact forming method including a step of
JP12391885A 1985-06-07 1985-06-07 Formation of contact Pending JPS61281523A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12391885A JPS61281523A (en) 1985-06-07 1985-06-07 Formation of contact

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12391885A JPS61281523A (en) 1985-06-07 1985-06-07 Formation of contact

Publications (1)

Publication Number Publication Date
JPS61281523A true JPS61281523A (en) 1986-12-11

Family

ID=14872562

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12391885A Pending JPS61281523A (en) 1985-06-07 1985-06-07 Formation of contact

Country Status (1)

Country Link
JP (1) JPS61281523A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01212451A (en) * 1988-02-20 1989-08-25 Sony Corp Manufacture of semiconductor device
JPH0210856A (en) * 1988-06-29 1990-01-16 Matsushita Electron Corp Manufacture of semiconductor device
JPH06216064A (en) * 1993-01-18 1994-08-05 Nec Corp Al contact structure and manufacture thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5768033A (en) * 1980-10-16 1982-04-26 Toshiba Corp Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5768033A (en) * 1980-10-16 1982-04-26 Toshiba Corp Manufacture of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01212451A (en) * 1988-02-20 1989-08-25 Sony Corp Manufacture of semiconductor device
JPH0210856A (en) * 1988-06-29 1990-01-16 Matsushita Electron Corp Manufacture of semiconductor device
JPH06216064A (en) * 1993-01-18 1994-08-05 Nec Corp Al contact structure and manufacture thereof

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