TWI251265B - Method for removing photoresist in semiconductor manufacturing process - Google Patents

Method for removing photoresist in semiconductor manufacturing process Download PDF

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TWI251265B
TWI251265B TW93115506A TW93115506A TWI251265B TW I251265 B TWI251265 B TW I251265B TW 93115506 A TW93115506 A TW 93115506A TW 93115506 A TW93115506 A TW 93115506A TW I251265 B TWI251265 B TW I251265B
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photoresist
stage
semiconductor
ashing
patent application
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TW93115506A
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TW200426917A (en
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Sammy Chu
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Psk Inc
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    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26Processing photosensitive materials; Apparatus therefor
    • G03F7/42Stripping or agents therefor
    • G03F7/427Stripping or agents therefor using plasma means only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • H01L21/31133Etching organic layers by chemical means
    • H01L21/31138Etching organic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Plasma & Fusion (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Drying Of Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

The present invention discloses a method for removing photoresist in the semiconductor manufacturing process, which employs the plasma to form the mixture gas containing hydrogen (H2) for ashing process to remove the photoresist. Moreover, the method for removing photoresist in semiconductor manufacturing process not only employs the plasma to form the mixture gas containing hydrogen for ashing process to remove the photoresist, but also eliminates the forming of SiO2 film to reduce the silicon consumption, and avoids the occurrence of popping. The present invention cannot only thoroughly clear the residual dopant of DUV (deep ultra violet) photoresist with high dose implantation, but also improve the effect of ashing process.

Description

1251265 __案號 93115506 五、發明說明(1)1251265 __Case No. 93115506 V. Description of invention (1)

【發明所屬之技術領域】 j發=有關一種半導體製程中去除光阻的方 二二Τίΐ等it體形成含氫氣(u的混合氣體,進 4丁火化(Ashing)製私從而去除光阻。 【先前技術】 半導體製程之一的光餘微爭、、扣r . 製程是經由五個階段所構成,=去(b Ph0t0 LUhograPhy) 旋塗(spin coating)光i , 3二=段是在半導體基板上 段是以選擇性的曝露上述光_ =成光阻層的階段;第二階 段;第三階段是為了在半導二的曝光(Exposure)階 _ (Photoresist Pattern) ,:土板上幵,成光阻圖案 (Deve 1 op)的階段;第四,曝光的光阻層顯影 體基板部位進行蝕刻(E t =·又是對沒有被光阻覆蓋的半導 五階段是清除在蝕刻或植^ lng)或者植入雜質的階段;第 案的灰化製程。 雜質階段時用於遮罩的光阻圖 在上述該半導體製造 形成金屬配線層之製程,二中’灰化階段結束後,進入 線以及對晶片與外界之門^而形成連接晶片上的各元件配 屬薄膜。 曰起結合墊(Bond Pad)作用的金 其中灰化是待蝕刻製 去除無用光阻的製程, 或 於蝕刻光阻底部基板上’的屬於蝕刻製程的一種。光阻是用 離子時起遮罩作用的从新圖案’或者在 的物質. 該上述灰化製程中所 γ所使用的是等 離子植入製程結束後 的一種。光 基板外露部位植入 用以[Technical field to which the invention pertains] j-fabrication is related to the removal of a photoresist in a semiconductor process, such as a square gas, a gas mixture containing hydrogen (u, a gas mixture, and a smoldering (Ashing) process to remove the photoresist. Prior art] One of the semiconductor processes is a small amount of light, and the process is formed by five stages, = (b Ph0t0 LUhograPhy) spin coating light i, 3 = segment is on the semiconductor substrate The upper stage is a stage of selectively exposing the above-mentioned light _ = into a photoresist layer; the second stage; the third stage is for Exposure step _ (Photoresist Pattern), on the earth plate, The stage of the photoresist pattern (Deve 1 op); fourth, the exposed photoresist layer is etched on the substrate portion of the photoresist layer (E t =· is again a half-guided stage that is not covered by the photoresist is removed in etching or planting ^ Lng) or the stage of implanting impurities; the ashing process of the first case. The photoresist pattern used for the mask in the impurity stage is in the process of forming the metal wiring layer by the semiconductor manufacturing described above, and after the end of the 'ashing stage, the line enters the line. And the door to the wafer and the outside world The components on the bonded wafer are assigned to the film. The gold which acts as a bond pad is a process in which the ash is to be etched to remove the useless photoresist, or on the underlying substrate of the etched photoresist. A photoresist is a new pattern or a substance that acts as a mask when ions are used. In the above ashing process, γ is used after the end of the plasma implantation process. The exposed portion of the optical substrate is implanted.

籬手體,而反應氣體Handle body, and reaction gas

第5頁 1251265 _案號93115506_、年月 a 修正_ 五、發明說明(2) 是氧氣(0 2> 。因此,該光阻去除製程是讓光阻和氧氣起反 應的氧化過程,氧化是一種燒化過程,因此,可稱之為灰 化(Ash i ng)製程。如上所述,我們把灰化製程中所需的 設備叫作灰化器(Asher)。 近年來,隨著半導體製造技術要求設備集成度高、速 度快,晶片技術也趨於細致化。隨著晶片的細致技術,晶 片的主成分即矽,在經過多個製程時逐漸被消耗而形成了 問題。Page 5 1251265 _ Case No. 93115506_, Year a Correct _ V. Invention Description (2) is oxygen (0 2 > Therefore, the photoresist removal process is an oxidation process that allows photoresist and oxygen to react, oxidation is a kind The burning process, therefore, can be referred to as the Ashing process. As mentioned above, we refer to the equipment required in the ashing process as Asher. In recent years, with semiconductor manufacturing technology The device is required to be highly integrated and fast, and the wafer technology is also becoming more and more detailed. With the meticulous technology of the wafer, the main component of the wafer is entangled, which is gradually consumed when it passes through multiple processes, which poses a problem.

尤其在灰化製程中使用氧氣來形成等離子體時,晶片 的部分表面與上述技術中之氧氣起作用而形成氧化膜。如 上所述,當矽表面形成氧化膜層後,不僅需要製造作為日 後進行淺接面技術(S h a 1 1 〇 w j u n c t i ο η)的元件,而且起 電極作用的摻雜多晶石夕(d 〇 p e d ρ ο 1 y - s i 1 i c ο η)大量消耗 亦造成了問題。 目前的光阻灰化製程中,在晶片上植入高劑量離子 (High Dose Implantation)後容易發生爆裂現象,為了 減少上述爆裂現象發生,把製程溫度設為低溫,或者在結 束南劑S:離子植入(High Dose Implantation)製程後進 行加固(Pin-up),但仍無法徹底解決爆裂問題。Particularly when oxygen is used to form a plasma in the ashing process, part of the surface of the wafer acts with oxygen in the above technique to form an oxide film. As described above, when the oxide film layer is formed on the surface of the crucible, it is necessary to manufacture not only an element which is a shallow junction technique (S ha 1 1 〇wjuncti ο η) but also a doped polycrystal as an electrode (d 〇 Ped ρ ο 1 y - si 1 ic ο η) A lot of consumption also caused problems. In the current photoresist ashing process, a high-dose ion implantation (High Dose Implantation) is likely to occur after the wafer is implanted. In order to reduce the occurrence of the above-mentioned burst phenomenon, the process temperature is set to a low temperature, or at the end of the south agent S: ion After the High Dose Implantation process, the pin-up is performed, but the burst problem cannot be completely solved.

在高集成矽上,由於波長43 6nm的G線(G-1 ine)和波 長36 5nm的I線(1-1 ine)的波長過長,基板可限定的 ^ 過大亦成了問題。為了進一步精密作業,建議使用波長^ 2 4 8nm或1 93nm的植入了高劑量離子的DUV和X線。彳' 由於現有之I線(I - 1 i n e)光阻钱刻製程存在分子大 1251265 案號 93115506 _η 曰 修正 五、發明說明(3) 、黏度高的問題,在高集成矽上使用植入高劑量離子的DUV (Deep Ultra Violet)光阻,代替 I線(1-1 ine)光阻。 但上述的植入高劑量離子的DUV光阻餘刻技術,無法使利用 瑪有氧氣的灰化製程徹底清除殘留物質。 【發明内容】 本發明的主要目的係提供一種半導體製程中去除光阻 的方法,其利用等離子體形成含氫氣(Η 0的混合氣體,進 行灰化(Ashing)製程,從而去除光阻。 本發明的另一目的是提供一種半導體製程中去除光阻 的方法,以減少矽氧化膜的形成,降低耗矽量,避免爆裂 現象發生;徹底清除植入了高劑量離子的DUV光阻的殘餘物 質。 本發明的又一目的是提供一種半導體製程中除去光阻 的方法,從而提升灰化製程的功效。 為達成上述發明之目的,本發明係在去除半導體構件 上的光阻的灰化製程中採用等離子體,形成含氫氣(Η 2)的混 合氣體。本發明適用於所有光阻灰化製程,尤其對植入高 劑量離子(High Dose Ion Implantation)的石夕基板十分 有效。 茲為使 貴審查委員對本發明之結構、特徵及所達成 之功效更有進一步之瞭解與認識,謹佐以較佳之實施例圖 友配合詳細之說明,說明如後: 【實施方式】 本發明係作為半導體製程中去除光阻的方法,其特徵On the highly integrated germanium, since the wavelength of the G line (G-1 ine) having a wavelength of 43 6 nm and the I line (1-1 ine) having a wavelength of 36 5 nm is too long, the substrate can be too large to be defined. For further precision work, it is recommended to use DUV and X-rays with high doses of ions at wavelengths of 248 nm or 193 nm.彳' Due to the existing I-line (I - 1 ine) photoresist process, there is a large molecular number of 1251225. Case No. 93115506 _η 曰 Amendment 5, invention description (3), high viscosity, use high implantation on high-integration Dionic (Deep Ultra Violet) photoresist, instead of I-line (1-1 ine) photoresist. However, the above-mentioned DUV photoresist remnant technique implanted with high-dose ions cannot completely remove residual substances by using the ashing process with oxygen. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for removing photoresist in a semiconductor process, which uses a plasma to form a mixed gas containing hydrogen gas (Η 0, and performs an ashing process to remove photoresist). Another object is to provide a method for removing photoresist in a semiconductor process to reduce the formation of a tantalum oxide film, reduce the amount of ruthenium, avoid bursting, and completely remove residual materials of DUV photoresist implanted with high dose ions. It is still another object of the present invention to provide a method for removing photoresist in a semiconductor process, thereby improving the efficiency of the ashing process. To achieve the above object, the present invention is applied to an ashing process for removing photoresist on a semiconductor member. The plasma forms a mixed gas containing hydrogen (Η 2). The present invention is applicable to all photoresist ashing processes, especially for the high-dose Ion Implantation, which is very effective for reviewing the high-dose Ion Implantation. Members have further understanding and understanding of the structure, characteristics and effects of the present invention. The embodiment described in detail with FIG Friends, as described later: [Embodiment The present invention is a method of removing the photoresist as the semiconductor manufacturing process, characterized in

第7頁 1251265Page 7 1251265

是由五個階段所構成,即第一階段是在半導體基板上旋塗 先阻,形成光阻層的階段;第二階段是選擇性的曝露光阻 層的曝光(Exposure)階段;第三階段是為了形成光阻圖 案,讓曝露的光阻層顯影(Deve 1 op)的階段;第四階段是 對沒有被上述光阻覆蓋的半導體基板部位進行蝕刻 (E t ch i ng)或者植入雜質的階段;第五階段是清除在上述 蝕刻或植入雜質階段時用於遮罩的光阻圖案的灰化製程; 而上述灰化製程是利用等離子體形成含氫氣(Η 2>的混合氣 體,防止在高溫下發生爆裂現象,並在抑制微粒 (Part icle)產生狀態下清除光阻圖案,藉以解決上述課 題0 如上所述’在利用等離子體形成含氫氣的混合氣體時 ,最大限度地減少氧化膜生成、降低耗矽量。 本發明作為半導體製程中去除光阻的方法,其特徵是 根據咼劑量離子植入(High Dose ion Implantation)模 式製作上述半導體基板,從而解決上述課題。 本發明作為半導體製程中去除光阻的方法,其特徵是 上述光阻含有深紫外線(DUV: Deep Ultra Violet),從 而解決上述課題。 本發明作為半導體製程中去除光阻的方法,其特徵是 上述氫(Η 2)跟氮(N 2)或者氦(He)混合成另一種混合氣 體,從而解決上述課題。 ~ 本發明作為半導體製程中去除光阻的方法,其特徵是 上述氫氣(Η Ο占氣體總量的2 %〜1 〇 〇 % (體積百分比),你It consists of five stages, that is, the first stage is the stage of spin coating on the semiconductor substrate to form the photoresist layer; the second stage is the exposure phase of the selective exposure photoresist layer; the third stage In order to form a photoresist pattern, the exposed photoresist layer is developed (Deve 1 op); the fourth stage is to etch the semiconductor substrate portion not covered by the photoresist or implant impurities. The fifth stage is to remove the ashing process for the photoresist pattern used for the mask during the etching or implanting impurity stage; and the ashing process is to form a hydrogen-containing (Η 2 > mixed gas by using a plasma, Preventing the occurrence of cracking at high temperatures and removing the photoresist pattern in the state of suppressing the generation of particles, thereby solving the above problem. 0 As described above, when the mixed gas containing hydrogen is formed by plasma, the oxidation is minimized. Membrane generation and reduction of consumption. The present invention is a method for removing photoresist in a semiconductor process, which is characterized by a high dose ion implantation (High Dose ion Implantation) mode. The above-described problem is solved by the above-described semiconductor substrate. The present invention is a method for removing photoresist in a semiconductor process, characterized in that the photoresist contains deep ultraviolet rays (DUV) to solve the above problems. A method for removing photoresist, characterized in that the hydrogen (Η 2) is mixed with nitrogen (N 2 ) or helium (He) to form another mixed gas, thereby solving the above problems. ~ The present invention as a method for removing photoresist in a semiconductor process , which is characterized by the above hydrogen (Η Ο Ο 2% to 1 〇〇% (volume percentage) of the total amount of gas, you

第8頁 1251265 案號 93115506 Λ_ 曰 修正 五、發明說明(5) 而解決上述課題。 本發明作為去阻光阻的方法,其特徵是上述灰化製程 温度在1 0 0°C〜2 0 0°C,從而解決上述課題。 本發明的另一實施例是半導體製程中去除光阻的方法 其特徵是由五個階段構成,即第一階段是在半導體基板 上旋塗光阻,形成光阻層的階段;第二階段是選擇性的曝 露光阻層的曝光(Exposure)階段;第三階段是為了形成 光阻圖案,讓曝露的光阻層顯影(D e ve 1 οp)的階段;第四 階段是對沒有被上述光阻覆蓋的半導體基板部位進行蝕刻 :E t c h i n g)或者植入雜質的階段;第五階段是清除在上述 蝕刻或植入雜質階段時用於遮罩的光阻圖案的灰化製程; 而上述灰化製程是利用等離子體形成含氳(Η 〇的混合氣體 或者氮氣(NH a),防止在高溫下發生爆裂現象,並在抑制 微粒產生的狀態下清除光阻圖案,從而解決上述課題。 透過參見附圖以及相關實施例進行詳細說明。表1是對 整個實施例的總結表。 【表1】Page 8 1251265 Case No. 93115506 Λ _ 曰 Amendment V. Invention Note (5) to solve the above problems. The invention is a method for removing photoresist, characterized in that the ashing process temperature is in the range of 100 ° C to 200 ° C, thereby solving the above problems. Another embodiment of the present invention is a method for removing photoresist in a semiconductor process characterized by five stages, that is, a first stage is a step of spin coating a photoresist on a semiconductor substrate to form a photoresist layer; the second stage is Selective exposure to the exposure phase of the photoresist layer; the third phase is to form a photoresist pattern to develop the exposed photoresist layer (D e ve 1 οp); the fourth phase is to be not exposed to the above light Blocking the covered semiconductor substrate portion for etching: Etching) or implanting impurities; the fifth stage is to remove the ashing process for the photoresist pattern used for the mask during the etching or implanting impurity stage; The process is to use a plasma to form a mixed gas containing ruthenium or ruthenium (NH a) to prevent the occurrence of a burst at a high temperature, and to remove the photoresist pattern in a state where the generation of particles is suppressed, thereby solving the above problem. The drawings and related embodiments are described in detail. Table 1 is a summary table for the entire embodiment. [Table 1]

第9頁 1251265 案號 93115506 Λ_ 曰 修正 直、發明說明(6)Page 9 1251265 Case No. 93115506 Λ_ 修正 Correction Straight, invention description (6)

No. 02 n2 h2n2 製程 ( ( ( 溫度 seem seem seem re ) :)! i ) ) :製程時 氧化膜 間 濃度 :(秒) (A) TE Μ 照 00 70 80 2 75 7 ο 00 8 50 28 第2圖 有關上述表1的簡要說明如下:製程Α是在2 5 0°C的製程 溫度下,係為習用技術製程的灰化法中的7 〇 〇 〇 s c c m的氧氣 和8 0 0 seem的氮氣進行75秒灰化後,用穿透式電子顯微鏡 測量氧化膜厚度,其結果如第1圖所示為1 7 A。 製程B是本發明實施例,在2 5 0°C下對8 0 0 0 seem的H2N2 氣體進行2 8 5秒灰化後,用穿透式電子顯微鏡測量氧化膜厚No. 02 n2 h2n2 Process (( (temperature seem seem seem re ) :)! i ) ) : Oxidation film concentration during the process: (seconds) (A) TE Μ Photo 00 70 80 2 75 7 ο 00 8 50 28 2 The following is a brief description of Table 1 below: Process Α is at a process temperature of 250 ° C, which is 7 〇〇〇 sccm of oxygen and 80 seem of nitrogen in the ashing process of the conventional process. After the ashing was performed for 75 seconds, the thickness of the oxide film was measured by a transmission electron microscope, and the result was 1 7 A as shown in Fig. 1. Process B is an embodiment of the present invention, and the oxidized film thickness is measured by a transmission electron microscope after ashing the H2N2 gas of 800 seeming at 205 ° C for 285 seconds.

第10頁 1251265 93iiRFinfi 修正 曰 五、發明說明(?) - 度 ς、结果如第2圖所示,其厚度達到無法測量的程度。 -2 JB 在 | 述表1條° 1程室(process chamber)的可視窗觀察根據上 二坊件進行的製程,其結果是習用技術製程即製程A中Page 10 1251265 93iiRFinfi Correction 曰 V. Inventive Note (?) - Degree ς The result is as shown in Figure 2, and its thickness is unmeasurable. -2 JB in | Table 1 ° 1 process room (process chamber) window observation according to the process of the second square, the result is the conventional technology process that is process A

{jj J a、々女;衣現象,但在本發明實施例,即使用氫氣的製程ί ϊΐ出現爆裂現象。 ‘表2】 製程c 壓力 (Torr 〇2 h2n2 scan 程度°c 程間秒 ΠΟΟΟ I 1900 150 製裎D , 150 8000 Ϊ Ϊ表2是在使用DUV (植入高劑量離子)光阻的晶片 j f化.技術後,檢查的殘留物。 件如2 ^ C係為習用技術去除現有光阻的製程’上述製程條 ]cj/所示’壓力為2托耳,氧氣為1 7 0 0 0 Sccm,氮氣為 / = 7而製程溫度為2 5 0°C,製程時間為150秒。 2所示' If ^為本發明去除光阻的製程’上述製程條件如表 seem,而製程為 w2^ 氧氣為 8 0 0 0 sccm,Η A 為 8 0 0 0 依據上f度為15 0°c,製程時間為1 5 0秒。 多雜^,作Ϊ條件去除光阻’其結果為製程C結束後留有很 、換句;^程^敗底清除了所有殘留物質。 在本發明中在以氫氣為主的製程上,利用 1251265 _案號 93115506_年月日__ 五、發明說明(8) 除氫外的其他氣體,如上述表2所示的氮(N 0 、氦(He)混 合物去除光阻時,可以徹底清除光阻殘留物;或者利用氨 氫化合物去除光阻時,亦可以徹底清除殘留物。 另者,在本發明的製程中,把回應(製程)溫度設為 1 0 0〜2 0 0°C時,也可以達到徹底清除殘留物質的效果。 如上所述,在光阻灰化製程中使用本發明中的相關製{jj J a, prostitute; clothing phenomenon, but in the embodiment of the invention, that is, the process using hydrogen gas bursts. 'Table 2】 Process c Pressure (Torr 〇2 h2n2 scan degree °c Interval ΠΟΟΟ I 1900 150 裎 D , 150 8000 Ϊ Ϊ Table 2 is the use of DUV (implanted high dose ion) photoresist chip After the technology, check the residue. Parts such as 2 ^ C is the process of removing the existing photoresist from the conventional technology 'The above process bar' cj / shown 'pressure is 2 Torr, oxygen is 1 700 0.02 cm, nitrogen The process temperature is /50 and the process time is 150 seconds. 2 If 'If ^ is the process for removing photoresist in the present invention', the above process conditions are as shown, and the process is w2^ oxygen is 8 0 0 0 sccm, Η A is 8 0 0 0 According to the upper f-degree is 15 0 °c, the process time is 150 seconds. More than ^, as a condition to remove the photoresist', the result is left after the end of process C In other words, in the process of the hydrogen-based process, the use of 1,251,265 Other gases, such as the nitrogen (N 0 , 氦 (He) mixture shown in Table 2 above, can remove the photoresist residue completely when removing the photoresist; or use ammonia When the hydrogen compound is removed from the photoresist, the residue can be completely removed. In addition, in the process of the present invention, when the response (process temperature) is set to 1 0 0 to 2 0 ° C, the residual substance can be completely removed. The effect of the present invention is used in the photoresist ashing process as described above.

第12頁 1251265 _案號 93115506_年月日_修正 、_ 五、發明說明(9) 程,如實施例結果所示,將不會形成氧化膜,故無需製造 曰後需要進行淺接的元件,還能防止起電極作用的摻雜多 晶石夕(doped poly-silicon)大量損耗。 在植入高劑量離子(High Dose Ion Implantation) 後去除光阻的灰化製程上,使用本發明的方法,即使在 2 0 0°C以上的製程溫度下也不產生爆裂現象,且可達到抑制 微粒產生,可以提升半導體的製造生產能力。 在高集成矽必須使用的植入高劑量離子的DUV去除光阻 製程上,使用本發明中氫氣為主的化合物或者在低溫下使 用混合物時,可以徹底清除植入高劑量離子的D U V光刻膠殘Page 12 1251265 _ Case No. 93115506_年月日日_Amendment, _ V. Inventive Note (9) Process, as shown in the results of the examples, no oxide film will be formed, so there is no need to fabricate components that need to be shallow after fabrication. It also prevents a large amount of doped poly-silicon loss due to the action of the electrodes. On the ashing process for removing photoresist after implantation of high-dose Ion Implantation, the method of the present invention does not cause bursting even at a process temperature of above 200 ° C, and can be suppressed. The generation of particles can enhance the manufacturing capacity of semiconductors. The DUV photoresist implanted with high dose ions can be completely removed by using the hydrogen-based compound of the present invention or the mixture at a low temperature in a highly integrated DUV-removing photoresist process which must be used for high-input ions. Residual

以上所述者,僅為本發明一較佳實施例而已,並非用 來限定本發明實施之範圍,故舉凡依本發明申請專利範圍 所述之形狀、構造、特徵及精神所為之均等變化與修飾, 均應包括於本發明之申請專利範圍内。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, so that the shapes, structures, features, and spirits described in the claims of the present invention are equally varied and modified. All should be included in the scope of the patent application of the present invention.

第13頁 1251265 案號 93115506 Λ_η 曰 修正 圖式簡單說明 第1圖係習用技術製程用穿透式電子顯微鏡所拍攝的照片 第2圖係本發明製程用穿透式電子顯微鏡所拍攝的照片。 _ i^· 第14頁Page 13 1251265 Case No. 93115506 Λ_η 曰 Correction Brief description of the drawing Fig. 1 is a photograph taken by a transmission electron microscope with a conventional technique. Fig. 2 is a photograph taken by a transmission electron microscope of the process of the present invention. _ i^· Page 14

Claims (1)

1251265 案號 93115506 Λ_ 曰 修正 六、申請專利範圍 1 · 一種半導體製程 體製程中包括五 ^ 旋塗光阻,形成 曝露光阻層的曝 了形成光阻圖案 的階段;第四階 基板部位進行蝕 ;第五階段是清 屏蔽的光阻圖案 等離子體形成含 發生爆裂現象, 光阻圖案。 2 ·如申請專利範圍 的方法,其中該 High Dose ion 丨·如申請專利範圍 的方法,其中該 Violet)的光阻 4 ·如申請專利範圍 的方法,其中與 、氦(He)其中 ;·如申請專利範圍 製程中去除光阻 總量的2 %〜1 0 0 % 中去除光阻的方法,其方法係在半導 個階段,第一階段是在半導體基板上 光阻層的階段;第二階段是選擇性的 光(Exposure)階段;第三階段是為 ,讓曝光的光阻層顯影(De ve 1 οp) 段是對沒有被上述光阻覆盖的半導體 刻(E t c h i n g)或者植入雜質的階段 除在上述蝕刻或植入雜質階段時用於 的灰化階段;其中該灰化階段係利用 氫(Η Ο的混合氣體,防止在高溫下 並在抑制微粒產生的狀態下達到清除 第1項所述之半導體製程中去除光阻 半導體基板係以高劑量離子植入( Implantation)模式製作而成。 第1項所述之半導體製程中去除光阻 光阻含有深紫外線(D e e p U 11 r a o 第1項所述之半導體製程中去除光阻 該氫氣(Η 2)混合的氣體係氮(N 2) 之一種氣體。 第1 、2 、3或4項中所述之半導體 的方法,其中該氫氣(Η 0量佔氣體 (體積百分比)。1251265 Case No. 93115506 Λ _ 曰 Amendment VI, Patent Application Scope 1 · A semiconductor process consists of a five-coat spin-coating resistor to form a photoresist pattern exposed to the exposed photoresist pattern; the fourth-order substrate portion is etched The fifth stage is to form a photoresist pattern with a photoresist pattern that contains a burst phenomenon and a photoresist pattern. 2) A method as claimed in the scope of the patent, wherein the method of applying the patent range, such as the method of the patent application, wherein the photoresist of the Violet) is as described in the patent application, wherein, and (He); The method for removing photoresist in the range of 2%~1 0 0% of the total amount of photoresist removed in the patent-pending process, the method is in the semi-conducting stage, the first stage is the stage of the photoresist layer on the semiconductor substrate; The stage is a selective exposure phase; the third stage is to develop the exposed photoresist layer (De ve 1 οp) to the semiconductor engraving or implanting impurities not covered by the photoresist The stage of ashing used in addition to the etching or implantation of the impurity stage described above; wherein the ashing stage utilizes a mixed gas of hydrogen (防止 , , , , , , , , , 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第The photoresist removal semiconductor substrate in the semiconductor process described in the above is fabricated by a high-dose ion implantation (Implantation) mode. The photoresist removal process in the semiconductor process described in Item 1 contains deep ultraviolet rays (D). Eep U 11 rao The semiconductor process described in item 1 removes a gas of nitrogen (N 2 ) which is a gas system mixed with hydrogen (Η 2). The semiconductor described in items 1, 2, 3 or 4. The method wherein the hydrogen (the amount of Η 0 accounts for gas (volume percent). 第15頁 1251265 案號 93115506 曰 修正 六、申請專利範圍 3 ·如申請專利 程令去除光 2 0 0〇C。 7 · —種半導體 體製 旋塗 曝露 了形 的階 基板 ;第 遮罩 等離 之一 8 9 10 程中包 光阻, 光阻層 成光阻 段;第 部位進 五階段 的光阻 子體形 者,防 產生的狀態 如申請專利 的方法,其 Dose ion 如申請專利 的方法,其 V i ο 1 e t)的 如申請專如 去除光阻的 氮(、 範圍第1 、2 、3或4項所述之半導體製 阻的方法,其中該灰化製程溫度為1 0 0°C〜 製程中去除光阻的方法,其方法係在半導 括五個階段,第一階段是在半導體基板上 形成光阻層的階段;第二階段是選擇性的 的曝光(Exposure)階段;第三階段是為 圖案,讓曝露的光阻層顯影(Develop) 四階段是對沒有被上述光阻覆蓋的半導體 行#刻(E t c h i n g)或者植入雜質的階段 是清除在上述蝕刻或植入雜質階段時用於 圖案的灰化製程;其中該灰化製程是利用 成含氫(Ηθ混合氣體或氨氣(NHa)中 止在高溫下發生爆裂現象,並在抑制微粒 下達到清除光阻圖案。 範圍第7項所述之半導體製程中去除光阻 中該半導體基板以高劑量離子植入(H i gh Implantation)模式製作而成。 範圍第7項所述之半導體製程中去除光阻 中該光阻為含有深紫外線(D e e p U 11 r a 光阻。 申請專利範圍第7項所述之半導體製程中 方法,其中與該氫氣(H z)混合的氣體係 氦(He)之其中一種氣體。Page 15 1251265 Case No. 93115506 修正 Amendment 6. Patent application scope 3. If the patent application procedure removes light 200 〇C. 7 · A semiconductor system is spin-coated to expose the shape of the step substrate; the first mask is separated by a photoresist in the 8 9 10 process, the photoresist layer is a photoresist segment; the first part is a five-stage photoresist sub-shape The state of the anti-generation is as in the patent application method, the Dose ion as the patent application method, the V i ο 1 et), such as the application for the removal of photoresist nitrogen (, range 1, 2, 3 or 4) The method for semiconductor resistance, wherein the ashing process temperature is 100 ° C ~ the method of removing photoresist in the process, the method is in five stages of semi-conducting, the first stage is to form light on the semiconductor substrate The stage of the resist layer; the second stage is a selective exposure stage; the third stage is a pattern, and the exposed photoresist layer is developed (Develop). The four stages are semiconductor lines not covered by the above-mentioned photoresist. The stage of etching or implanting impurities is to remove the ashing process for patterning during the etching or implanting impurity stage described above; wherein the ashing process utilizes hydrogen-containing (Ηθ mixed gas or ammonia (NHa) Suspension at high temperatures The film bursts and the photoresist pattern is removed under the suppression of the particles. The semiconductor substrate in the semiconductor process described in the scope of the seventh item is fabricated by high-dose ion implantation (H i gh Implantation) mode. The photoresist in the semiconductor process described in item 7 is a deep ultraviolet ray (D eep U 11 ra photoresist). The method in the semiconductor process described in claim 7 wherein the hydrogen gas (H z a gas of the mixed gas system He (He). 第16頁 1251265 _案號93115506_年月日__ 六、申請專利範圍 11 ·如申請專利範圍第7、8 、9或1 0項所述之半導體製 程中去除光阻的方法,其中該氫氣(Η Ο量佔氣體總 量的2 %〜1 0 0 % (體積百分比)。 1 2 ·如申請專利範圍第7 、8 、9或1 0項所述之半導體製 程中去除光阻的方法,其中該灰化製程溫度為1 0 0°C〜 2 0 0〇C 。Page 16 1251265 _ Case No. 93115506_年月日日__ VI. Patent Application No. 11 · A method for removing photoresist in a semiconductor process as described in claim 7, 8, 9, or 10, wherein the hydrogen (Η Ο 占 占 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 · · · · · · · · · · · · · · · · · · · 如 · · 如 如 如 如 如 如The ashing process temperature is from 10 ° C to 2 0 0 〇 C. 第17頁Page 17
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