經濟部中央標準局貝工消費合作社印製 463237 五、發明説明（丨） 發明之領域 本發明乃有關於形成半導體元件之微佈局圖案的方法 ，且更特別的是形成預防反射薄膜以降低佈局圖案非均勻 性及變形的技術，此非均勻性及變形乃由於散亂反射而產 生凹口，或者在元素隔離及接觸成形的曝光程序中振動而 發生的，此乃由均勻的轉換半導體底材上遮罩之佈局圖案 而不管出現在高反射率底材上之散亂反射層的厚度。 相關技術之說明 傳統上形成半導體元件之微佈局圖案的方法在圖1到 3中有詳細的例舉。 圖1和2表示了依照先前技術形成半導體元件之微佈 局圖案之方法的截面視圖。 圖3爲依照先前技術顯示圖2之反射率的圖形。 依照先前技術形成半導體元件之微佈局圖案的方法中 ，如圖1中所描述的，一氧化矽層2及氮化矽薄膜3依序 在半導體底材1上形成β 接著，一光阻層4沉積在氮化矽薄膜3上面β ' 接著，光阻層4使用元素離遮罩(未顒呆出來)由曝光 和顯影方法選擇性的移除以便化成光阻佈局圖案4 β 接著，使用光阻佈局圖案4作爲遮罩將氧化矽層2及 氮化矽薄膜3選擇性的移除直到半導體底材1曝露出來爲 (請先閱讀背面之注意事項再填寫本頁) 装· ,1Τ 本紙張尺度逋用中國國家標準（CNS ) Α4規格（2丨0><297公釐） 463237 經濟部中央標隼局員工消費合作社印聚 B7 五、發明説明（> ) 止，以便形成半導體底材1之表面上的元^隔離區域。 接著，一熱氧化薄膜(未顯示出來)以氧化擴散的方法 在元素隔離區域上形成，因而形成元素隔離薄膜(未顯示出 來）。 在熱氧化薄膜以氧擴散的方法形成最上層之元素隔離 區域時，氮化矽薄膜3的形成是爲了壓抑氧化薄膜在水平 方向的成長。 另外，在曝光的方法中，半導體底材之反射率很高且 當光線的波長縮短時鑄模尺寸則增加了，且作爲元素隔離 之光阻佈局圖案的尺寸cil和d2並不是單一的尺寸(dl尹d2) ，而是佈局圖案的尺寸減少了 0.3/zm，這是因爲光阻佈局 圖案之尺寸乃正比於或度比於分佈在光阻佈局圖案內的曝 光光線的強度。 也就是說，從高反射率之底材所反射的光線完全通過 氧化矽和氮化矽薄膜而沒有被其吸收，且由於在氧化矽薄 膜和氮化矽薄膜之間很小的步階高度差異，光阻之反射率 改變得很大。 因此，假如半導體元件之製造方法如上面所說的方法 加以執行的話，每個單位元件之特性將會改變。 另外，如圖2中所示的，一元素隔離絕緣薄膜12, 一 閘極氧化薄膜13, 一字元線14在半導體底材11之上形成 。接著，氧化矽薄膜15在整個結構之曝光表面上形成以便 使得上半表面平坦化。 接著，一光阻(未顯示出來）乃沉積在整個結構的上表 _ 5 本紙張又度適用中國囷家標隼（CNS ) Α4規格（210Χ297公t ) (請先閱讀背面之注意事項再填寫本頁) 裝. 訂 經濟部中央標準局員工消費合作社印製 4 63 23 7 A7 B7 五、發明説明（巧） 面之上，且使用接觸遮罩(未顯示出來)經由曝光和顯影將光 阻選擇性的移除，以便在氧化矽薄膜15之上形成光阻佈局 圖案(未顯示出來）。 在此，曝光之方法使用365nm和248nm波長的光線來 源加以實施。 接著，上述的曝光光線並未被出現在半導體底材11和 字元線14之間的氧化矽薄膜15所吸收且完全的反射。因 此，其對光阻之反射能力由於氧化矽薄膜15之厚度差異而 有很大的改變，即便氧化矽薄膜只有微米厚度的差異。 接著，使用光阻佈局圖案(未顯示出來)作爲遮罩將氧 化矽薄膜15選擇性的加以移除，以便形成曝露出半導體底 材11和字元線14之第一個和第二個接點孔洞16和17。 在此，如圖3中所示的，氧化矽薄膜在365nm和 248nm的光線下之光學特性中，其對於光阻之反射能力依 照氧化薄膜之厚度而有週期性的大改變。 如此於再次反射能力中的改變產生了接觸孔洞尺寸的 改變，且有時候甚至沒有形成接觸孔洞。 如上面所述的，傳統上形成半導體元件之微佈局圖案 的方法具有下列的問題。 當透明的絕緣薄膜例如氧化矽薄膜或者氮化矽薄膜等 等.·，並不會吸收365nm和248nm之曝光波長之光線，且會 出現在高反射率和光阻之底材間，且其中透明的絕緣薄膜 在底材上具有將近200-700 A之厚度差異時，由於厚度的差 異及0.1-0.5之曝光光線之再次反射能力的差異，會發生加 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝- --0 Α7 Β7 46323 五、發明説明（4 ) 強和破壞性的干涉β (請先閱讀背面之注意事項再填寫本頁) 因此，應該在半導體底材上均勻成形之佈局圖案依照 在底材上的位置而有不平均之成形6 此外，所需之佈局圖案並不會形成，因而使得良率降 低及元件的品質降低，導致高度積體元件難以產生。 發明之槪要 因此，本發明之目的之一即爲了克服上述提到的先前 技術中所遇到的問題，並且在底材上執行佈局圖案程序以 提供一個形成微佈局圖案之方法給高積體化之半導體元件 ，其中的底材具有很高的步階高度差異及很高的反射率， 並使用雙層預防反射薄膜β 本發明之另一個目的是要提供一個形成半導體元件之 微佈局圖案之方法以改善半導體元件之特性及良率》 經濟部中央標準局貝工消費合作社印裝 爲了要達到本發明這些優點及其它的優點，形成半導 體元件之微佈局圖案之方法包含的步驟有：提供步階高度 差異之半導體底材，在曝光波長中半導體底材之上形成透 明薄膜，在半導體元件上形成具有非晶矽堆疊結構及氧化 矽·氮化矽薄膜之雙層預防反射薄膜，在雙層預防反射薄膜 之上形成光阻佈局圖案，使用光阻佈局圖案作爲遮罩選擇 性的將雙層預防反射薄膜及透明薄膜移除，及移除光阻佈 局圖案β 另外，本發明之方法特性上所包含之步驟爲：在半導 7 本紙張尺度適用中國國家標準（CNS ) Α4規格（2丨0Χ297公釐} 經濟部中央橾準局貝工消費合作社印製 4. 6 3 2 3 7 Α7 Β7 五、發明説明（<) 體底材上以步階高度差異之順序形成第一個墊絕緣薄膜和 第二個墊絕緣薄膜；在第二個墊絕緣薄膜之上形成具有非 晶矽堆疊結構及氧化矽-氮化矽薄膜：使用電漿處理雙層預 防反射薄膜；在雙層預防反射薄膜之上形成光阻佈局圖.案 ;使用光阻佈局圖案作爲遮罩，選擇性的移除雙層反射薄 膜和第二個墊絕緣薄膜；移除光阻佈局圖案；蝕刻第—個 墊絕緣薄膜和剩下的雙層預防度射薄膜，且形成一個第一 個和第二個墊絕緣薄膜佈局圖案以曝露半導體底材之預定 的部分。 另外，形成半導體元件之微佈局圖案的方法包含的步 驟爲:在半導體底材上形成元素隔離絕緣薄膜及閘極電極： 形成絕緣薄膜以便將半導體底材之表面平坦化；在絕緣薄 膜之上形成具有非晶矽之堆疊結構和氧化矽·氮化矽薄膜之 雙層預防反射薄膜；使用電漿處理雙層預防反射薄膜；在 ’雙層預防反射薄膜之上形成光阻佈局圖案；形成接觸孔洞 以便使用光阻佈局圖案作爲遮罩將半導體底材及閘極電極 之預定部分曝光；移除光阻佈局圖案；且移除雙層預防反 射薄膜。 同時，本發明之原理乃是要提供一個在半導體底材之 間的預防反射薄膜之細小的光線吸收器，使得曝光程序的 光線並沒有照在透明的絕緣薄膜如氧化薄膜，氮化薄膜& 氧化-氮化薄膜上，以便形成均勻的元素隔離佈局圖案和g 勻的接點佈局圖案β 在傳統技術中，當一般的單層預防反射薄膜插入透Β月 8 本紙張尺度適用中國困家標準（CNS )八4说格（210Χ297公釐) ' 裝 . 訂 ？ 冰 <請先閱讀背面之注^項再填寫本頁) 經濟部中央標準局貝工消費合作社印装 A7 五、發明説明（b ) 絕緣薄膜之間時，光阻會吸收大約50%之曝光光線，但其 餘的則照在透明薄膜之上，且在透明薄膜和高反射能力底 材之間的接觸面中所反射的光線出現在光阻薄膜上。 因此，即便預防反射薄膜的作用可避免某些厚度之透 明絕緣薄膜之反射，它並無法避免其它厚度之曝光光線之 反射，因而產生了非均勻性光阻佈局圖案之形成。 然而，本發明提供了雙層預防反射薄膜結構，包含一 預防反射薄膜例如氧化矽-氮化矽薄膜及一非晶矽，其由吸 收大部分的曝光光線來移除穿透到透明薄膜之曝光光線以 便提供均勻的佈局圖案，而避免在元素隔_離佈局圖案曝光 方法和接觸佈局圖案曝光方法中由於透明絕緣薄膜之厚度 差異產生佈局圖案尺寸之影響，其中元素隔離佈局圖案曝 光方法具有光阻/—雙層預防反射薄膜/ 一透明絕緣薄膜/一 高度反射能力之底材的堆疊結構。 吾人應可瞭解先前之一般敘述及下面的詳細描述兩者 均爲範例性及解釋性的，且意欲提供如申請專利範圍中本 發明的進一步解釋。 附圖之簡略說明 本發明之其他目的和情況從下列敘述之具體實施例並 參考附圖之後將變得更加明顯，其中： 圖1和2顯示了依照先前之技術形成半導體元件之微 佈局圖案之方法的截面視圖： 9 __ 本紙張尺度適用中國國家標準（CNS ) Α4规格（210Χ 297公釐） II! ^ n ί —訂 11 I I \ (請先閱锖背面之注意事項再填寫本页) 經濟部中央榡準局員工消費合作社印製 A7 B7 i'發明説明（Ί) 圖3顯示了依照圖2之先前技術之圖形；且 圖4到9顯示了依照本發明形成半導體元件之微佈局 _案之方法的截面視圖。 較佳實施例的詳細說明 現在將詳細參考本發明的較佳實施例，此範例乃例舉 於附圖中。 圖4到9顯示了依照本發明之實施例形成半導體元件 之微佈局圖案之方法的截面視圖，並顯示了以步階高度差 驾在半導體底材上形成元素隔離絕緣薄膜的技術 依照本發明形成半導體元件之微佈局圖案之方法，如 ® 4中所不，其建構之方式爲首先，—塾氧化薄膜32和一 塾氮化薄膜33在半導體底材31之元素隔離之預定部分上 以维階高度之差異形成。 另外，一吸收曝光光線之非晶矽34薄薄的在墊氮化薄 膜33上沉積。 非曰曰敬34在曝光波長如多晶砂材料中具有很高的虛數 折射率(k)，且可用具有很高之虛數折射率之材料如多晶矽 所取代。 在此，非晶矽34或多晶矽(未顯示出來)之虛數折射率 在248腿之光波波長下分別爲3.65和15，且其可能因爲結 晶化而有些許的變化。 另外，非砂和多晶政之吸收率”α，，由下面式子所決 _ 10 '裝 打 \···^ (靖先閲讀背面之注意事項再填寫本頁) 本紙张尺展通用Τ码ΒΗ参株华（CNS ) Μ規格（210x297公釐） 經濟部中央標準局貝工消費合作社印聚 4 63 23 ^ Α7 Β7 五、發明説明（？） 定： α =4 7Γ k/ λ.....-.............第 式 (其中α代表吸收率，k代表虛數折射率且λ代表曝光 波長） 由第一個公式，非晶砂和多晶砂在248mn光波波長之 吸收率分別爲0.0185A1和0.0177A·1。 另外，當248nm先波波長入射到非晶砍和多晶较上時 ，吸收37^(:^1)之厚度分別爲54A，56Α»因此，大部分之 曝光光線都在200或更少之厚度下即被吸收了。 然而，非晶矽34比起多晶矽爲較好的光線吸收者，因 爲非晶矽34之表面比多晶矽較爲平滑》 同時，非晶矽34之沉積乃由爐型式化學氣相沉積法 (CVD)，或電漿增強CVD (PECVD)加以執行。 在此，薄膜34之沉積厚度形成於100-500Α，使得曝光 光線無法穿透墊氮化薄膜33。 另外，沉積的條件中矽之來源氣體爲$出4或Si2H6，且 於此範例中，氫氣乃加以稀釋以便改善厚度之一致性及降 低沉積速率。髙頻功率爲0-1000W，沉積壓力0.01-10 Torr ，且底材溫度在室溫-700°C之間。接著，如圖5中所示的， 預防反射薄膜之堆疊層結構乃在非晶矽34之上形成氧化矽 -氮化矽薄膜35而形成的。 在此，氧化矽-氮化矽薄膜35以100-500A之厚度應用 PECVD方法形成。 另外，氧化矽-氮化矽薄膜35在曝光光線之波長爲 (請先閱讀背面之注意事項再填寫本頁) 裝- ,1Τ 本紙伕尺度適用中國國家梯準（CNS ) Α4規格（210Χ297公釐} A7 在63237 B7__ 五、發明説明（q ) 248nm時，其折射率的寊數部分爲1.5-2.5，且其虛數部分爲 0.1-1.5 » 另外，在深-UV光阻和非晶矽34分別沉積在氧化矽-氮化矽薄膜35上面和下面的例子中，其實數折射率，虛數 折射率，和其厚度分別爲2.1±0.2, 0.5土0.2, 300±50» 另外，氧化矽-氮化矽薄膜35由PECVD方法形成，且 使用 0-300sccm 的 SiH4，0-500sccm 的 N20，0-300sccm 的 NH3, 0-5000sccm 的 N2，和 0-5000sccm 的 He,且特別的是 NH3氣體未在例子中使用。 另外，氧化矽-氮化矽薄膜35以O.Ol-lOTorr之處理腔 壓力，100-500°C之底材溫度，及0-1000W之高頻功率來形 成。 在此，队和He氣體用做稀釋氣體，且它們可以大量的 混合以得到薄膜均勻性及降低沉積速率。 如圖6中所示的，在氧化矽·氮化矽薄膜35沉積之後， 氧氣電漿或N20電漿36乃做爲表面處理以便改善光阻(未 顯示出來)之佈局圖案。 在此，即便有墊氧化薄膜32和墊氮化薄膜33之非均 勻厚度，電漿表面處理也會加以執行以便得到均勻的元素 隔離光阻佈局圖案》接著，如圖7中所示的，光阻佈局圖 案37在氧化矽·氮化矽薄膜35之上形成。 在此，光阻佈局圖案37使用光阻(未顯示出來)做爲元 素隔離遮罩(未顯示出來)加以曝光並顯影之後選擇性的移 除。 12 本紙張尺度逋用中國國家榡準（CNS ) Α4規格(Tl〇X297&H ' f 訂 J "i (婧先閲讀背面之注意事項再填寫本頁〕 經濟部中央標準局員工消費合作社印製 A63 2 ί Α7 _____Β7_ 五、發明説明（（C?) 另外，光阻佈局圖案37之形成使得元素隔離區每個都 相同，也就是預定尺寸dl和d2(dl=d2) 〇 接著，如圖8中所示的，氧化矽-氮化矽薄膜35,非晶 矽34,墊氮化薄膜33利用光阻佈局圖案37作爲遮罩依序 加以蝕刻。 接著，氧化矽-氮化矽薄膜35和非晶矽34加以蝕刻， 其中氧化矽薄膜35或弈晶矽34及墊氮化薄膜33之蝕刻選 擇性爲1-3: 1，以作爲氮化薄膜蝕刻條件。 接著，墊氮化薄膜33利用光阻佈局圖案37作爲遮罩 加以蝕刻。 接著，如圖9中所示的，光阻佈局圖案37首先加以蝕 刻，氧化矽-氮化矽薄膜35和非晶矽薄膜34在墊氮化薄膜 33,非晶矽薄膜34和墊氧化薄膜32之蝕刻選擇性爲1-3: 1 之情況下完全加以移除。在此同時，墊氮化薄膜佈局圖案 33和墊氧化薄膜佈局圖案32由曝光半導體底材31之預定 區域而形成。 經濟部中央標準局貝工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 同時，本發明之另一個具體實施例中，接觸孔洞在具 有步階高度差異之兩個半導體底材部分上形成，且其原理 爲如本發明之實施例中所示的，利用雙層結構之薄膜形成 具有預定尺寸之佈局圖案。 此外，在肜成半導體元件之微佈局圖案的方法中，非 晶矽和氧化矽-氮化矽薄膜之堆叠結構在光阻和透明薄膜之 間形成，且佈局的方法在光阻上實行以便形成元件之均勻 的微佈局圖案並產生鑄模內之元素特性均勻化。 13 Ϊ紙張尺度it用中國因家標率（CNS ) A4規格< 210X297公釐) ^ 經濟部智慧財產局員工消費合作社印製 岸 1一 >. B7_1——.”.._一 五、發明說明（II ) 再者，層間佈線之黏著性之可靠度已經有所改善，因 此半導體元件之良率有很大的改善。 再者，由於已經詳細的描述了本發明，吾人應可瞭解 在不偏離本發明之精神及範圍之下，如同所附之申請專利 範圍中所界定的，可以有許多不同的變化，替代性及修正 性。 圖式元件符號說明 A7 1 半導體底材 2 氧化矽層 3 氮化矽薄膜 4 光阻層 11 半導體底材 12 元素隔離絕緣薄膜 13 閘極氧化薄膜 14 字元線 15 氧化矽薄膜 16 第一個接點孔洞 17 第二個接點孔洞 31 半導體底材 32 墊氧化薄膜 33 墊氮化薄膜 34 非晶矽 35 氧化矽-氮化矽薄膜 36 電漿 14 ----------- 敦--------訂-----一！線 (請先閱讀背面之泛意事項再填寫本頁) 本紙張尺度適用中國國家標準CCNS)A4規格（210 X 297公t ) 4 63 23 /_B7 4 63 23 /_B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（C) 37 光阻佈局圖案 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------· I 訂·------— 1 (請先閱讀背面之注意事項再填寫本頁)Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shelley Consumer Cooperative, 463237 V. Description of the Invention (丨) Field of the Invention The present invention relates to a method for forming a micro-layout pattern of a semiconductor device, and more particularly, to form an anti-reflection film to reduce the layout pattern Non-uniformity and deformation technology. This non-uniformity and deformation is caused by notches caused by scattered reflections or vibration during the exposure process of element isolation and contact forming. This is caused by uniform conversion on the semiconductor substrate. The layout pattern of the mask regardless of the thickness of the stray reflective layer that appears on the highly reflective substrate. Description of the Related Art Conventionally, a method for forming a micro-layout pattern of a semiconductor device is exemplified in detail in FIGS. 1 to 3. 1 and 2 are sectional views showing a method of forming a micro-layout pattern of a semiconductor element according to the prior art. FIG. 3 is a graph showing the reflectance of FIG. 2 according to the prior art. In the method for forming a micro-layout pattern of a semiconductor device according to the prior art, as described in FIG. 1, a silicon oxide layer 2 and a silicon nitride film 3 are sequentially formed on the semiconductor substrate 1. Then, a photoresist layer 4 is formed. Deposited on the silicon nitride film 3 β 'Next, the photoresist layer 4 is selectively removed by exposure and development methods using an element separation mask (not left out) to form a photoresist layout pattern 4 β. Next, a photoresist is used The layout pattern 4 is used as a mask to selectively remove the silicon oxide layer 2 and the silicon nitride film 3 until the semiconductor substrate 1 is exposed. (Please read the precautions on the back before filling in this page.) Use Chinese National Standard (CNS) A4 specification (2 丨 0 > < 297 mm) 463237 Employees' Cooperative Cooperatives Printed by the Central Bureau of Standards of the Ministry of Economic Affairs B7. 5. Description of Invention (>) in order to form a semiconductor substrate 1 Element ^ isolation area on the surface. Next, a thermal oxidation film (not shown) is formed on the element isolation region by oxidative diffusion, thereby forming an element isolation film (not shown). When the thermally oxidized thin film forms the uppermost element isolation region by oxygen diffusion, the silicon nitride thin film 3 is formed to suppress the growth of the oxidized thin film in the horizontal direction. In addition, in the exposure method, the reflectivity of the semiconductor substrate is very high and the mold size increases when the wavelength of light is shortened, and the sizes cil and d2 of the photoresist layout pattern as element isolation are not a single size (dl Yin d2), but the size of the layout pattern is reduced by 0.3 / zm. This is because the size of the photoresist layout pattern is proportional or proportional to the intensity of the exposure light distributed in the photoresist layout pattern. In other words, the light reflected from the highly reflective substrate completely passes through the silicon oxide and silicon nitride films without being absorbed by them, and because of the small step height difference between the silicon oxide film and the silicon nitride film The reflectivity of the photoresist changes greatly. Therefore, if the method of manufacturing a semiconductor element is performed as described above, the characteristics of each unit element will change. In addition, as shown in FIG. 2, an element isolation insulating film 12, a gate oxide film 13, and a word line 14 are formed on the semiconductor substrate 11. Next, a silicon oxide film 15 is formed on the exposed surface of the entire structure so as to flatten the upper half surface. Next, a photoresist (not shown) is deposited on the entire structure. 5 This paper is again applicable to the Chinese standard (CNS) Α4 size (210 × 297 mm) (Please read the precautions on the back before filling This page is printed. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 63 23 7 A7 B7 V. Description of the invention (ingenious) on the surface, and using a contact mask (not shown) to block the photoresist through exposure and development Selective removal to form a photoresist layout pattern (not shown) on the silicon oxide film 15. Here, the exposure method is performed using light sources with wavelengths of 365 nm and 248 nm. Then, the above-mentioned exposure light is not absorbed and completely reflected by the silicon oxide film 15 appearing between the semiconductor substrate 11 and the word line 14. Therefore, the reflection ability of the photoresist is greatly changed due to the thickness difference of the silicon oxide film 15, even if the silicon oxide film has only a difference in micrometer thickness. Next, the photoresist layout pattern (not shown) is used as a mask to selectively remove the silicon oxide film 15 to form the first and second contacts exposing the semiconductor substrate 11 and the word line 14. Holes 16 and 17. Here, as shown in FIG. 3, among the optical characteristics of the silicon oxide film under the light of 365 nm and 248 nm, its reflection capacity for photoresist changes periodically depending on the thickness of the oxide film. Such a change in the re-reflection ability causes a change in the size of the contact hole, and sometimes the contact hole is not even formed. As described above, the conventional method of forming a micro-layout pattern of a semiconductor element has the following problems. When a transparent insulating film such as a silicon oxide film or a silicon nitride film, etc., does not absorb light with an exposure wavelength of 365nm and 248nm, and it will appear between substrates with high reflectance and photoresistance, and the transparent When the insulation film has a thickness difference of nearly 200-700 A on the substrate, due to the difference in thickness and the difference in the re-reflection ability of the exposure light of 0.1-0.5, it will increase by 6 This paper size applies Chinese National Standard (CNS) A4 Specifications (210X297 mm) (Please read the precautions on the back before filling this page) Installation---0 Α7 Β7 46323 V. Description of the invention (4) Strong and destructive interference β (Please read the precautions on the back before (Fill in this page) Therefore, the layout pattern that should be uniformly formed on the semiconductor substrate should be unevenly formed according to the position on the substrate. 6 In addition, the required layout pattern will not be formed, thus reducing yield and components. The quality is reduced, which makes it difficult to produce highly integrated components. Summary of the Invention Therefore, one of the objects of the present invention is to overcome the problems encountered in the aforementioned prior art, and to perform a layout pattern program on a substrate to provide a method for forming a micro-layout pattern to a high volume Semiconductor devices, the substrate of which has a high step height difference and high reflectivity, and uses a double-layer anti-reflection film β Another object of the present invention is to provide a micro-layout pattern for forming semiconductor devices. Methods to Improve the Characteristics and Yield of Semiconductor Components "Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, in order to achieve these and other advantages of the present invention, the method for forming micro-layout patterns of semiconductor components includes the steps of: providing steps Semiconductor substrates with different step heights, a transparent film is formed on the semiconductor substrate at the exposure wavelength, and a double-layer anti-reflection film with an amorphous silicon stack structure and a silicon oxide and silicon nitride film is formed on the semiconductor element. Preventing the formation of photoresist layout patterns on reflective films, using photoresist layout patterns as masks Removing the double-layer anti-reflection film and transparent film, and removing the photoresist layout pattern β In addition, the method characteristic of the present invention includes the following steps: In the semiconducting 7 paper size, the Chinese National Standard (CNS) Α4 specification is applied (2 丨 0 × 297 mm) 4.6 3 2 3 7 Α7 Β7 printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (<) The first step on the body substrate is in the order of step height differences. A pad insulation film and a second pad insulation film; forming an amorphous silicon stack structure and a silicon oxide-silicon nitride film on the second pad insulation film: using a plasma to treat a double-layer anti-reflection film; Prevent the formation of a photoresist layout on the reflective film. Use the photoresist layout pattern as a mask to selectively remove the double-layer reflective film and the second pad insulation film; remove the photoresist layout pattern; etch the first— The pad insulation film and the remaining double-layered preventive radiation film, and form a first and a second pad insulation film layout pattern to expose a predetermined portion of the semiconductor substrate. In addition, a micro layout diagram of the semiconductor element is formed The method includes the steps of: forming an element isolation insulating film and a gate electrode on a semiconductor substrate: forming an insulating film to planarize the surface of the semiconductor substrate; forming a stacked structure with amorphous silicon on the insulating film and oxidizing Double-layer anti-reflection film of silicon and silicon nitride film; use plasma to treat double-layer anti-reflection film; form photoresist layout pattern on 'double-layer antireflection film; form contact holes to use photoresist layout pattern as a mask Exposing a predetermined portion of a semiconductor substrate and a gate electrode; removing a photoresist layout pattern; and removing a double-layer antireflection film. At the same time, the principle of the present invention is to provide an antireflection film between semiconductor substrates. Small light absorber, so that the light of the exposure process does not shine on transparent insulating films such as oxide films, nitride films & oxide-nitride films, in order to form a uniform element isolation layout pattern and g uniform contacts Layout pattern β In the conventional technology, when a general single-layer antireflection film is inserted through Sleepy home Standard (CNS) eight 4 said grid (210Χ297 mm) 'equipment. Book? Bing < Please read the note ^ on the back before filling this page) Printed by A7 of the Central Standards Bureau of the Ministry of Economic Affairs, Printed by the Bayer Consumer Cooperative. V. Description of the Invention (b) The photoresist will absorb about 50% of the exposure between the insulating films Light, but the rest shines on the transparent film, and the light reflected in the contact surface between the transparent film and the highly reflective substrate appears on the photoresist film. Therefore, even though the prevention of the reflective film can prevent the reflection of transparent insulating films of certain thicknesses, it cannot prevent the reflection of the exposure light of other thicknesses, thus creating the formation of non-uniform photoresist layout patterns. However, the present invention provides a double-layer anti-reflection film structure, including an anti-reflection film such as a silicon oxide-silicon nitride film and an amorphous silicon, which absorbs most of the exposure light to remove the exposure penetrating to the transparent film. Light in order to provide a uniform layout pattern while avoiding the effect of layout pattern size due to the difference in thickness of the transparent insulating film in the element separation and separation layout pattern exposure method and contact layout pattern exposure method, wherein the element isolation layout pattern exposure method has photoresist / —Double-layer anti-reflection film / A transparent insulating film / A highly reflective substrate stack structure. I should understand that both the previous general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as in the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Other objects and conditions of the present invention will become more apparent from the specific embodiments described below and with reference to the accompanying drawings, in which: FIGS. 1 and 2 show micro-layout patterns of semiconductor devices formed according to the prior art; Sectional view of the method: 9 __ This paper size applies to the Chinese National Standard (CNS) Α4 size (210 × 297 mm) II! ^ N ί —Order 11 II \ (Please read the notes on the back of the page before filling this page) Economy Printed on the A7 B7 i 'Invention Description (Ί) of the Central Government Procurement Bureau Employee Consumer Cooperative (Figure 3) Figure 3 shows the prior art pattern according to Figure 2; and Figures 4 to 9 show the micro-layout of semiconductor components formed in accordance with the present invention Sectional view of the method. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. 4 to 9 show cross-sectional views of a method for forming a micro-layout pattern of a semiconductor element according to an embodiment of the present invention, and show a technique for forming an element isolation insulating film on a semiconductor substrate with a step height difference formed in accordance with the present invention The method for the micro-layout pattern of semiconductor elements is not the same as that in ® 4, and the construction method is first of all-the hafnium oxide film 32 and the hafnium nitride film 33 are dimensionally ordered on a predetermined portion of the element isolation of the semiconductor substrate 31 A difference in height is formed. In addition, a thin amorphous silicon 34 that absorbs the exposure light is deposited on the pad nitride film 33 thinly. Feijing 34 has a high imaginary refractive index (k) in exposure wavelengths such as polycrystalline sand materials, and can be replaced with a material with a high imaginary refractive index such as polycrystalline silicon. Here, the imaginary refractive index of amorphous silicon 34 or polycrystalline silicon (not shown) is 3.65 and 15 at the wavelength of the light wave of 248 legs, and it may be slightly changed due to crystallization. In addition, the absorptivity of non-sand and polycrystalline government "α" is determined by the following formula _ 10 'installation \ ··· ^ (Jing first read the precautions on the back before filling in this page) This paper shows the general T code ΒΗginsand plants (CNS) Μ specifications (210x297 mm) Printed by the Central Laboratories of the Ministry of Economic Affairs Shellfish Consumer Cooperatives 4 63 23 ^ Α7 Β7 V. Description of the invention (?) Definition: α = 4 7Γ k / λ ... ..-............. Formula (where α is the absorptivity, k is the imaginary refractive index and λ is the exposure wavelength) From the first formula, amorphous sand and polycrystalline sand are in The absorptances of the 248mn light wave wavelength are 0.0185A1 and 0.0177A · 1. In addition, when the 248nm first wave wavelength is incident on the amorphous chopping and polycrystalline, the absorption thicknesses of 37 ^ (: ^ 1) are 54A, 56A »As a result, most of the exposure light is absorbed at a thickness of 200 or less. However, amorphous silicon 34 is a better light absorber than polycrystalline silicon because the surface of amorphous silicon 34 is more than polycrystalline silicon. "Smoothing" At the same time, the deposition of amorphous silicon 34 is performed by furnace-type chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD). Here, thin The deposition thickness of 34 is formed at 100-500A, so that the exposure light cannot penetrate the pad nitride film 33. In addition, the source gas of silicon in the deposition conditions is $ 4 or Si2H6, and in this example, hydrogen is diluted so that Improve the consistency of thickness and reduce the deposition rate. The frequency power is 0-1000W, the deposition pressure is 0.01-10 Torr, and the substrate temperature is between room temperature and 700 ° C. Then, as shown in Figure 5, prevent The stacked layer structure of the reflective film is formed by forming a silicon oxide-silicon nitride film 35 on the amorphous silicon 34. Here, the silicon oxide-silicon nitride film 35 is formed using a PECVD method at a thickness of 100-500 A. In addition, The wavelength of the exposed light of the silicon oxide-silicon nitride film 35 is (please read the precautions on the back before filling in this page). -1T This paper's standard applies to China National Standard (CNS) A4 specification (210 × 297 mm) A7 at 63237 B7__ V. Description of the invention (q) at 248nm, the refractive index part is 1.5-2.5, and its imaginary part is 0.1-1.5 »In addition, deep-UV photoresist and amorphous silicon 34 are deposited separately Examples above and below the silicon oxide-silicon nitride film 35 The actual refractive index, imaginary refractive index, and thickness are 2.1 ± 0.2, 0.5 ± 0.2, 300 ± 50, respectively. In addition, the silicon oxide-silicon nitride film 35 is formed by the PECVD method, and a 0-300sccm SiH4, 0-500sccm of N20, 0-300sccm of NH3, 0-5000sccm of N2, and 0-5000sccm of He, and especially NH3 gas was not used in the examples. In addition, the silicon oxide-silicon nitride film 35 is formed using a processing chamber pressure of 0.01 to 100 Torr, a substrate temperature of 100 to 500 ° C, and a high frequency power of 0 to 1000 W. Here, the He and He gases are used as diluent gases, and they can be mixed in a large amount to obtain film uniformity and reduce the deposition rate. As shown in FIG. 6, after the silicon oxide · silicon nitride film 35 is deposited, the oxygen plasma or N20 plasma 36 is used as a surface treatment to improve the layout pattern of the photoresist (not shown). Here, even if there is a non-uniform thickness of the pad oxide film 32 and the pad nitride film 33, the plasma surface treatment will be performed to obtain a uniform element isolation photoresist layout pattern. Then, as shown in FIG. 7, the light The resist layout pattern 37 is formed on the silicon oxide / silicon nitride thin film 35. Here, the photoresist layout pattern 37 is selectively removed after being exposed and developed using a photoresist (not shown) as an element isolating mask (not shown). 12 This paper uses China National Standards (CNS) A4 specifications (T10X297 & H'f J " i (Jing first read the precautions on the back before filling out this page) Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs System A63 2 ί Α7 _____ Β7_ V. Description of the invention ((C?) In addition, the formation of the photoresist layout pattern 37 makes the element isolation regions each the same, that is, the predetermined dimensions dl and d2 (dl = d2). Then, as shown in the figure As shown in 8, silicon oxide-silicon nitride film 35, amorphous silicon 34, and pad nitride film 33 are sequentially etched using a photoresist layout pattern 37 as a mask. Next, the silicon oxide-silicon nitride film 35 and The amorphous silicon 34 is etched, and the etching selectivity of the silicon oxide film 35 or the crystalline silicon 34 and the pad nitride film 33 is 1-3: 1 as the etching conditions for the nitride film. Next, the pad nitride film 33 is used. The photoresist layout pattern 37 is etched as a mask. Next, as shown in FIG. 9, the photoresist layout pattern 37 is first etched, and a silicon oxide-silicon nitride film 35 and an amorphous silicon film 34 are formed on the pad nitride film 33. The etch selectivity of the amorphous silicon film 34 and the pad oxide film 32 is 1-3: 1 In this case, the pad nitride film layout pattern 33 and the pad oxide film layout pattern 32 are formed by exposing a predetermined area of the semiconductor substrate 31. Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (Please (Read the precautions on the back before filling this page) At the same time, in another embodiment of the present invention, the contact holes are formed on two semiconductor substrates with step height differences, and the principle is as implemented in the present invention As shown in the example, a double-layered thin film is used to form a layout pattern with a predetermined size. In addition, in a method of forming a micro-layout pattern of a semiconductor device, a stack structure of an amorphous silicon and a silicon oxide-silicon nitride film is It is formed between the photoresist and transparent film, and the layout method is implemented on the photoresist so as to form a uniform micro-layout pattern of the element and to uniformize the characteristics of the elements in the mold. 13 ΪPaper scale it uses the Chinese standard (CNS) ) A4 specifications < 210X297 mm) ^ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed on the shore 1 1 >. B7_1——. ".. _5. Description of the invention ( II) Furthermore, the reliability of the adhesion of the interlayer wiring has been improved, so the yield of semiconductor devices has been greatly improved. Furthermore, since the present invention has been described in detail, we should understand that without departing from this Under the spirit and scope of the invention, as defined in the scope of the attached patent application, there can be many different changes, substitutions and corrections. Schematic symbol description A7 1 Semiconductor substrate 2 Silicon oxide layer 3 Nitriding Silicon film 4 Photoresist layer 11 Semiconductor substrate 12 Element isolation insulating film 13 Gate oxide film 14 Character line 15 Silicon oxide film 16 First contact hole 17 Second contact hole 31 Semiconductor substrate 32 Pad oxide film 33 Pad nitride film 34 Amorphous silicon 35 Silicon oxide-silicon nitride film 36 Plasma 14 ----------- Dun -------- Order ----- One! Line (please read the general Italian matter on the back before filling this page) This paper size is applicable to the Chinese National Standard CCNS A4 size (210 X 297g t) 4 63 23 / _B7 4 63 23 / _B7 Employee Consumption of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the cooperative V. Description of the invention (C) 37 Photoresist layout pattern The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ---------------- ---- · Order I ---------- 1 (Please read the notes on the back before filling in this page)