1333239 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種形成接觸孔的方法，尤指一種利用 兩次以上曝光、兩次以上触刻之方式形成接觸孔的方法。 【先前技術】 > 隨著半導體製造技術越來越精密，積體電路也發生重 Φ 大的變革，使得電腦的運算性能和存儲容量突飛猛進，並 帶動周邊産業迅速發展。而半導體產業也如同摩爾定律所 預測的，以每18個月增加一倍電晶體數目在積體電路上的 • 速度發展著，同時半導體製程也已經從1999年的0.18微 - 米、2001年的0.13微米、2003年的90奈米（nm)(〇.〇9微米）， 進入到2005年65奈米（0.065微米製程）並朝向45奈米 邁進。因此，伴隨著半導體製程的進步和微電子元件的微 小化，單一晶片上的半導體元件的密度越來越大，相對地 元件之間的間隔也越來越小。這使得接觸洞（contact hole) 蚀刻（etch)製程的製作困難度越來越高。 先前技術中製作接觸洞的作法，係利用光阻層作為蝕 刻下方介電層的敍刻遮罩’而在45奈米（nm)的製程下，接 觸孔蝕刻的間距（pitch，即兩鄰近接觸孔中心點間之距離） 必須小於155奈米，而且顯影後關鍵尺寸（after development inspect critical dimension，ADICD)則必須大約 70 至 80 奈 1333239 米。就現行的黃光機台技術而言，其無法於一次曝光製程 t完成間距小於155奈米的接觸孔，所以目前業界常見的 作法是利用兩個光罩對光阻層進行兩次曝光後，再進行一 次蝕刻，以圖案化接觸孔。 但疋’當接觸孔#刻的間距小於14〇奈米時，即使是 利用上述兩次曝光、一次蝕刻的製程，也會因為進行第二 • 次曝光顯影時，黃光機台無法定義出過小的接觸孔圖案 (pattern)，而無法製作出接觸孔間距小於14〇奈米的接觸 孔。所以，如何製作出接觸孔蝕刻的間距小於14〇奈米的 ' 接觸孔係為該領域之重要課題。 【發明内容】 本發明係提供一種形成接觸孔的方法，以解決上述 題。 σ 本發明之一較佳實施例係提供一種形成接觸孔的方 法，包含提供-半導體基材，其上依序覆蓋—㈣停止層、 -層間介電層、一第一含石夕光阻層。於第一含石夕光阻層上 方形成一第一光阻圖案’接著’利用第一光阻圖案作為蝕 罩，進行-第-餘刻製程於含石夕光阻層形成複數個第 一開口。去除第-光阻圖案1後’於切光阻層上方形 成一第二光阻圖案，利用第二光阻圖案作為關遮罩，進 行-第二飯刻製程於含石夕光阻層形成複數個第二開口，以 6 1333239 及利用具有第一、第二開口的含矽光阻層作為蝕刻遮罩， 進行蝕刻製程，於層間介電層、蝕刻停止層中形成接觸孔。 本發明之另一較佳實施例係提供一種形成接觸孔的方 法，包含提供一半導體基材，其上依序覆蓋一層間介電層、 一第一含石夕光阻層。於第一含石夕光阻層上方形成一第一光 阻圖案，再利用第一光阻圖案作為蝕刻遮罩，進行一第一 触刻製程於第一含石夕光阻層形成複數個第一開口，去除第 一光阻圖案。然後，利用第一開口作為蝕刻遮罩，進行蝕 刻製程於層間介電層中形成複數個第一接觸孔並除去第一 含矽光阻層，於層間介電層上方形成一第二含矽光阻層， 於第二含矽光阻層上方形成一第二光阻圖案，以及利用第 二光阻圖案作為蝕刻遮罩，進行蝕刻製程於層間介電層中 形成複數個第二接觸孔。 和先前技術相較，先前技術是利用兩次曝光製程，曝 光在同一層光阻層上，所以會因為目前曝光機台無法定義 出過小的接觸孔圖案，造成曝光失敗。但是，就本發明而 言，本發明係先進行一次曝光後，就直接進行蝕刻製程， 將第一次曝光所產生的圖案轉移至含矽光阻層或者是層間 介電層中。接著，重新形成一光阻層，在不同位置再進行 一次曝光，再將新的圖案轉移至含矽光阻層或者是層間介 電層中。這種兩次曝光、兩次蝕刻的方式即可以形成觸孔 蝕刻的間距小於140奈米的結構。當然本發明在曝光機台 7 1333239 允許的情況下，也可以應用於兩次以上曝光、兩次以上蝕 刻，以形成間距更小的接觸孔。 【實施方式】 請參考第1至7圖，第1至7圖係為本發明第一實施 例之蚀刻接觸洞蚀刻停止層（contact etch stop layer，CESL) 之製程示意圖。如第1圖所示，首先提供一基底102，例 如一晶圓（wafer)或一矽覆絕緣（SOI)等之半導體基底， 且基底102表面已形成有金氧半導體電晶體等各式元件， 接著於基底102上方依序形成一接觸洞蝕刻停止層1〇4、 一層間介電層（interlayer dielectric, ILD) 106、一三層堆叠層 Π4。三層堆疊層114包含有一抗反射底層（bottom anti-reflective coating，BARC)108、一含石夕光阻層 11〇 以及 一 193(nm)奈米光阻層112。其中，抗反射底層1〇8係可利 用一 365奈米光阻層’即屬於i_Hne曝光範圍的光阻層來 形成。而193nm光阻層112則為深紫外光曝光範圍。另外， 層間介電層106可以包含有未摻雜矽氧層、摻雜矽氧層， 如四乙氧基碎院(tetetra-ethyl-ortho-silicate，TE0S)梦氧 層、或硼磷矽玻璃、氟矽氧層 '磷矽氧層或硼矽氧層等。 而且可利用電漿加強化學氣相沈積製程等薄膜沈積技術來 形成層間介電層106❶另外’在第一實施例中，接觸洞餘 刻停止層104的厚度為850埃(入）、一層間介電層1〇6的厚 度為3000埃、一抗反射底層1〇8的厚度為18〇〇埃一含 8 1333239 矽光阻層110的厚度為800埃以及一 193nm光阻層112的 厚度為2200埃。然後進行一曝光製程和顯影製程，以圖案 化193nm光阻層112。 接著，請參考第2圖，利用圖案化的193nm光阻層112 作遮罩，進行一蝕刻製程，並調整蝕刻氣體比例或壓力， power等參數以圖案化含矽光阻層110以得到具有數個梯 型的開口 202。每個開口 202的側邊都具有斜角（taper)204, 藉由調整蝕刻參數來改變斜角程度，開口 202的底部的寬 度較頂口處小。而且開口 202的深度僅500A，所以開口 202 的底部並未露出抗反射底層108，這樣可以保護抗反射底 層108結構的完整性。之後，去除殘餘的193nm光阻層112。 請參考第3圖。接著，重新形成一 193nm光阻層312， 而且新形成的193nm光阻層312會填滿開口 202，如第3 圖所示。然後再進行一曝光和顯影製程，以圖案化193nm 光阻層312。 請參考第4圖，以圖案化193nm光阻層312作為遮罩， 再進行另一次蝕刻製程，再次圖案化含矽光阻層110，形 成數個開口 402。開口 402的底部的寬度也較開口處小， 所以開口 402的側邊具有斜角204。而且開口 202的深度 僅500A，所以開口 202的底部並未露出抗反射底層108， 以保護抗反射底層108的結構。之後，去除殘餘的193nm 9 1333239 光阻層312。 睛參考第5目’直接對含石夕光阻層11〇進行蚀刻，直 到餘刻穿切光阻層m，暴^抗反射底層⑽。接著， 繼續對抗反射底層⑽進行_直到暴露出層間介電層 106為止。之後，利用已經被圖案化的抗反射底層1〇8作 為遮罩，利用-触刻製程將層Μ介電I 1〇6餘刻至暴露出 接觸洞蝕刻停止層1〇4。此時，含矽光阻層η〇已經被耗 損完，而抗反射底層108也已經被耗損許多。 請參考第6圖，去除剩下的抗反射底層1〇8。接著， 凊參考第7圖，以圖案化後的層間介電層1〇6作為遮罩， 進行一突破(break through)性質的蝕刻製程以圖案化接觸 洞蝕刻停止層104，形成如第7圖所示之接觸孔7〇2。 請參考第8至15圖，第8至15圖係為本發明第二實 施例之蝕刻接觸洞蝕刻停止層之製程示意圖。第二實施例 和第一實施例的差別是在於第二實施例多了金屬化合物遮 罩層1602在層間介電層106和抗反射底層1〇8之間。 如第8圖所示，首先提供一已形成有金氧半導體電晶 體等各式元件之基底102 ’接著於基底102上方依序形成 一接觸洞蝕刻停止層104、一層間介電層1〇6、一金屬化合 物遮罩層1602、一三層堆疊層114。三層堆疊層114包含 1333239 有一抗反射底層108、一含石夕光阻層110以及一 193nm光 阻層112。其中，抗反射底層108可為365 nm光阻層，而 193nm光阻層112則為深紫外光曝光範圍。另外，在第二 實施例中，接觸洞蝕刻停止層104的厚度為850埃(A)、一 層間介電層106的厚度為3000埃、一抗反射底層108的厚 度為1800埃、一含矽光阻層110的厚度為800埃以及一 193nm光阻層112的厚度為2200埃。首先，進行一曝光製 程和顯影製程，以圖案化193nm光阻層112。 接著，請參考第9圖，利用圖案化的193nm光阻層112 作遮罩，進行一蝕刻製程以圖案化含矽光阻層110。蝕刻 後所形成的圖案化含矽光阻層110具有數個梯型的開口 202，且開口 202的底部的寬度較頂口處小，其側邊具有斜 角204。而且開口 202的深度僅500A，所以開口 202的底 部並未露出抗反射底層108，以保護抗反射底層108的結 構。之後，去除殘餘的193nm光阻層112。 請參考第10圖，接著，重新形成一 193nm光阻層312, 而且新形成的193nm光阻層312會填滿開口 202中。然後， 再進行一曝光和顯影製程，以圖案化193nm光阻層312。 然後，請參考第11圖，以圖案化193nm光阻層312作為 遮罩，再進行另一次蝕刻製程，再次圖案化含矽光阻層 110，形成數個開口 402，開口 402的側邊具有斜角204， 且開口 402的底部的寬度也較開口處小。另外，開口 202 1333239 的深度也只有5GGA，所以開σ 2G2的底部並未露出抗反射 底層108，以保護抗反射底層1〇8的結構。之後，去除殘 餘的193nm光阻層312。 口月參考第12目’直接對含石夕光阻| 11〇進行飯刻直 到暴露出抗反射底層⑽。接著，利關案化後的含石夕光 阻層則作银刻遮罩’對抗反射底層⑽進行一則製程 直到暴露出金屬化合物遮罩層膽。^後，以圖案化的抗 反射底層⑽作為鮮，再對金屬化合物遮罩層膽進行 敍刻以圖案化金制⑽2。之後，去除掉金耗合物遮罩 層1602上方所有的光阻層。 請參考第13圖’以圖案化後的金屬層_2作為遮罩， 對層間介電層⑽進行_，以形成圖案化的層間介電層 106並暴露出接觸洞餘刻停止層^ 。 圖，去除圖案化後的金屬化合物遮罩層 H)6作Π罩：考第15圖，以圖案化後的層間介電層 成如第15圖所示之接觸孔702。 π參考第16至23圖，第化至^圖係為本 ^例之_接觸_刻停止層之製程示意圖。如第= 不，關地’提供—已形成有金氧半導體電晶體等各式 1333239 元件之基底102，且基底102上方依序具有一接觸洞蝕刻 停止層104、一層間介電層106、一三層堆疊層114。三層 堆疊層114包含有一抗反射底層108、一含紗光阻層110 以及一 193nm光阻層112。其中，抗反射底層108可為365 nm光阻層108。另外，在第三實施例中，接觸洞触刻停止 層104的厚度為850埃(人）、一層間介電層106的厚度為 3000埃、一抗反射底層108的厚度為1800埃、一含矽光 阻層110的厚度為800埃以及一 193nm光阻層112的厚度 為2200埃。首先，進行一曝光製程和顯影製程，以圖案化 193nm光阻層112。 接著，請參考第17圖，利用圖案化的193nm光阻層 112作遮罩，進行一蝕刻製程，以圖案化含矽光阻層110， 蝕刻後所形成的圖案化含矽光阻層110具有數個梯型的開 口 202。每個開口 202的側邊都具有斜角204，且開口 202 的底部的寬度較頂口處小。另外開口 202的深度僅500A， 所以開口 202的底部並未露出抗反射底層108，以保護抗 反射底層108的結構。之後，去除殘餘的193nm光阻層112。 請參考第18圖，接著，以圖案化後的含矽光阻層110 作為遮罩，蝕刻含矽光阻層110直到暴露出抗反射底層 108。此階段的蝕刻製程，使得原本厚度為800 A的含矽光 阻層110消耗成厚度僅剩下500 A。在此請特別注意，由於 開口 202的底部寬度較頂口處小，使得此階段蝕刻的寬度 13 1333239 係以開口 202底部的寬度為準。之後，繼續利用被蝕刻穿 的含吩光阻層110作為遮罩，對抗反射底層1〇8進行蝕刻 直到暴露出層間介電層1〇6為止，以圖案化抗反射底層 108。一般來說，含矽光阻層丨1〇經過抗反射底層1〇8的蝕 刻製程後，含矽光阻層11〇已經被蝕刻製程耗損完全。 請參考第19圖’以圖案化後的抗反射底層ι08作為遮 • 單對層間介電層106進行蝕刻’直到暴露出接觸洞蝕刻停 止層104並形成數個開口 1902。接著，去除層間介電層106 上方的抗反射底層1〇8。 請參考第20圖’重新依序在圖案化後的層間介電層 106上方形成一抗反射底層ι2〇2、一含矽光阻層12〇4以及 一 193 nm光阻層1206，而且抗反射底層12〇2係填滿每個 開口 1902中。接著，如同第16圖一樣，對193nm光阻層 1206進行-曝光製程和顯影製程以圖案化193nm光阻層 1206 ’但是其曝光區域和第16圖之曝光區域不同。 接下來的步驟就如同上述第Π至第19圖的步驟。利 用圖案化的193nm光阻層12()6作遮罩，進行一触刻製程， 以圖案化3碎光阻層12〇4。接著，以圖案化後的含石夕光阻 層1204作為遮罩，飾办丨a 做刻含矽光阻層1204直到暴露出抗反 射底層1202。之後，搞 欠繼續利用被蝕刻穿的含矽光阻層12〇4 作為遮罩，對抗反射麻恩 τ紙層1202進行蝕刻直到暴露出層間介 1333239 電層106為止，以圖案化抗反射底層1202。然後，以圖案 化後的抗反射底層1202作為遮罩對層間介電層106進行蝕 刻直到暴露出接觸洞蝕刻停止層104。此時含矽光阻層 1204已在蝕刻製程中消耗完，但是還殘餘一些抗反射底層 1202，形成如第21圖的結構。 請參考第22圖，接著，去除層間介電層106上方的抗 反射底層1202。然後，請參考第23圖，以圖案化後的層 間介電層106作為遮罩，進行一突破性質的蝕刻製程以圖 案化接觸洞蝕刻停止層104，形成如第23圖所示之接觸孔 702。 和先前技術相較，先前技術是利用兩次曝光製程，曝 光在同一層光阻層上，所以會因為目前曝光機台無法定義 出過小的接觸孔圖案，造成曝光失敗。但是，就本發明而 言，本發明係先進行一次曝光後，就直接進行蝕刻製程， 將第一次曝光所產生的圖案轉移至含矽光阻層或者是層間 介電層中。接著，重新形成一光阻層，在不同位置再進行 一次曝光，再將新的圖案轉移至含矽光阻層或者是層間介 電層中。這種兩次曝光、兩次蝕刻的方式即可以形成觸孔 蝕刻的間距小於140奈米的結構。當然本發明在曝光機台 允許的情況下，也可以應用於兩次以上曝光、兩次以上蝕 刻，以形成間距更小的接觸孔。 15 1333239 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 圍。 【圖式簡單說明】 第1至7圖係為本發明第一實施例之蝕刻接觸洞蝕刻停止 層之製程示意圖。 第8至15圖係為本發明第二實施例之蝕刻接觸洞蝕刻停止 層之製程示意圖。 第16至23圖係為本發明第三實施例之钮刻接觸洞飯刻停 止層之製程示意圖。 【主要元件符號說明】 基底 接觸洞餘刻停止層 層間介電層 抗反射底層 含矽光阻層 193nm光阻層 三層堆疊層 開口 斜角 接觸孔 金屬化合物遮罩層 102 104 106 108 ' 1202 110 、 1204 112 、 312 、 1206 、 1802 114 202 、 402 204 702 16021333239 IX. Description of the Invention: [Technical Field] The present invention relates to a method of forming a contact hole, and more particularly to a method of forming a contact hole by using two or more exposures or two or more touches. [Prior Art] > As the semiconductor manufacturing technology becomes more and more sophisticated, the integrated circuit also undergoes major changes, which makes the computing performance and storage capacity of the computer advance by leaps and bounds, and drives the surrounding industries to develop rapidly. The semiconductor industry, as predicted by Moore's Law, has doubled the number of transistors per 18 months on the integrated circuit, and the semiconductor process has also been 0.18 micro-meters in 1999, 2001. 0.13 microns, 90 nanometers (nm) in 2003 (〇.〇9 microns), entered the 65nm (0.065 micron process) in 2005 and moved towards 45nm. Therefore, with the advancement of the semiconductor process and the miniaturization of the microelectronic components, the density of the semiconductor elements on a single wafer is becoming larger and larger, and the spacing between the components is becoming smaller and smaller. This makes the contact hole etch process more difficult to fabricate. In the prior art, the contact hole is formed by using the photoresist layer as a mask for etching the underlying dielectric layer', and in the process of 45 nm (nm), the pitch of the contact hole etching (pitch, ie, two adjacent contacts) The distance between the center points of the holes must be less than 155 nm, and the after development inspect critical dimension (ADICD) must be approximately 70 to 80 to 1333239 meters. As far as the current yellow light machine technology is concerned, it is impossible to complete the contact hole with a pitch of less than 155 nm in one exposure process t. Therefore, it is common practice in the industry to use two masks to expose the photoresist layer twice. An etching is performed again to pattern the contact holes. However, when the spacing of the contact holes is less than 14 nanometers, even if the above two exposures and one etching process are used, the yellow light machine cannot be defined too small when performing the second exposure development. The contact hole pattern is not able to make a contact hole having a contact hole pitch of less than 14 nanometers. Therefore, how to make a contact hole with a contact hole etching distance of less than 14 nanometers is an important issue in this field. SUMMARY OF THE INVENTION The present invention provides a method of forming a contact hole to solve the above problems. σ A preferred embodiment of the present invention provides a method of forming a contact hole comprising: providing a semiconductor substrate, sequentially covering the same - (4) a stop layer, - an interlayer dielectric layer, and a first Schiffon photoresist layer . Forming a first photoresist pattern over the first shi-shi photoresist layer and then using the first photoresist pattern as an etch mask to perform a first-to-last process to form a plurality of first openings in the shi-shi photoresist layer . After removing the first photoresist pattern 1 , a second photoresist pattern is formed over the photoresist layer, and the second photoresist pattern is used as a gate mask, and the second rice etching process is performed on the stone-containing photoresist layer to form a plurality of photoresist patterns. The second opening is etched by using a photoresist layer having a first and a second opening as an etch mask to form a contact hole in the interlayer dielectric layer and the etch stop layer. Another preferred embodiment of the present invention provides a method of forming a contact hole comprising providing a semiconductor substrate sequentially overlying an interlevel dielectric layer, a first Schottky photoresist layer. Forming a first photoresist pattern over the first shi-shi photoresist layer, and using the first photoresist pattern as an etch mask, performing a first etch process to form a plurality of first photo-shield layers An opening removes the first photoresist pattern. Then, using the first opening as an etch mask, performing an etching process to form a plurality of first contact holes in the interlayer dielectric layer and removing the first germanium-containing photoresist layer, and forming a second tin-containing light over the interlayer dielectric layer The resist layer forms a second photoresist pattern over the second germanium-containing photoresist layer, and uses the second photoresist pattern as an etch mask to perform an etching process to form a plurality of second contact holes in the interlayer dielectric layer. Compared with the prior art, the prior art utilizes a double exposure process and is exposed on the same photoresist layer, so that the exposure machine fails because the current exposure machine cannot define a small contact hole pattern. However, in the present invention, the present invention directly performs an etching process after first performing an exposure process to transfer the pattern resulting from the first exposure to a germanium-containing photoresist layer or an interlayer dielectric layer. Next, a photoresist layer is reformed, another exposure is performed at different locations, and the new pattern is transferred to the germanium containing photoresist layer or the interlayer dielectric layer. This double exposure, two etching method can form a structure in which the contact etching is less than 140 nm. Of course, the present invention can also be applied to two or more exposures and two or more etchings, as permitted by the exposure machine 7 1333239, to form contact holes having a smaller pitch. [Embodiment] Please refer to Figs. 1 to 7, and Fig. 1 to Fig. 7 are schematic views showing a process of etching a contact etch stop layer (CESL) according to a first embodiment of the present invention. As shown in FIG. 1 , a substrate 102 such as a wafer or a silicon-on-insulator (SOI) semiconductor substrate is first provided, and various components such as a MOS transistor are formed on the surface of the substrate 102. Then, a contact hole etch stop layer 1〇4, an interlayer dielectric layer (ILD) 106, and a three-layer stacked layer Π4 are sequentially formed on the substrate 102. The three-layer stacked layer 114 includes a bottom anti-reflective coating (BARC) 108, a shi-shi resist layer 11 〇, and a 193 (nm) nano-resist layer 112. Among them, the antireflection underlayer 1 8 can be formed by using a 365 nm photoresist layer, i.e., a photoresist layer belonging to the i_Hne exposure range. The 193 nm photoresist layer 112 is in the deep ultraviolet light exposure range. In addition, the interlayer dielectric layer 106 may comprise an undoped germanium oxide layer, a doped oxygen layer, such as a tetetra-ethyl-ortho-silicate (TEOS) layer, or a borophosphonite glass. , fluoroantimony layer 'phosphorus oxide layer or boron oxynitride layer. Moreover, a thin film deposition technique such as a plasma enhanced chemical vapor deposition process can be used to form the interlayer dielectric layer 106. In the first embodiment, the contact hole stop layer 104 has a thickness of 850 angstroms (in) and one layer. The thickness of the electric layer 1 〇 6 is 3000 angstroms, the thickness of the anti-reflective underlayer 1 〇 8 is 18 〇〇 Å and contains 8 1 333 239 矽 the thickness of the photoresist layer 110 is 800 angstroms and the thickness of the 193 nm photoresist layer 112 is 2200. Ai. An exposure process and a development process are then performed to pattern the 193 nm photoresist layer 112. Next, please refer to FIG. 2, using the patterned 193 nm photoresist layer 112 as a mask, performing an etching process, and adjusting the etching gas ratio or pressure, power and other parameters to pattern the germanium-containing photoresist layer 110 to obtain a number. A ladder-shaped opening 202. The sides of each opening 202 have a taper 204 that is varied by adjusting the etch parameters to make the bottom of the opening 202 less wide than the top opening. Moreover, the depth of the opening 202 is only 500A, so the bottom of the opening 202 does not expose the anti-reflective underlayer 108, which protects the structural integrity of the anti-reflective underlayer 108. Thereafter, the remaining 193 nm photoresist layer 112 is removed. Please refer to Figure 3. Next, a 193 nm photoresist layer 312 is reformed, and the newly formed 193 nm photoresist layer 312 fills the opening 202 as shown in FIG. An exposure and development process is then performed to pattern the 193 nm photoresist layer 312. Referring to FIG. 4, the 193 nm photoresist layer 312 is patterned as a mask, and another etching process is performed to pattern the germanium-containing photoresist layer 110 again to form a plurality of openings 402. The width of the bottom of the opening 402 is also smaller than the opening, so the sides of the opening 402 have a bevel 204. Moreover, the opening 202 has a depth of only 500 A, so the bottom of the opening 202 does not expose the anti-reflective underlayer 108 to protect the structure of the anti-reflective underlayer 108. Thereafter, the remaining 193 nm 9 1333239 photoresist layer 312 is removed. The eye is directly etched with reference to the fifth object', and the etched photoresist layer 11 直接 is directly etched until the photoresist layer m is passed through, and the antireflection underlayer (10) is violent. Next, continue against the reflective underlayer (10) until the interlayer dielectric layer 106 is exposed. Thereafter, using the anti-reflective underlayer 1 已经 8 which has been patterned as a mask, the layer Μ dielectric I 1 〇 6 is left to expose the contact hole etch stop layer 1 〇 4 by a --touch process. At this time, the germanium-containing photoresist layer η has been consumed, and the anti-reflective underlayer 108 has also been worn out a lot. Please refer to Figure 6 to remove the remaining anti-reflective underlayer 1〇8. Next, referring to FIG. 7, the patterned interlayer dielectric layer 1〇6 is used as a mask, and a break through etching process is performed to pattern the contact hole etch stop layer 104 to form a pattern as shown in FIG. The contact hole 7 〇 2 is shown. Please refer to Figs. 8 to 15, which are schematic views showing the process of etching the contact hole etch stop layer of the second embodiment of the present invention. The difference between the second embodiment and the first embodiment is that the second embodiment has a metal compound mask layer 1602 between the interlayer dielectric layer 106 and the anti-reflection underlayer 1〇8. As shown in FIG. 8, first, a substrate 102 having a plurality of elements such as a MOS transistor is formed, and then a contact hole etch stop layer 104 and an interlayer dielectric layer 1 〇 6 are sequentially formed over the substrate 102. A metal compound mask layer 1602, a three-layer stacked layer 114. The three-layer stacked layer 114 includes 1333239 having an anti-reflective underlayer 108, a shi-shi photoresist layer 110, and a 193 nm photoresist layer 112. The anti-reflective underlayer 108 can be a 365 nm photoresist layer, and the 193 nm photoresist layer 112 is a deep ultraviolet exposure range. In addition, in the second embodiment, the contact hole etch stop layer 104 has a thickness of 850 angstroms (A), the interlayer dielectric layer 106 has a thickness of 3000 angstroms, and the anti-reflective underlayer 108 has a thickness of 1800 angstroms. The photoresist layer 110 has a thickness of 800 angstroms and a 193 nm photoresist layer 112 has a thickness of 2200 angstroms. First, an exposure process and a development process are performed to pattern the 193 nm photoresist layer 112. Next, referring to FIG. 9, the patterned 193 nm photoresist layer 112 is used as a mask, and an etching process is performed to pattern the germanium-containing photoresist layer 110. The patterned germanium-containing photoresist layer 110 formed after etching has a plurality of trapezoidal openings 202, and the bottom of the opening 202 has a smaller width than the top opening and a side edge having an oblique angle 204. Moreover, the depth of the opening 202 is only 500A, so the bottom of the opening 202 does not expose the anti-reflective underlayer 108 to protect the structure of the anti-reflective underlayer 108. Thereafter, the remaining 193 nm photoresist layer 112 is removed. Referring to Figure 10, a 193 nm photoresist layer 312 is then formed, and the newly formed 193 nm photoresist layer 312 fills the opening 202. Then, an exposure and development process is performed to pattern the 193 nm photoresist layer 312. Then, referring to FIG. 11, the 193 nm photoresist layer 312 is patterned as a mask, and another etching process is performed to pattern the germanium-containing photoresist layer 110 again to form a plurality of openings 402. The sides of the opening 402 have a slope. The corner 204, and the width of the bottom of the opening 402 is also smaller than the opening. In addition, the depth of the opening 202 1333239 is also only 5GGA, so the bottom of the opening σ 2G2 does not expose the anti-reflection underlayer 108 to protect the structure of the anti-reflection underlayer 1〇8. Thereafter, the remaining 193 nm photoresist layer 312 is removed. The mouth of the month is referred to the 12th item. Directly on the stone-like photoresist | 11〇, the rice is exposed until the anti-reflective bottom layer (10) is exposed. Next, the Lishi-shi resist layer after the profit is treated as a silver engraved mask 'anti-reflective bottom layer (10) for a process until a metal compound mask layer is exposed. After that, the patterned anti-reflective underlayer (10) is used as a fresh, and the metal compound mask layer is etched to pattern the gold (10)2. Thereafter, all of the photoresist layer above the gold consuming mask layer 1602 is removed. Referring to Fig. 13', the patterned dielectric layer 2 is used as a mask, and the interlayer dielectric layer (10) is subjected to _ to form a patterned interlayer dielectric layer 106 and expose the contact hole stop layer. Fig., the patterned metal compound mask layer is removed. H) 6 is used as a mask: In Fig. 15, the patterned interlayer dielectric layer is formed into a contact hole 702 as shown in Fig. 15. π refers to the 16th to 23th drawings, and the second to the figure is a schematic diagram of the process of the _contact_etch stop layer of the present example. If the first = no, the ground is 'provided', the base 102 of each of the elements 1333239, such as a MOS transistor, has been formed, and the substrate 102 has a contact etch stop layer 104, an interlayer dielectric layer 106, and a layer. Three layers of stacked layers 114. The three-layer stacked layer 114 includes an anti-reflective underlayer 108, a yarn-containing photoresist layer 110, and a 193 nm photoresist layer 112. The anti-reflective underlayer 108 can be a 365 nm photoresist layer 108. In addition, in the third embodiment, the contact hole etch stop layer 104 has a thickness of 850 angstroms (person), the interlayer dielectric layer 106 has a thickness of 3000 angstroms, and the first anti-reflective underlayer 108 has a thickness of 1800 angstroms. The photoresist layer 110 has a thickness of 800 angstroms and a 193 nm photoresist layer 112 has a thickness of 2200 angstroms. First, an exposure process and a development process are performed to pattern the 193 nm photoresist layer 112. Next, referring to FIG. 17, using the patterned 193 nm photoresist layer 112 as a mask, an etching process is performed to pattern the germanium-containing photoresist layer 110, and the patterned germanium-containing photoresist layer 110 formed after etching has A plurality of ladder shaped openings 202. The sides of each opening 202 have a bevel 204 and the width of the bottom of the opening 202 is smaller than at the top. In addition, the depth of the opening 202 is only 500A, so the bottom of the opening 202 does not expose the anti-reflective underlayer 108 to protect the structure of the anti-reflective underlayer 108. Thereafter, the remaining 193 nm photoresist layer 112 is removed. Referring to FIG. 18, next, the patterned photoresist layer 110 is used as a mask to etch the germanium-containing photoresist layer 110 until the anti-reflective underlayer 108 is exposed. The etching process at this stage causes the original photoresist layer 110 having a thickness of 800 A to be consumed to a thickness of only 500 Å. It is important to note here that since the width of the bottom of the opening 202 is smaller than that of the top opening, the width of the etching at this stage 13 1333239 is based on the width of the bottom of the opening 202. Thereafter, the etch-resistant phenus-containing photoresist layer 110 is continued as a mask, and the reflective underlayer 1 〇 8 is etched until the interlayer dielectric layer 1 〇 6 is exposed to pattern the anti-reflective underlayer 108. Generally, after the etching process of the anti-reflective underlayer 1〇8, the germanium-containing photoresist layer 11〇 has been completely consumed by the etching process. Referring to Figure 19, the patterned anti-reflective underlayer ι08 is used as a mask to etch the interlayer dielectric layer 106 until the contact hole etch stop layer 104 is exposed and a plurality of openings 1902 are formed. Next, the anti-reflection underlayer 1 〇 8 above the interlayer dielectric layer 106 is removed. Please refer to FIG. 20' to form an anti-reflection underlayer ι2 〇 2, a ytterbium-containing photoresist layer 12 〇 4 and a 193 nm photoresist layer 1206 over the patterned interlayer dielectric layer 106, and anti-reflection. The bottom layer 12〇2 fills each opening 1902. Next, as in Fig. 16, the 193 nm photoresist layer 1206 is subjected to an exposure process and a developing process to pattern the 193 nm photoresist layer 1206' but the exposed areas thereof are different from those of the 16th. The next steps are as in the steps from the above to the 19th. The patterned 193 nm photoresist layer 12 (6) is used as a mask to perform a etch process to pattern the three photoresist layers 12〇4. Next, the patterned shi-shaden photoresist layer 1204 is used as a mask, and the 丨a is patterned to contain the photoresist layer 1204 until the anti-reflective underlayer 1202 is exposed. Thereafter, the etchback continues to utilize the etched ruthenium-containing photoresist layer 12〇4 as a mask, and the anti-reflection Mn τ paper layer 1202 is etched until the interlayer dielectric 1323239 is exposed to pattern the anti-reflection underlayer 1202. . Then, the interlayer dielectric layer 106 is etched with the patterned anti-reflective underlayer 1202 as a mask until the contact hole etch stop layer 104 is exposed. At this time, the germanium-containing photoresist layer 1204 has been consumed in the etching process, but some anti-reflection underlayer 1202 remains, forming a structure as shown in FIG. Referring to Figure 22, the anti-reflective underlayer 1202 over the interlayer dielectric layer 106 is removed. Then, referring to FIG. 23, using the patterned interlayer dielectric layer 106 as a mask, a breakthrough etching process is performed to pattern the contact hole etch stop layer 104 to form a contact hole 702 as shown in FIG. . Compared with the prior art, the prior art utilizes a double exposure process and is exposed on the same photoresist layer, so that the exposure machine fails because the current exposure machine cannot define a small contact hole pattern. However, in the present invention, the present invention directly performs an etching process after first performing an exposure process to transfer the pattern resulting from the first exposure to a germanium-containing photoresist layer or an interlayer dielectric layer. Next, a photoresist layer is reformed, another exposure is performed at different locations, and the new pattern is transferred to the germanium containing photoresist layer or the interlayer dielectric layer. This double exposure, two etching method can form a structure in which the contact etching is less than 140 nm. Of course, the present invention can also be applied to two or more exposures and two or more etchings in the case where the exposure machine permits, to form contact holes having a smaller pitch. 15 1333239 The above is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the present invention should be covered by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1 to 7 are schematic views showing the process of etching an etch stop layer of the first embodiment of the present invention. 8 to 15 are schematic views showing the process of etching the contact hole etch stop layer in the second embodiment of the present invention. 16 to 23 are schematic views showing the process of the stop layer of the button-shaped contact hole of the third embodiment of the present invention. [Main component symbol description] Substrate contact hole residual stop layer interlayer dielectric layer anti-reflection underlayer germanium photoresist layer 193nm photoresist layer three-layer stack layer opening bevel contact hole metal compound mask layer 102 104 106 108 ' 1202 110 , 1204 112 , 312 , 1206 , 1802 114 202 , 402 204 702 1602