經濟部中央標準局貝工消费合作社印製 A7 B7 五、發明説明（丨） ㈠技術領域 ·. 本發明是關於積體電路雙井區製程（twin-WQll process)之對準標記（alignment mark)的製造方法，特 別是關於利用雙氮化砂触刻（double nitride etching) 來製造對準標記的方法。 (二） 發明背景 在積體電路的製造過程，會產生起伏不平的地形地勢， 這些起伏不平的地形地勢在矽半導體基板上彷彿一個標記 (mark)，吾人可利用「標記」作爲微影曝光製程之不同層 次之光罩的對準（alignment)。例如，隔離電性元件之場 氧化層突出矽半導體基板表面大約1000到3000埃之間， 便可作爲後續複晶矽閘極之微影曝光製程之對準標記。 問題是，傳統雙井區積體電路製程（twin-well process)所形成之地形地勢在N井區跟P井區之間呈現 一高低差，而由於光學效應之影響將造成光阻微距 (critical dimension)不易控制。另外以目前半導廣泛應 用的Nikon步進對準機而言又必須考量其對準標記製作，藉 以製程步驟改善達到一目的。 (三） 發明的簡要說明 本發明之主要目的是提供一種積體電路之對準標記 (alignment mark)的製造方法。 此方法首先在P型矽半導體基板上形成第一氧化矽墊 層和第一氮化矽，接著，利用微影技術形成第一光阻圖 案，並以所述第一光阻圖案作爲蝕刻護罩（etching mask)，利用電漿蝕刻技術蝕去所述第一氮化矽以形成 (請先閱讀背面之注意事項再填寫本頁) -裝 訂 本紙張尺度逋用中國國家橾牟(〇奶）八4規格（210\297公釐) 83. 3. 10,000 經濟部中央樣準局員工消費合作社印製 A7 B7 五、發明説明（>) 「第一氮化砂圖案」。然後，以所述第一光阻圖案作爲離 子佈植護罩（implantatioii mask)，透過「第一氧化砂墊 層」進行N型離子佈植，以在所述P型矽半導體基板形 成N摻雜區域（N-doped region)，並去除所述第一光阻 圖案。 接著，利用微影技術形成第二光阻圖案，並以所述第 二光阻圖案作爲蝕刻護罩，利用電漿蝕刻技術蝕去所述 「第一氮化矽圖案」以形成第二氮化矽圖案，所述第二氮 化矽圖案之位置介於N并區跟P井區之間。然後，以所 述第二光阻圖案作爲離子佈植護罩，透過「第一氧化矽墊 層」進行P型離子佈植，以在所述P型矽半導體基板形 成P慘雜區域（P-doped region)，並去除所述第二光阻 圖案。 接著，在高溫的環境下進行井區驅入步驟，以活化所 述N摻雜區域與P摻雜區域，以分別形成N井區跟P 井區（N-well and P-well)，然後去除所述「第二氮化矽 圖案」。在井區驅入過程會形成氧化物，使得在所述τ第 二氮化砂圖案」跟「氧化物」之間形成具高度之階梯係因 氮化矽會抑制二氧化矽之生長，故形成一階梯以作爲對準 標記（alignment mark)，作爲後續微影曝光對準之用。 接著，形成第二氧化矽墊層和第三氮化矽，接著，利 用微影技術形成第三光阻圖案，並以所述第三光阻圖案作 爲蝕刻護罩，利用電漿蝕刻技術蝕去N井區跟P井區之 間的所述第三氮化矽以露出所述第二氧化矽墊層，以形成 「第三氮化矽圖案」。然後，在含氧氣的高溫環境中，以 (請先閲讀背面之注意事項再填寫本頁) .裝. 訂 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 經濟部中夬標隼局員工消費合作杜印製 A7 _B1 五、發明説明（》） 所述「第三氮化砂圖案」作爲氧化護罩（oxidation ®ask)，在露出之所述第二氧化矽墊層區域形成場氧化層 (field oxide)。 由於所述「第二氮化矽圓案」之位置對稱的介於N摻 雜區域跟P摻雜區域之間，故形成場氧化層後，所述N 井區跟P井區以場氧化層作爲對稱中心，呈現對稱一致的 地形地勢。場氧化層可以作爲一個理想的微影製程之對準 檩記（alignment mark)，供後續製程對準之用。 (四） β示的簡要說明 圖一到圖十一是本發明之實施例的製程剖面示意圖。 (五） 發明的詳細說明 以下利用Ρ型矽半導體基板作爲實施例說明本發明之 方法，但本發明之方法可以延伸推廣到用Ν型矽半導體基 板。 請參考圖一、圖二和圖三。首先，在P型矽半導體基 板1上形成第一氧化矽墊層3和第一氮化砂5，如圖一 所示，接著，利用微影技術形成第一光阻圖案7，如圖二 所示，並以所述第一光阻圖案7作爲蝕刻護罩，利用電獎 蝕刻技術蝕去所述第一氮化矽5以形成「第一氮化矽圖案 Μ」，然後，以所述第一光阻圖案7作爲離子佈植護罩透 過「第一氧化矽墊層3」進行N型離子佈植9，以在所述 P型矽半導體基板1形成N摻雜區域11，如圖三所示。 所述「第一氧化矽墊層3」通常是以熱氧化技術形 成’氧化溫度約1000°C，其厚度介於320到380埃之 間。所述「第一氮化矽5」是以低壓化學氣相沉積法形 (請先閱讀背面之注意事項再填寫本頁) 裝- 訂 本紙張尺度適用中國國家榡牟（CNS ) M规格（21〇x；297公釐） 經濟部中央標準局負工消费合作社印裝 A7 B7 五、發明说明（/) 成，其反應溫度約760°C，反應壓力約350毫托爾，反應 氣體是SiH2Cl2和· NH3，其厚度介於1350到1650埃之 間。形成N摻雜區域11之N型離子通常是磷（P31)， 其離子佈植劑量介於1E11到1E13原子/平方公分之 間，離子佈植能量介於50到150 Kev之間。另外，對所 述「第一氮化矽5」之電漿蝕刻，可以利用磁場增強式活 性離子式電漿蝕刻技術（MERIE)或電子迴旋共振電漿蝕刻 技術（ECR)或傳統的活性離子式電漿蝕刻技術（RIE)， 通常是利用磁場增強式活性離子式電漿蝕刻技術，其電獎 反應氣體是CF4、CHF3、Ar和02氣體。 請參考圖四、圖五和圖六。利用氧氣電漿和硫酸溶液去 除所述第一光阻圖案7後，接著，利用微影技術形成第二 光阻圖案13，如圖四所示，並以所述第二光阻圖案13作 爲蝕刻護罩，利用電漿蝕刻技術蝕去所述「第一氮化矽圖 案5A」以形成第二氮化矽圖案5B，如圖五所示，所述 「第二氮化矽圖案5B」之位置將介於N井區跟P井區之 間。然後，以所述第二光阻圖案13作爲離子佈植護罩， 透過「第一氧化矽墊層3」進行P型離子佈植15，以在 所述P型矽半導體基板1形成P摻雜區域17 (P-doped region)，如圖六所示。最後，再利用氧氣電漿和硫酸溶 液去除所述第二光阻圖案13。 形成P摻雜區域17之P型離子通常是硼（B")， 也可以是二氟化硼（BF2)，其離子佈値劑量介於1E12到 1E13原子/平方公分之間，其離子佈値能量則介於1〇到 80 Kev之間。對所述「第一氮化矽圖案5A」之電漿蝕 (請先閲讀背面之注意事項再填寫本頁) -裝. 訂 本紙張尺度適用中國國家棣準（CNS ) A4规格（210X297公釐） 83. 3.10,000 經濟部中失橾準扃員工消费合作社印装 303495 五、發明説明（5") 刻，也是利用磁場增強式活性離子式電漿蝕刻技術’其電 漿反應氣體是CF4、CHF/、Ar和02氣體。 請參考圖七。接著’在含氮氣和氧氣的高溫的環境下進 行井區驅入步驟（well drive-in) ’以活化所述N摻雜 區域11與P摻雜區域Π，以分別形成N井區11A跟 P井區17A (N-well and P-well) ’另一方面，在井區 驅入過程會形成氧化物〗9，其厚度介於2000到2400埃 之間，如圖七所示。請注意，完成井區驅入後’在所述 「第二氮化砂圖案5B」跟「氧化物19」之間形成了高度 約1000埃的階梯99，如圖七所示，所述「階梯99」附 近呈現對稱一致的地形地勢，能作爲對準標記（aHgnment mark)，作爲後續微影曝光對準之用，這是本發明之關 鍵。 請參考圖八、圖九和圖十。利用氧氣電漿或磷酸溶液去 除所述「第二氮化矽圖案5B」後，接著形成第二氧化矽墊 層21和第三氮化矽23，如圖八所示，然後，利用微影技 術形成第三光阻圖案25，如圖九所示，並以所述第三光阻 圖案25作爲蝕刻_罩，利用電漿蝕刻技術蝕去N井區 11A跟P井區ΠΑ之間的所述第三氮化矽23以露出N 井區11A跟P井區ΠΑ之間的所述第二氧化矽墊層 21 ’以形成「第三氮化矽圖案23A」，再利用氧氣電漿和 硫酸溶液去除所述第三光阻圖案25，如圖十所示。 同樣的，所述「第二氧化矽墊層21」也是以熱氧化技 術形成，氧化溫度約l〇〇〇°C，其厚度介於320到380埃 之間。所述「第三氮化矽23」是以低壓化學氣相沉積法 (請先閱请背面之注意事項再填寫本頁) 裝 訂 本紙張尺度逋用中國國家梂牟（CNS ) A4«息（21 〇 X 297公羞） 經濟部中央橾準局員工消费合作社印製 A7 B7 五、發明説明（b ) 形成，其反應溫度約760°C，反應壓力約350毫托爾，反 應氣體是SiH2Cl2和NH3，其厚度介於1350到1650埃 之間。而對所述「第三氮化矽23」之電漿蝕刻，也是利用 磁場增強式活性離子式電漿蝕刻技術，其電漿反應氣體是 CF4、CHF3、Ar 和 02 氣體。 請參考圖十一。然後，在含氧氣的高溫環境中，介於 925到975°C之間，以所述「第三氮化砂圖案23A」作爲 氧化護罩，在露出之所述第二氧化矽墊層21區域熱氧化 所述P型矽半導體基板1以形成場氧化層27，其氧化時 間介於150到200分鐘之間，所形成場氧化層27之厚 度介於4000到6000埃之間，利用磷酸溶液去除所述 「第三氮化矽圖案23A」和利用氫氟酸溶液去除所述「第 二氧化矽墊層21」後，如圖十一所示。 請注意，由於所述「第二氮化砂圖案5B」之位置對稱 的介於N摻雜區域11跟P摻雜區域17之間，故形成 場氧化層27後，所述N井區11A跟P井區ΠΑ以所 述場氧化層27作爲對稱中心，呈現對稱一致的地形地 勢。所述場氧化層27作爲後續製程之準標記（alignment mark) 〇 以上係以最佳實施例來述本發明，而非限制本發 明，並且，熟知半導體技藝之人士皆能明瞭，適當而作些 微的改變及調整，仍將不失本發明之要義所在，亦不脫離 本發明之精神和範圍。 本紙張尺度適用中國困家標準（CNS )八4规格（210Χ297公釐） 裝 訂 線 (請先W讀背面之注意事項再填寫本A7 B7 printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (丨) (1) Technical field ·. The present invention relates to the alignment mark of the twin-WQll process of integrated circuit Manufacturing method, in particular, a method for manufacturing alignment marks using double nitride etching. (2) Background of the invention In the manufacturing process of integrated circuits, there will be undulating topography, which is like a mark on a silicon semiconductor substrate. We can use "mark" as a lithography exposure process The alignment of the different levels of the photomask. For example, the field oxide layer of the isolation electrical device protrudes from the surface of the silicon semiconductor substrate by about 1000 to 3000 angstroms, which can be used as an alignment mark for the subsequent lithography exposure process of the polycrystalline silicon gate. The problem is that the topography created by the twin-well process in the traditional dual-well area presents a height difference between the N-well area and the P-well area, and the photoresist macro will be caused due to the effect of optical effects ( critical dimension) is not easy to control. In addition, with the Nikon step aligner widely used in the semiconductor industry, the alignment mark must be considered for the purpose of improving the process steps. (3) Brief description of the invention The main object of the present invention is to provide a method for manufacturing an alignment mark of an integrated circuit. In this method, a first silicon oxide pad layer and a first silicon nitride layer are formed on a P-type silicon semiconductor substrate, and then a first photoresist pattern is formed by using lithography technology, and the first photoresist pattern is used as an etching shield (Etching mask), using plasma etching technique to etch away the first silicon nitride to form (please read the precautions on the back before filling in this page) -The size of the bound paper uses the Chinese National Moumou (〇 奶) 8 4 Specifications (210 \ 297 mm) 83. 3. 10,000 A7 B7 printed by the Employee Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs V. Invention description (>) "First Nitride Sand Pattern". Then, using the first photoresist pattern as an ion implantation mask, performing N-type ion implantation through the "first oxide sand pad layer" to form N-doping on the P-type silicon semiconductor substrate Region (N-doped region), and remove the first photoresist pattern. Next, a second photoresist pattern is formed using photolithography technology, and the second photoresist pattern is used as an etching shield, and the "first silicon nitride pattern" is etched away using plasma etching technology to form a second nitride For the silicon pattern, the position of the second silicon nitride pattern is between the N parallel region and the P well region. Then, using the second photoresist pattern as an ion implantation shield, a P-type ion implantation is performed through the "first silicon oxide pad layer" to form a P doped region (P-) on the P-type silicon semiconductor substrate doped region) and remove the second photoresist pattern. Next, a well region driving step is performed under a high-temperature environment to activate the N-doped region and the P-doped region to form an N-well region and a P-well region (N-well and P-well), respectively, and then remove The "second silicon nitride pattern". During the driving process in the well area, oxide will be formed, so that a step with a high height is formed between the τ second nitride sand pattern ”and the“ oxide ”because silicon nitride will inhibit the growth of silicon dioxide. A step is used as an alignment mark for alignment of subsequent lithography exposures. Next, a second silicon oxide pad layer and a third silicon nitride layer are formed, and then, a third photoresist pattern is formed by using lithography technology, and the third photoresist pattern is used as an etching shield, which is etched away by plasma etching technology The third silicon nitride between the N-well region and the P-well region exposes the second silicon oxide pad layer to form a "third silicon nitride pattern". Then, in a high-temperature environment containing oxygen, please (please read the precautions on the back before filling out this page). Binding. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). Falcon Bureau ’s consumer cooperation du printing A7 _B1 V. Description of the invention (》) The “third nitride sand pattern” as an oxidation shield (oxidation ®ask) is formed in the exposed area of the second silicon oxide pad Field oxide layer (field oxide). Since the position of the "second silicon nitride round" is symmetrically between the N-doped region and the P-doped region, after the field oxide layer is formed, the N-well region and the P-well region are replaced by the field oxide layer As a center of symmetry, it presents a symmetrical and consistent topography. The field oxide layer can be used as an ideal alignment mark for the lithography process for subsequent process alignment. (4) Brief description of β Figures 1 to 11 are schematic cross-sectional views of the manufacturing process according to an embodiment of the present invention. (5) Detailed description of the invention The following uses the p-type silicon semiconductor substrate as an example to illustrate the method of the present invention, but the method of the present invention can be extended to use an N-type silicon semiconductor substrate. Please refer to Figure 1, Figure 2 and Figure 3. First, the first silicon oxide pad layer 3 and the first nitride sand 5 are formed on the P-type silicon semiconductor substrate 1, as shown in FIG. 1, and then, the first photoresist pattern 7 is formed using lithography technology, as shown in FIG. And using the first photoresist pattern 7 as an etching shield, the first silicon nitride 5 is etched away using an electric award etching technique to form a "first silicon nitride pattern M", and then, using the first A photoresist pattern 7 as an ion implantation shield performs an N-type ion implantation 9 through the "first silicon oxide pad layer 3" to form an N-doped region 11 on the P-type silicon semiconductor substrate 1, as shown in FIG. 3 Show. The "first silicon oxide pad layer 3" is usually formed by thermal oxidation technology. The oxidation temperature is about 1000 ° C, and the thickness is between 320 and 380 angstroms. The "First Silicon Nitride 5" is in the form of low-pressure chemical vapor deposition (please read the precautions on the back and then fill out this page). Binding-The size of the printed paper is applicable to the Chinese National Geographic (CNS) M specifications (21 〇x; 297 mm) A7 B7 printed by the Consumer Labor Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention description (/), its reaction temperature is about 760 ° C, reaction pressure is about 350 mTorr, reaction gas is SiH2Cl2 · NH3, with a thickness between 1350 and 1650 Angstroms. The N-type ions forming the N-doped region 11 are usually phosphorus (P31). The ion implantation dose is between 1E11 and 1E13 atoms / cm2, and the ion implantation energy is between 50 and 150 Kev. In addition, for the plasma etching of the "first silicon nitride 5", magnetic field enhanced active ion plasma etching technology (MERIE) or electron cyclotron resonance plasma etching technology (ECR) or traditional active ion type Plasma etching technology (RIE) is usually a magnetic field-enhanced active ion plasma etching technology, and its electric award reaction gases are CF4, CHF3, Ar and 02 gases. Please refer to Figure 4, Figure 5 and Figure 6. After removing the first photoresist pattern 7 with oxygen plasma and sulfuric acid solution, then, a second photoresist pattern 13 is formed by using lithography technology, as shown in FIG. 4, and the second photoresist pattern 13 is used as an etch Shield, using plasma etching technique to etch the "first silicon nitride pattern 5A" to form a second silicon nitride pattern 5B, as shown in FIG. 5, the position of the "second silicon nitride pattern 5B" It will be between Well N and Well P. Then, using the second photoresist pattern 13 as an ion implantation shield, a P-type ion implantation 15 is performed through the "first silicon oxide pad layer 3" to form P-doping on the P-type silicon semiconductor substrate 1 Region 17 (P-doped region), as shown in Figure 6. Finally, the second photoresist pattern 13 is removed using oxygen plasma and sulfuric acid solution. The P-type ions forming the P-doped region 17 are usually boron (B ") or boron difluoride (BF2), whose ion distribution dose is between 1E12 and 1E13 atoms / cm2, and their ion distribution The energy is between 10 and 80 Kev. Plasma erosion of the "First Silicon Nitride Pattern 5A" (please read the precautions on the back before filling in this page)-Packing. The size of this paper is applicable to China National Standard (CNS) A4 (210X297mm ) 83. 3.10,000 Printed by the Consumer Cooperatives of the Ministry of Economic Affairs 303495 V. Description of the invention (5 ") It also uses the magnetic field enhanced active ion plasma etching technology. The plasma reaction gas is CF4, CHF /, Ar and 02 gases. Please refer to Figure 7. Next, perform a well drive-in step under a high-temperature environment containing nitrogen and oxygen to activate the N-doped region 11 and the P-doped region Π to form N well regions 11A and P, respectively Well area 17A (N-well and P-well) 'On the other hand, oxides are formed during the drive-in process of the well area9, with a thickness between 2000 and 2400 Angstroms, as shown in Figure 7. Please note that after completion of the well drive-in, a step 99 with a height of about 1,000 angstroms is formed between the "second nitride sand pattern 5B" and the "oxide 19", as shown in FIG. 7, the "step Symmetrical and consistent topography near 99 "can be used as an alignment mark (aHgnment mark) and used for subsequent lithography exposure alignment. This is the key of the present invention. Please refer to Figure 8, Figure 9 and Figure 10. After removing the "second silicon nitride pattern 5B" with an oxygen plasma or phosphoric acid solution, a second silicon oxide pad layer 21 and a third silicon nitride layer 23 are formed, as shown in FIG. 8, and then, using the lithography technique A third photoresist pattern 25 is formed, as shown in FIG. 9, and the third photoresist pattern 25 is used as an etching_mask to etch away between the N well area 11A and the P well area ΠΑ using plasma etching technology The third silicon nitride 23 exposes the second silicon oxide pad layer 21 'between the N-well region 11A and the P-well region ΠA to form a "third silicon nitride pattern 23A", and then uses oxygen plasma and sulfuric acid solution The third photoresist pattern 25 is removed, as shown in FIG. Similarly, the "second silicon oxide pad layer 21" is also formed by thermal oxidation technology, the oxidation temperature is about 1000 ° C, and the thickness is between 320 and 380 angstroms. The "third silicon nitride 23" is a low-pressure chemical vapor deposition method (please read the precautions on the back and then fill out this page). The size of the bound paper is based on China National Amulet (CNS) A4 "Interest (21 〇X 297 public shame) A7 B7 printed by the Employee Consumer Cooperative of the Central Department of Economics of the Ministry of Economic Affairs 5. Description of the invention (b) Formed, its reaction temperature is about 760 ° C, reaction pressure is about 350 mTorr, reaction gases are SiH2Cl2 and NH3 , Its thickness is between 1350 and 1650 Angstroms. The plasma etching of the "third silicon nitride 23" also uses magnetic field enhanced active ion plasma etching technology, and the plasma reaction gases are CF4, CHF3, Ar and 02 gases. Please refer to Figure 11. Then, in a high-temperature environment containing oxygen, between 925 and 975 ° C, using the "third nitride sand pattern 23A" as an oxidation shield, in the exposed area of the second silicon oxide pad layer 21 The P-type silicon semiconductor substrate 1 is thermally oxidized to form a field oxide layer 27, and the oxidation time is between 150 and 200 minutes. The thickness of the formed field oxide layer 27 is between 4000 and 6000 angstroms, which is removed with a phosphoric acid solution After the "third silicon nitride pattern 23A" and the "second silicon oxide pad layer 21" are removed with a hydrofluoric acid solution, as shown in FIG. Please note that since the position of the "second nitride sand pattern 5B" is symmetrically between the N-doped region 11 and the P-doped region 17, after the field oxide layer 27 is formed, the N-well region 11A and In the well P area, the field oxide layer 27 is used as the center of symmetry, and the terrain is symmetrical and consistent. The field oxide layer 27 is used as an alignment mark for subsequent processes. The above describes the present invention in the preferred embodiments, but does not limit the present invention. Moreover, those skilled in the art of semiconductors will be able to understand it and make some appropriate changes. The changes and adjustments will not lose the essence of the present invention, and will not deviate from the spirit and scope of the present invention. The size of this paper is applicable to the China Sleepy Family Standard (CNS) 84 specifications (210Χ297mm) binding line (please read the precautions on the back before filling in this