TW439192B - Fabrication method of shallow trench isolation - Google Patents

Abstract

A fabrication method of forming shallow trench isolation on semiconductor substrate is provided, which comprises: at first, providing a semiconductor substrate, and dividing this semiconductor substrate into the adjacent first region and the second region; then, forming the mask layer on the semiconductor substrate, and etching the mask layer to expose part of the upper surface of the semiconductor substrate; then, forming the first photoresist layer to cover the second region, and exposing the first region; then, proceeding the ion doping process to form the first doped region on part of the exposed surface of the semiconductor substrate; after removing the first photoresist layer, forming the second photoresist layer to cover the first region, and exposing the second region; then, proceeding the ion doping process to form the second doped region on the surface of the exposed semiconductor substrate; after removing the second photoresist layer, performing an etching process on the semiconductor substrate to form a trench in the semiconductor substrate, wherein the trench sidewall adjacent to the bottom of the mask layer has some portion of the remained first doped region and the second doped region; and subsequently, forming the shallow trench isolation in the trench.

Description

43 91 92 A7 ---------- V. Description of the invention () Invention Gu M: The invention relates to a semiconductor process for a shallow trench isolation structure, and particularly relates to the formation of a dopant over the sidewall of the trench isolation structure. The method of miscellaneous areas. / 〆 Background of the Invention: With the advancement of the semiconductor industry to ultra-large integrated circuits (Ulsi), the dimensions of metal oxide half field-effect transistors (MOS) have been shrinking, making the performance of MOS devices often impossible. Effectively improve, and its related processes are more complicated and difficult. Especially when the size of the semiconductor device is reduced to less than 0.25 / xm, many effects that can be ignored or inconspicuous in the larger size will cause a significant decrease in the yield and reliability of the manufactured device. For example, when the active area of a semiconductor device is separated, the edge shape of the shallow trench isolation (STI) produced will cause a MOS device on the active area and cause leakage current. {Please read the precautions on the back before filling out this page.) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to the first figure, which shows the top view of semiconductor wafers in the current semiconductor-related processes. The rectangular structure 10 is composed of a polycrystalline silicon layer, and is used as a gate structure of a metal-oxide-semiconductor field-effect transistor (MOS) in a semiconductor device. As for the rectangular area 12, it represents the active area when defining the MOS device. It should be noted that, for a transistor structure, the source and drain structures are formed in the area 12, and the part not covered by the gate structure 10 is applicable to the paper scale __ _ China National Standard (CNS) A4 specification (210 X 297 mm) 4 3 91 9 2 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (the width L of the gate structure 10 can often be used to define the formation The channel length of the transistor element. As for the width W of the rectangular region 12 which defines the active region, it also indicates the width of the transistor element. Next, please refer to the second figure, which is a semiconductor wafer The cross-sectional view shows a cross-sectional view cut along the BB and line segments in the first figure. The full picture of the defined transistor structure can be clearly seen from the second figure. Among them, the gate structure 10 is located in the semiconductor substrate 14 Top surface. At the same time, in the semiconductor substrate on both sides of the gate structure 10, doped regions 16, 17 are defined as the drain / source, respectively. The doped region 16 passes through the gate structure. ίο, to The length of the miscellaneous region 17 is exactly the length 12L of the active region 12 in the first figure. Similarly, 'please refer to the third circle'. The figure also shows the cross section of the semiconductor wafer cut along the first AA 'line segment. Figure. As the above gate structure 10 is located on the upper surface of this semiconductor substrate 丨 4. As for the semiconductive substrate 14, two trench isolation structures 18 are formed to effectively determine the activeness of the transistor component. Area, wherein the width 12W between the two trench isolation structures 18 is the width of the active area shown in the first figure—in general, due to the gate junction 10 and the semiconductor substrate 14 located in the active area 12, The required M0s transistor will be either the manufactured trench isolation structure 18, the semiconductor substrate located therebetween, or the gate structure 10 formed thereon. Performance affects. This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) ---; 1 '-^ --- ^-^ Wood -------- Order- -------- line 丨} (Please read the precautions on the back before filling this page)

V. Description of the Invention (Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, it should be noted that as the semiconductor device shrinks, the ratio of the active area width W to the transistor channel length L (W / L), also From 10: 1 'in the traditional control system, it is gradually reduced to the current 2: 1. That is, due to the continuous shrinking of the element size, the active area used to define a MOS transistor element has also been reduced, which also makes the above W / L ratio 値 decreases. However, with the decrease of W / L ratio 値, the semiconductor substrate 丨 4 and the trench isolation structure 丨 8 the shape of the indirect surface area 20 tends to have a great / influence on the transistor element manufactured D Among them, because the semiconductor substrate 14 in the junction area 20 can produce a tip discharge effect, it often causes a large crowded electric field here. Moreover, the junction area 2 at the edge of the active area 12 In this case, a parasitic corner transistor (parasitic corner transistor) is generated, which in turn causes current leakage and sub-threshold leakage. This has been borrowed in the prior art. It can be overcome by forming a doped region on the sidewall and bottom of the trench structure (such as US Patent 5,960,276 by Liaw). As shown in the fourth figure, after the trench structure is defined on the semiconductor substrate 14, it can be overcome. A thin oxide layer 21 is first formed on the surface of the trench structure. Then, an ion doping process is performed on the trench structure to form a doped region on the bottom and sidewall of the trench structure. Among them, the sidewall of the trench in the N-well is formed. With respect to the bottom, a p-type doped region 22 can be formed, and as for the sidewall and bottom of the trench in the P-well, an n-type doped region 24 is formed. In this way, the active region and the trench can be effectively reduced Isolate the electric field congestion on the interface of the structure and reduce the leakage at the beginning (sub_ This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 Kg)) (Please read the notes on the back and fill in before (This page) -ci ---- Order ---------- line — 4 3 91 92 € Α7 __Β7 V. Invention () threshold leakage) occurred. But it should be noted that the same as The above-mentioned doped region is formed at the bottom of the trench structure. After being connected to the sidewall, for the junction of N_well and p_well in the fourth figure, since the formed p-type doped region 22 and n-type doped region 24 are also connected here. Therefore, Often, the energy gap between the ρ_N interface of the N-well and the P_well will be reduced, which will lead to leakage. Aim of the invention and the object: The purpose of the present invention is to provide a transistor device capable of suppressing M 0 S transistor. A method for manufacturing a shallow trench isolation structure with an edge leakage current in an active region. Another object of the present invention is to provide a method for controlling an initial voltage of a parasitic corner transistor in an edge of an active region. Another object of the present invention is to provide a method for manufacturing a shallow trench isolation structure capable of adjusting the leakage current at the edge of the active area. II ----- b ···-~ '/ · II:-:, __ Party (please read the notes on the back before filling out this page) Order the printed copy of the staff consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The invention provides a method for forming a trench isolation structure on a semiconductor substrate. First, the semiconductor substrate can be divided into adjacent PMOS regions and NMOS regions, and the t PMOS region is used to define a PMOS element, and the NMOS region is used to define an NMOS element. Next, a nitride layer can be formed on the semiconductor substrate, covering the PMOS area and the paper size. Applicable to China National Standard (CNS) A4 (210 X 297 mm). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4ί 3 9 ί 92 Α7 ----_____ 5. Description of the invention () NMOS area. An oxide layer is formed on the nitride layer. Subsequently, the nitride layer and the oxide layer are etched to form an opening pattern in the nitride layer and the oxide layer, and an upper surface of a part of the semiconductor substrate in the PMOS region and the NMOS region is exposed. Next, a first photoresist layer is formed on the semiconductor substrate and the oxide layer to cover the NMOS region and expose the pMos region. In addition, the first photoresist layer and the oxide layer are used as a mask to perform an ion doping process on the semiconductor substrate so as to form an n-type doped region on a part of the semiconductor substrate exposed in the PMOS region. The doping process is performed at an inclined angle so that the n-type doped region can be extended into the semiconductor substrate at the bottom of the nitride layer. After removing the first photoresist layer, a second photoresist layer is formed on the semiconductor substrate and the oxide layer to cover the PMOS region and expose the NMOS region. By using the second photoresist layer and the oxide layer as a mask, an ion doping process is performed on the semiconductor substrate to form a P-type doped region on a portion of the semiconductor substrate exposed in the NMOS region. The ion doping process is also performed at an inclined angle, so that the P-type doped region can be extended into the semiconductor substrate at the bottom of the nitride layer. After removing the second photoresist layer, the oxide layer is used as an etching mask to perform an etching process on the semiconductor substrate so as to remove the Π-type doped regions and the p-type doped regions that are not covered by the nitride layer, and A trench is formed in the semiconductor substrate in the PMOS region and the NMOS region. Among them, the upper edge of the trench sidewall in the PMOS region has a partially remaining n-type doped region, and the upper edge of the trench sidewall in the NMOS region has a partially residual ρ-type doped region. Subsequently, A shallow trench isolation structure is formed in the trench. Brief description of the drawings: This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) -------- Order --- ------ Line I, 43 91 92 ^ A7 B7 The display is defined in the semiconductor display. According to the traditional technology, the display is based on the traditional technology. 5. Description of the invention () With the following detailed description combined with the attached diagram, it will be easy Understand the above and many advantages of this invention, among them: the first picture is the gate structure and active area of the top surface of the substrate of the semiconductor wafer; the second picture is the MOS transistor as defined by the cross section of the semiconductor wafer; The second figure is a cross-sectional view of a semiconductor wafer. The shallow trench isolation structure is used to define the active area of a MOS transistor. • The fourth figure is a cross-sectional view of a semiconductor wafer, showing the formation of a doped region in a shallow trench isolation structure according to traditional techniques. Bottom to reduce leakage at the beginning; the fifth figure is a cross-sectional view of a semiconductor wafer, showing the steps of forming an oxide layer, a nitride layer, an anti-reflection layer and a photoresist layer on a semiconductor substrate according to the present invention; FIG. 6 is a cross-sectional view of a semiconductor wafer, showing a step of etching a nitride layer and an oxide layer to expose a part of the surface of a semiconductor substrate according to the present invention; and FIG. 7 is a cross-sectional view of a semiconductor wafer, showing the progress according to the present invention. : Ion doping procedure to form a doped region on the surface of a semiconductor substrate; a delamination diagram is a cross-sectional view of a semiconductor wafer showing an ion doping procedure to form a doped region on the surface of a semiconductor substrate according to the present invention; The ninth figure of the step is a cross-sectional view of a semiconductor wafer, showing the application of the paper standard according to the present invention (Home Standard (CN & A4 size coffee x 297 gongchu (please read the note on the back before filling this page)) Ministry of Economy Intellectual Property Bureau Prints clothing for consumer cooperatives -------- Order --------- line I Ji ------- l · ---- A7 B7 Intellectual Property Bureau, Ministry of Economic Affairs Printed by Employee Consumer Cooperative 92. V. Description of Invention () Semiconductor substrates μ μ ,, Steps: In order to form a trench structure in the semiconductor substrate, the tenth picture is a cross section of a semiconductor wafer into shallow trenches. Steps in the trench · Xianding according to the invention Sub-doping procedure to form a well in a semiconductor substrate; the eleventh figure shows the semiconductor wafer, the sub-doping procedure, E. Well-type semiconductor: bottom: the essence; the step of the Gu crystal 1 on metal semiconductor substrates, to define the invention in detail, HF [; The present invention provides a new method structure. Among them, in the definition groove is accurate to the cocoon to do Ma Gu strike # 4 离 结 Λ A,. I / special Before we were in the + conductor substrate, the doped region was formed on the semiconductor substrate by the doping process of the red and red ions before doping. In this way, after the trench structure is defined, there is a residual knee region in the trench. In order to achieve effective suppression of secondary green, it is possible to achieve threshold leakage. ge) (Nursing fruit. For a detailed description of the present invention, please refer to the fifth figure as follows. In a preferred embodiment, there is a single substrate ^ substrate 1 (3b-in general, other types) The paper standard is applicable to the 1f1 National Standard (CNS) A4 specification (21〇X 297) 丨 丨 " ΓΙ!-'Llfl ·! Order _11! _! Line 1}, --- J ( Please read the note on the back before filling in this page) 4 3 9ΐ 92 &v; Α7 ____ Β7__ 5. Description of the invention () (Please read the notes on the back before filling this page) Semiconductor materials such as galliUm arsenide ), Germanium (germanium), or a silicon substrate (siHcO1 on insulator (SOI)) on the insulating layer can be used as a semiconductor substrate. In addition, the characteristics of the surface of the semiconductor substrate will not affect the present invention. To cause a special effect, the crystal orientation can also be selected as < 1 1 0 > or < 1 1 1 > It should be noted that the semiconductor substrate 100 can be distinguished into adjacent PMOS regions. 101 and NNiOS area 103. The PM0S area 101 is used to define the PMOS device on it, and the NMOS area 103 is used to define the NMOS device on it. Next, a first oxide layer 102, a nitride layer 104, a second oxide layer 106, and an anti-reflection layer 108 can be sequentially formed on the semiconductor substrate 100. Among them, the first oxide layer 1 The thickness of 02 is about 100 to 200 angstroms, which is used to prevent the subsequent formation of the nitride layer 104 ′ from causing damage to the surface of the semiconductor substrate 100. In a preferred embodiment, “this first oxide layer i 〇2, can be formed in the temperature of about 700 to i 丨 00C and oxygen-filled environment. In addition, it can also be formed by suitable oxides and their chemical combinations and procedures. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs As for the subsequent formation of the nitride layer 104 and the second oxide layer 106, they can be used as a mask layer for the subsequent lithography process and ion doping process. The 'nitride layer 104 can be about 400 to 450. The furnace is formed at ° C, and the reaction gases in the process are SiH4, 仏 〇 and NH3. As for the second oxide layer 106, silicon dioxide formed by chemical vapor deposition can be used. This chemical vapor phase The deposition enamel is made of TEOS at a temperature of 600 to 800 and a pressure of about 0_1 to 10 Torr. Into a desired oxide layer. In a preferred embodiment, the formed nitride layer 104 has a thickness of about 100 to 1900 angstroms. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm> Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of invention (), and the second oxide layer 106 has a thickness of about 800 to 1600 Angstroms. In addition, in one embodiment, the formed anti-reflection layer (ARC) 108 can be fabricated by using a silicon nitride material (SiNx) to effectively improve the lithographic resolution. 'The silicon nitride layer can be deposited using any suitable process. As is familiar to those skilled in the art, processes such as low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (pECVD) can be used. Obtained by deposition. Furthermore, the temperature at which the silicon nitride layer is formed is about 40 0-8 00¾. As for the reaction gas used to make the silicon nitride layer, SiH4, NH3, N2, N20 or SiH2Cl2, NH3, N2, N20 can be selected. Next, a photoresist layer 110 can be formed on the upper surface of the anti-reflection layer 108, where 'this photoresist layer 110' has three openings as shown in the fifth figure = then, use this light The resist layer 110 is used as an etching mask, and the anti-reflection layer 108 is subjected to an etching process to transfer the opening pattern to the anti-reflection layer 108. Then, as shown in the sixth figure, the second oxide layer 106, the nitride layer 104, and the first oxide layer 102 'are sequentially etched to form an opening pattern in the above layers, and a part of the semiconductor is exposed. The upper surface of the substrate 100. Among them, a part of the semiconductor substrate 100 exposed by the opening pattern is distributed to the PMOS region 101 and the NMOS region 103. In addition, after the etching process is completed, the photoresist layer 11 can be removed. In a preferred embodiment, a reactive ion etching (RIE) technique can be used to etch the nitrided layer and the oxide layer, and the etching agent for the nitrided layer can be selected from CF / H2, CHFS or CH3CHF2j for etching oxidation Layer etching agent, you can choose CC12F2, CHF3 / CF4, CHF / 〇, this paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) i '! _!'-! 1 ^ " ！ 1 Order !!! Line 1} * r · IJ wf Please read the notes on the back before filling this page)

91 92 V. Description of the invention (ch3chf2. Cf4 / 02〇 Then, referring to the seventh figure, a first photoresist layer 112 is formed on the semiconductor substrate 100 to cover the NMOS region 103. Next, the first photoresist is used The layer 112 and the second oxide layer 106 are used as a mask to perform an ion doping process on the semiconductor substrate 100, so that in the PM0S region 101, an exposed part of the surface of the semiconductor substrate 100 forms an n-type doped region. 114. It should be noted that this ion doping process is performed at a tilted angle, and is defined by the n-type doped region 114, except that it is formed on the exposed semiconductor substrate 100. In addition, it can also extend along the edge of the first oxide layer 102 to the semiconductor substrate 100 at the bottom of the first oxide layer 102. In a preferred embodiment, the n-type doped region described above 14 is formed using phosphorus or arsenic as a dopant. After completing the ion doping process, the first photoresist layer ιΐ2 is removed. Then, as shown in the eighth figure, a second photoresist layer U6 is also formed. The semiconductor substrate 100 is used to cover the PMOS region 101. Also, as described above By using the second photoresist layer 116 and the oxide layer 106 as a mask, an ion doping process is performed on the semiconductor substrate 100 so as to be covered by the second oxide layer 1 in the region ^ 3. 06 exposed part of the semiconductor substrate 100 surface to form a p-type doped region 1 8. Similarly, this ion doping process is also performed at a tilted angle to define the p-type The doped region 118 may extend along the edge of the first oxide layer 102 to the semiconductor substrate 100 below it. In a preferred embodiment, the p-type doped region ιΐ8 is --- ΓΙΙΙ1 --- ^ — "'4 -------- Order --------- line-2 (Please read the note § on the back before filling this page) Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the employee consumer cooperative 11 4391 92 Α7 Β7 V. Description of the invention () Use rotten or gasification touch as the substrate to form it. After completing the ion doping procedure, the second photoresist layer 1 1 6 is also moved After using the first photoresist layer 112 and the second photoresist layer 116 to define the n-type doped region 114 and the p-type doped region ιΐ8 on the surface of the semiconductor substrate, respectively, please refer to In the ninth figure, 'the second oxide layer I% and the nitride layer 104 are used as etching masks' to perform an etching process on the semiconductor substrate ιOO as shown by the arrow in the figure in order to form the trenches 120, 122, and On the semiconductor substrates in the PM0s region 101 and the NMOS region 103. In a preferred embodiment, the step of 'etching is to use an isotropi cal reactive ion etch (RIE) to Semiconductor substrate workers etched. In addition, when the semiconductor substrate 100 is composed of a silicon substrate, the melting agent used in this step may be selected from SiCl4 / Cl2, BC13 / Cl2, HBr / Cl2 / 〇2, HBr / 02, Br2 / SF4. SF6. Among them, because the foregoing ion doping process is performed at an inclined angle, the upper edge of the side wall of the trench 1 20 located in the PM OS region 101 is adjacent to the first oxide layer 102, and there is still some residual η Type doped region 114. As for the trench 122 located at the boundary between the PMOS region 101 and the NMOS region 103, it is located on the upper edge of the left half of the side wall in the PMOS region 101, as shown in the ninth figure. 4. Similarly, the upper edge of the side wall of the trench 124 in the NMOS region 103 is directly connected to the first oxide layer 102, and also has a partially remaining p-type doped region 118. In addition, the right half of the side wall of the trench I22 is located in the NM0S area 103, and the Chinese paper standard (CNS) A4 specification (210 x 297 public love) is applied to the upper edge of the paper. (Please read the precautions on the back before (Fill in this page) ------ I--Order ---- 111--line-- 'Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 4 3 ^ 1 92fi

V. Description of the invention () It is also a residual p-type doped region 118. (Please read the precautions on the back before filling this page.) Please refer to the tenth figure. After the trenches 120, i22, and 124 are defined in the conductor substrate 100, the first one on the surface of the semiconductor substrate 100 can be removed. The second oxide layer 106, the button layer 104, and the first oxide layer 102 are formed in shallow trench isolation structures 126, 128, and 130 in the trenches 120, 122, and 124. Generally, s' can use hot phosphoric acid to remove the residual nitrided layer 104, and hydrofluoric acid can be used to remove the first oxide layer 102 and the second oxide layer 100. As for the shallow trench isolation structure, it can be deposited by using thermal oxidation method or chemical oxygen phase deposition method, and then manufactured by chemical mechanical polishing (CMP). As shown in the eleventh figure, a third photoresist layer 132 may be further formed on the semiconductor substrate 100 to cover the NMOS region 103. And by using

An ion doping process having an inclined angle is defined, and an N. type well 1 34 is defined in the semiconductor substrate 100 in the pMOS region 101. After the completion of the ion doping process, the third photoresist layer 132 may be removed. Further, as shown in FIG. 12, j forms a fourth photoresist layer 136 to cover the pMOS region 101 on the semiconductor substrate. A p-type well 138 is formed in the semiconductor substrate 100 located in the NMOS region 103 by performing ion doping with an inclined angle. Same |

After the P-well 138 is formed, the fourth photoresist layer 136 is removed. —I Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Subsequently, as shown in the thirteenth figure, the polycrystalline silicon layer 140 and the polycrystalline silicide metal 142 are formed by using traditional technology to isolate structures in shallow trenches 丨

W6, 128, 130 and the semiconductor substrate 100 as the active area, set the paper size to apply Chinese National Standard (CNS) A4 specifications (210 X 297 mm) System 4391 92 A7 _ B7 V. Description of the invention () Defines the gate structure of the MOS transistor element. In addition, a silicon nitride layer 144 is formed on the surface of the semiconductor substrate 100, the polycrystalline silicon layer 140, and the polycrystalline silicon silicide metal 142 to be used as a barrier layer. Among them, it is located inside the pM0s region and is located For the active area between the shallow trench isolation structure 126 and 28, a PMOS transistor element can be formed. As for the active region within the nM0S region 103 and located between the shallow trench isolation structures 128 and 130, an NMOS transistor element is formed. It should be noted that, for PMOS transistor elements, since the edges of both sides of the active region have residual n-type doped regions, it is possible to effectively reduce the large number of concentrated active elements in the traditional process. The electricity at the edge of the area is% ', and the chance of leakage current occurring here is suppressed. That is, for a parasitic transistor that is green at the edge of the active region, due to the remaining n-type doped region 114, its effective starting voltage will be higher than that of the transistor element located in the center of the active region. Come higher. In this way, the sub-tbjeshold leakage phenomenon caused by the parasitic transistor adjacent to the shallow trench isolation structure in the traditional process can be effectively suppressed. Furthermore, as shown in the thirteenth figure, since the interface between the PMOS region 101 and the NMOS region 103 does not have any remaining n-type doped region 114 or p-type doped region 118, Therefore, the P-N junction will not cause leakage current due to the change of the energy gap. In particular, in the present invention, in order to reduce the leakage current at the edge of the active area and effectively suppress the occurrence of secondary leakage, the Chinese national standard (CNS) A4 specification (210 X 297 mm) is applied to this paper size. ) ---: 丨 丨 丨 丨 --- i — 5 --------- Order --------- line-}, (Please read the notes on the back before filling this page ) 43 91 92 A7 B7 V. Description of the Invention (PMOS region 101 (N-type well) edge of the active region, forming a ^ -type doped region 114. And, in the NMOS region 103 (p-type well) In the active region, the green region ^ forms a p-type doped region 118. However, for other components with specific requirements, the method of the present invention can also be used to form an n-type doped region in the NMOS region (that is, a p-type region). In the well), or to form a p-type doped region on the edge of the active region in the PMOS region (ie, the N-type well), and control the edge corner parasitic transistor by controlling the doping concentration of copper. ) Its starting voltage and the effect of controlling the amount of leakage current in between. Although the present invention is explained above with a preferred example, It is not intended to limit the spirit and the inventive substance of the present invention, but only to this embodiment. For those skilled in the art, "modifications made without departing from the spirit and scope of the present invention" should be included in the following Within the scope of patent application. (Please read the note on the back of the page before filling in this page.) The paper printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese National Standard (CNS) A4 (210 X 297 mm)- · -------- — — II --- II. --- JI 1.1 —— — — — — — — — —

Claims (1)

4391 92 Α8 Β8 C8 D8 Sixth, the Intellectual Property Bureau of the Ministry of Economic Affairs, the employee consumer cooperative printed a patent application scope κ A method of forming a trench isolation structure on a semiconductor substrate 'The method includes at least the following steps: Provide a semiconductor substrate, where the The semiconductor substrate can be divided into a first region and a second region, which are mutually similar; a mask layer is formed on the semiconductor substrate; the mask layer is etched to expose the first and second regions. Part of the upper surface of the semiconductor substrate; forming a first photoresist layer on the semiconductor substrate to cover the second region 'and exposing the first region; using the first photoresist layer and the single power layer as Masking, performing an ion doping procedure with an inclined angle on the semiconductor substrate to form a first doped region on the surface of the exposed semiconductor substrate, wherein the first doped region extends to the power layer In the semiconductor substrate at the bottom; removing the first photoresist layer; forming a second photoresist layer on the semiconductor substrate so as to cover the first area / area and exposing the second area; using the Two photoresist layers and the mask layer are used as mask layers, and an ion doping process with an inclined angle is performed on the half-body substrate to form a service area on the exposed part of the surface of the semiconductor substrate. The second doped plutonium region extends to the semiconductor substrate at the bottom of the mask layer; the second photoresist layer is removed; the mask layer is used as an etching power to perform a engraving process on the semiconductor substrate 'To remove part of the first doped region and part of the > miscellaneous region' and form a trench in the semiconductor substrate, which is adjacent to the high-powered paper standard applicable to the CNH standard (CNS ) A4 size (21〇x 297mm) {Please read the note f on the back before filling this page) 0_ ^ ί! I! I — II 1.)--Ί-Ι — ΙΓΙΙΙΙΙΙ—— —-4 3 9192 ^ b Co D8 6. On the sidewall of the trench at the bottom of the patent application scope, there are a portion of the first doped region and a portion of the second doped region; and a shallow trench isolation structure is formed in the trench. 2. The method according to item 1 of the scope of patent application, wherein the above-mentioned first area is a PMOS area used to define a PMOS device, and the second area is an NMOS area used to define an NMOS device. 3. The method according to item 2 of the patent application, wherein the first doped region is an n-type doped region and the second doped region is a p-type doped region. 4. For the method of claim 3, the above-mentioned n-type doped region is formed using phosphorus or arsenic as a dopant, and the p-type doped region is formed using boron or boron difluoride as a dopant. Qualitatively. 5. The method according to item 2 of the patent application park, wherein the first doped region is a p-type doped region and the second doped region is an n-type doped region. 6. The method of claim 5 in which the above-mentioned n-type doped region is formed using phosphorous or arsenic as a dopant, and the P-type doped region uses boron or boron difluoride as a dopant. And formed. 7. For the method of applying for the first item of the patent scope, in which the above paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau, "..V ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 i * J_ I 1 1. ^ 1« ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 43 9192 A8 B8 C8 D8. 6. The patent application Fanyuan layer is a composite layer of a nitride material and an oxide material. Semiconductor: bottom: application: patent The method of the first item of the scope, * The above-mentioned method of touching the semiconductor material < step 'is performed by using an anisotropic embedding process. Then, the method of the first item of 9 :: China Patent Patent Park, Among them, the semiconductor hemp ^^ .. ^ ^ in the above-mentioned region has an N_ 丼 region, and the semiconductor substrate in the second region has a p-well region. 1．If a patent is applied for The square enamel of item 9, wherein the above-mentioned first doped region is an n-type doped region formed using phosphorus or god as a substrate; ^ -doped region is the use of boron or boron difluoride Make A p-type doped region formed for doping. Π. The method according to item 9 of the scope of patent application, wherein the first doped region is a mouth-type dopant formed using boron or boron difluoride as a dopant. Impurity region, and the second doped region is an n-type doped region formed using phosphorus or arsenic as a dopant. 12. A method for forming a trench isolation structure on a semiconductor substrate, the method includes at least the following Step 提供: Provide a semiconductor substrate, wherein the semiconductor substrate can be distinguished into a PMOS region and an NMOS region adjacent to each other, and the pMOS region is used to define a PMOS element, and the NMOS region is used to define an NMOS element; Form a nitride layer on the semiconductor substrate and cover the PMOS area. The paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)- III 1 III «— — — — 111 I 1) / · — I ί Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperatives of the Ministry of Economic Affairs, printed by the Consumers' Cooperative of the Ministry of Economic Affairs, printed by umr i. Forming an oxide layer on the nitride layer; contacting the gasification layer and the oxide layer to form an opening pattern in the gasification layer and the tritium layer, and exposing the PMOS region located in the PMOS region; And the upper surface of the semiconductor substrate with a portion in the NMOS region; a person forms a first photoresist layer on the semiconductor substrate and the oxide layer to cover the NMOS region and expose the pMOS region; use The first photoresist layer and the oxide layer are used as a mask to perform an ion doping process on the semiconductor substrate, so as to form an n-type doped region on a part of the semiconductor substrate exposed in the PMOS region, where the ions The doping process is performed at an oblique angle so that the n-type doped region can extend into the semiconductor substrate at the bottom of the nitride layer; remove the first photoresist layer; and form a second photoresist layer on the semiconductor Over the substrate and the oxide layer to cover the PMOS region and expose the NMOS region; use the first photoresist layer and the oxide layer as a mask to perform an ion doping process on the semiconductor substrate to form P-type doped region exposed in NMOS region Part of the semiconductor substrate, wherein the ion doping process is performed at an inclined angle so that the P-type doped region can extend into the semiconductor substrate at the bottom of the hydrogenation layer; remove the second photoresist layer ; Using the oxide layer as an etching mask to perform a engraving process on the semiconductor substrate so as to remove the n-type doped region and the p-type doped region that are not covered by the nitride layer, and form a trench at The PMOS area and the 19 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (21〇X 297 Gongchu)-, 11: -2 -------- Order --------- Line (Please read the precautions on the back before filling this page) A8B8C8D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. The semiconductor underpayment in the NMOS area of the patent application, which is located on the side wall of the trench in the PMOS area The upper edge has a partially residual n-type doped region, and the upper edge of the trench sidewall in the NMO S region has a partially residual p-type doped region; and a shallow trench isolation structure is formed in the trench. . I3. The method according to item I2 of the patent application scope, wherein before forming the nitrided layer, it further comprises forming a first oxide layer on the surface of the semiconductor substrate to prevent the nitrided layer from causing damage to the surface of the semiconductor substrate. 14. The method according to item 12 of the patent application park, wherein before etching the nitride layer and the oxide layer, the following steps are further included: forming an anti-reflection layer on the oxide layer to improve the lithographic resolution And forming a photoresist layer on the anti-reflection layer, wherein the photoresist layer has an opening for defining a trench pattern. 15. The method according to item 12 of the patent application park, wherein the aforementioned p-type doped region is formed using boron or boron difluoride as a dopant. 16 ♦ The method according to item 12 of the patent application park, wherein the n-type doped region is formed by using phosphorus or crushing as a dopant. 20 This paper size applies to China National Standard (CNS) A4 specifications < 210 X 297 public love) (Please read the precautions on the back before filling this page)-!!! 1 Order -------- I . '! I