TW316329B - Manufacturing method of field effect transistor with titan silicide shallow junction and narrow gate - Google Patents

Abstract

A manufacturing method of field effect transistor comprises of: on silicon semiconductor wafer forming oxide needed by isolating field effect transistor; (1) forming one metal, first polysilicon and first dielectric; (2) by photolithography technology forming photoresist pattern with first opening, in which the above first opening is located on the position prepared to be used as field effect transistor gate; (3) in plasma etching chamber on the above first opening sidewall forming non-volatile polymer spacer, and second opening for making the above first opening become smaller; (4) with the above photoresist pattern as mask etching the above first dielectric, first polysilicon and metal to form third opening; (5) removing the above photoresist pattern; (6) on the above third opening sidewall forming dielectric spacer; (7) forming gate oxide; (8) in the above third opening performing channel doping; (9) forming one second polysilicon, and by photolithography and etch technology etching the above second polysilicon to form field effect transistor gate.

Description

316329 A7 B7

sr / ^ > 7 V. Description of the invention () (―). Field of the invention The present invention relates to a metal oxide semiconductor field effect transistor (MOSFET) with a shallow junction of titanium silicide and a narrow gate Manufacturing method. (2) Background of the invention Now, the traditional method of manufacturing a gold-oxygen half field effect transistor will be described using FIGS. Initially, the field oxide required for isolating the metal oxide semi-field effect transistor 52 was formed on the P-type sand semiconductor wafer 52 (silicon semiconductor wafer). Next, the gate oxide layer 54 ′ of the metal-oxide-half field-effect transistor is formed as shown in FIG. 1 and the channel junction 55 of the metal-oxide-half field-effect transistor is connected to form a doped region 50 as shown in FIG. 2 'To adjust the threshold voltage (Threshold Voltage) of the metal oxide semi-field effect transistor. Then, a layer of polycrystalline silicon 58 is deposited, and the polycrystalline silicon is etched away using photolithography technology and electro-etching etching technology to form a gate electrode 58 of a gold-oxygen half-field effect transistor, as shown in FIG. 3. Next, an N · lightly doped source / drain electrode 60 ′ is formed as shown in FIG. 4, then a layer of sand dioxide 62 is deposited, and the silicon dioxide is vertically etched back unidirectionally, so that Silicon dioxide sidewalls 62 are formed on both sides of the gate 58 as shown in FIG. 5. Finally, the ion implantation is used to form the N + densely doped source / drain 64, as shown in FIG. 6, to complete the fabrication of the metal oxide half-field effect transistor. However, the "channel doping 55" covers the entire silicon semiconductor wafer 52, and when entering the deep submicron field, the doping concentration of the "channel doping 55" must be very high, which will cause the entire silicon semiconductor crystal An increase in the doping concentration of circle 52 leads to an increase in junction leakage and junction capacitance of the metal oxide semi-field effect transistor, which deteriorates the characteristics of the metal oxide semi-electrode 3. Brief description of the invention. Du Yin 31, Beigong Consumer Cooperation of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs (please first read the "note" item on the back and then fill this page). The main purpose of the present invention is to provide a shallow contact The manufacturing method of metal oxide semi-field transistors with flat and narrow gates. Another object of the present invention is to provide a method for manufacturing a metal oxide half field effect transistor with low junction leakage and low junction capacitance. The main method of the present invention is as follows. First, the field oxide layer required to isolate the metal oxide half-field effect transistor is formed on the silicon semiconductor wafer. Next, form a layer of titanium, first polycrystalline silicon and silicon nitride, and use non-volatile polymer sidewalls to form a wide paper size. Applicable to China National Crushing Rate (CNS) A4 specification (210X297 mm) H3 degree is less than micro Openings of the "Analysis Limit" (The openings) are prepared as gate positions. Then, a photoresist pattern is formed using photolithography technology, and the silicon nitride, the first polycrystalline silicon and titanium are etched away using the photoresist pattern as a shield, and the photoresist pattern is removed. Next, 'dielectric spacers are formed on the sides of the opening.' Next, a gate oxide layer is formed on the surface of the silicon semiconductor wafer in the opening, and "channel doping" is performed in the opening . Finally, a layer of second polycrystalline silicon is formed, and the second polycrystalline silicon is etched away using lithography technology and plasma etching technology to form a field electrode transistor. A metal oxide semi-field transistor with a shallow junction of titanium silicide 'low junction leakage and low junction capacitance is completed in Yan. (4). Brief description of the figures Figures 1 to 6 are schematic cross-sectional views of the manufacturing process of the traditional method for manufacturing metal oxide half field effect transistors. 7 to 17 are schematic cross-sectional views of the manufacturing process of an embodiment of the present invention. (V). Detailed description of the invention The following is a description of the method of the present invention using N-channel metal-oxide half field effect transistor (NMOSFET), but the method of the present invention can be extended to P-channel metal-oxide half field effect transistor (PMOSFET) and Manufacture of Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET). Please refer to Figure 7 now. First, a conventional local silicon oxide (LOCOS) is used to form an oxide layer 4 required on the P-type silicon semiconductor wafer 2 to isolate the N-channel metal oxide half field effect transistor, as shown in FIG. 7. The thickness of the oxide layer 4 is between 3000 angstroms and 6000 angstroms. The oxide layer 4 can also be formed using the conventional shallow trench isolation (STI) technique. Printed by the Beigong Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs. Now please refer to Figures 8 and 9. Next, a layer of titanium 6 is formed, as shown in FIG. 8, and then a layer of first polycrystalline silicon 8 and silicon nitride 10 is formed, as shown in FIG. The "Titanium 6" is usually formed by sputtering technology, and its thickness is between 200 and 400 angstroms. The "first polycrystalline silicon 8" is formed by the in-situ phosphorus doped technique of phosphorus atoms. Its reaction principle is low-pressure chemical vapor deposition. The reaction gas is a mixed gas of PH3, SiH4 and N2. The reaction temperature is between 525 and 575 t. Its ion impurity concentration is between 1E20 and 1E22 atoms / cm3, and its thickness is between 1000 and 3000 Angstroms. The "silicon nitride 10" is also usually formed by low-pressure chemical vapor deposition. The reaction gas is a mixed gas of SiCl2H2 and NH3, and its thickness is between 500 and 1000 angstroms. Now please refer to Figs. 10 and 11 ". Next, a photoresist pattern 12 is formed by using lithography technology, and the photoresist pattern 12 is formed with an opening 13A 'as shown in FIG. Then, place the "P-type sand semiconductor wafer 2" into the plasma etching reaction chamber, and use the reaction gas and the photoresist pattern 12 in the plasma etching reaction chamber to apply the national piano-like standard (CNS) A in the application of the paper standard. 4 Specifications (210 X 297 mm) 316329 H3 The side wall of the "opening 13A" forms a non-volatile polymer sidewall spacer 14 (non-volatile polymer sidewall spacer), so that the width of the "opening 13A" becomes smaller as the "opening As shown in Figure i, if the width of the "opening 13A" is equal to the lithographic analysis limit, the width of the "opening 13B" will be smaller than the lithographic analysis limit. Please note that the positions of the "opening 13A" and "opening 13B" are prepared as the positions of the metal oxide half field effect transistor gates. Please note that the "non-volatile polymer sidewall material. H" is mainly composed of hydrocarbons containing silicon and fluorine. We control the flow by controlling the gas flow in the plasma etching reaction chamber. The width of the non-volatile polymer sidewall 14 ". Now please refer to Figure 12 and Figure 13. Then, using the "photoresist pattern 12" as an etching shield, the silicon nitride 10 'first polycrystalline silicon 8 and titanium 6 are etched away, as shown in FIG. Next, the "photoresist pattern 12" and the "non-volatile polymer sidewall material 14" are removed to form an "opening 13C", as shown in FIG. Please note that the width of "Opening 13C" is less than the lithography resolution limit. Generally, the "photoresist pattern 12" and the "non-volatile polymer sidewall material 14" are removed using oxygen plasma and sulfuric acid solution. For the plasma etching of the silicon nitride 10, the first polycrystalline silicon 8 and the titanium 6, magnetic field enhanced active ion plasma uranium etching technology (MERIE) or electron cyclotron resonance plasma etching technology (ECR) can be used. Or is it the traditional active ion plasma etching technology (RIE), in the field of sub-micron technology or deep sub-micron field, generally using magnetic field enhanced active ion plasma etching, the plasma reaction gas is SF6 and HBr and other gases . Please note that the "first polycrystalline silicon 8" is used as an N-type impurity diffusion source. In the subsequent high temperature step, the phosphorus atoms in the "first polycrystalline silicon 8" will be driven into the "P-type silicon 8" The semiconductor wafer is used to form the source and drain of the N-channel metal oxide semi-field effect transistor (NMOSFET), and the junction depth of the formed source and drain can be less than 0.1 microns. Generally, in a passive gas environment, The driving temperature of the high-temperature driving step is between 800 and 900 ° C, and the driving time is between 10 and 30 minutes. The Employee Welfare Committee of the Central Sample Bureau of the Ministry of Economic Affairs will print the «. Now please refer to the figure 14. Next, a dielectric layer 16 is formed, and the "dielectric layer 16" is unidirectionally etched back to form a dielectric layer sidewall 16 on the side of the "opening 13 (:" (dielectric spacer), as shown in Figure 14. The "dielectric layer 16" is usually a non-doped silicon dioxide formed by low-pressure chemical vapor deposition, and the reaction gas is TetraEthOxySilane ; TE0S) or silane (silane), the reaction temperature is about 720 ° C, the reaction pressure is between 0.2 and 0.4 Torr , The thickness is between 500 and 1500 angstroms. The plasma etching of the "dielectric layer 16" can use magnetic field enhanced active ion plasma etching technology or electron cyclotron resonance plasma etching technology, or it is traditional Active ion type electric award etching technology, in the field of sub-micron technology or deep sub-micron field, generally uses magnetic field enhanced active ion plasma etching, the plasma reaction gas is CF4 and CHF3 and other fluorine gas with a small amount of argon Gas. Now please refer to Figures 15 and 16. Next, a gate oxide layer I8 of a metal oxide half field effect transistor is formed in the "opening 13C" as shown in Figure 15. Then, the nitride Silicon 10, the first polycrystalline silicon 8 and titanium 6 are used as the ion implantation protection cover, and the ion implantation technique is used to perform channel doping 20 'in the "opening nc" to form the doped region 22, as shown in FIG. In order to adjust the threshold voltage of the N-channel gold-oxygen half field effect transistor. In addition to the threshold voltage ion implantation, it can also be applied to the national standard (CNS) A4 specification (210X) of this paper scale. (297 male dreams) H3 Deep ion implantation (deep implantation) is performed to prevent the punch-through effect of the N-channel gold-oxygen half-field effect transistor. The gate oxide layer 18 thermally oxidizes the "P type" in a high-temperature environment containing oxygen It is formed by the silicon atoms on the surface of the silicon semiconductor wafer 2 ", whose oxidation temperature is between 850 and 950 ° C, and its thickness is between 100 and 200 Angstroms. The ion channel of the" channel doping " The ion species is usually boron atoms. Now please refer to FIG. 17. Finally, a layer of second polycrystalline silicon 30 is formed, and the second polycrystalline silicon 30 is etched away using lithography and plasma etching techniques to form The gate electrode of the field effect transistor is shown in Figure 17. A metal oxide semi-field transistor with a shallow junction of titanium silicide 'low junction leakage and low junction capacitance was completed in Yan. The "second polycrystalline silicon 30" is also formed by the synchronous impurity exchange technology of phosphorus atoms. The reaction principle is low-pressure chemical vapor deposition. The reaction gas is a mixed gas of PH3, SitU and N2. The reaction temperature is between 525. At 575 ° C, the concentration of ionic impurities is between 1E20 and 1E22 atoms / f /: cm, and its thickness is between 2000 and 3500 Angstroms. The plasma etching of the "second polycrystalline silicon 30" also uses the magnetic field enhanced active ion plasma etching technology, and the plasma reaction gases are Cl2, 〇2 and HBr gas 0 to complete the N-channel gold oxygen After the fabrication of the half-field effect transistor, a standard process is used to form the contact window 'first-layer metal connection, via hole (ViaHole) and second-layer metal connection to form an N-channel metal oxide half-field transistor volume circuit . The first layer of metal connection is usually made of titanium, titanium nitride, tungsten and aluminum alloy, and the first layer of metal connection contains a metal plug (metal plug) and crosses the contact window Make electrical contact with the source / drain of the gold-oxide half-field effect transistor. The second-layer metal connection is usually made of titanium, titanium nitride, tungsten, and aluminum alloy, and the second-layer metal connection contains a metal plug and crosses the via hole and the The first layer of metal wiring makes electrical contact. The above uses the best embodiments to explain the present invention, not to limit the present invention, and anyone skilled in semiconductor technology can understand that appropriate changes and adjustments will still lose the essence of the present invention, nor Departs from the spirit and scope of the present invention. Printed by the Beigong Welfare Committee of the Central Prototype Bureau of the Ministry of Thread Economy. This paper ruler is applicable to China National Standards (CNS) A4 regulation private (Ϊ21〇X 297

Claims (1)

A8 B8 C8 _____ · D8 VI. Scope of patent application 1-Method for manufacturing field effect transistors, including: f oxide layer needed to form isolated field effect transistors on silicon semiconductor wafer; & A polycrystalline silicon and the first dielectric layer; photolithography technology to form a photoresist pattern with a "first-opening", the position of the "first-opening" is prepared as a position of the field effect transistor gate; The "non-volatile polymer sidewall material" is formed on the side wall of the "first opening" in the etching reaction chamber to reduce the width of the "first opening" to become the "second opening"; The pattern is that the shield etched away the first dielectric layer, the first polycrystalline silicon and the metal to form a "third opening";-the photoresist pattern was removed;-formed on the side of the "third opening" Dielectric spacer (dielectricspacer); forming a gate oxide layer; in the "third opening". "Channel miscellaneous"; forming a layer of second polycrystalline silicon, and using lithography and etching techniques to etch away The second polycrystalline silicon is used to form the gate of the field effect transistor. 2. The method as claimed in item 1 of the patent application, wherein the metal refers to titanium, the thickness of which is between 200 and 400 angstroms. 3. The method as claimed in item 1 of the patent application, wherein the thickness of the "first polycrystalline silicon" is between 1000 and 3000 angstroms. 4. The method as claimed in item 1 of the patent application, wherein the "first dielectric layer" refers to nitrided sand with a thickness between 500 and 1000 angstroms. 5. The method as claimed in item 1 of the patent scope, wherein the "dielectric layer sidewall material" is composed of non-doped silicon dioxide, and the plasma-etching technique is used to perform the "doped silicon dioxide j" It is formed by vertical unidirectional etch back. 6. As in the method of patent application item 1, the thickness of the gate oxide layer is between 100 and 200 angstroms.. 7. As in the patent application item 1 Method, wherein the thickness of the second polycrystalline silicon layer is between 2000 and 3500 angstroms. 8. The method as claimed in item 1 of the patent application, wherein the method of forming a "third opening" is known Lithography technology and plasma etching technology, and the plasma etching technology refers to magnetic field enhanced active ion plasma etching technology or electron cyclotron resonance plasma etching technology or traditional active ion type electric award etching technology. * 316329 (please read the note $ item on the back and then this page) ni — ^ n 1 ^ 1 1 ^ 1 _ Order the paper size of the printed version of the Central Consortium Bureau of the Ministry of Economic Affairs Beigong Consumer Cooperative for easy use. Knead half (CNS) A4 specification (210 X297mm)